CMOS IC
Under Development
Ver:1.01
80901
SYSTEM-BIZ Div. S. Kubota 1/26
8-Bit Single Chip Microcontroller
LC876764A/48A
LC876764A
8 bit Single Chip Microcontroller incorporating 64KB ROM and 1536 byte RAM on chip
LC876748A
8 bit Single Chip Microcontroller incorporating 48KB ROM and 1536 byte RAM on chip
Overview
The LC876764A/LC876748A are 8 bit single chip microcomputers with the following on-chip functional
blocks:
- CPU: operable at a minimum bus cycle time of 100ns
- On-chip ROM Maximum Capacity : LC876764A
64K bytes
LC876748A
48K
bytes
- On-chip RAM: 1536 bytes
- VFD automatic display controller / driver
- 16 bit timer / counter (can be divided into two 8 bit timers)
- 16 bit timer / PWM (can be divided into two 8 bit timers)
- four 8 bit timer with prescaler
- timer for use as date / time clock
- High speed clock counter
- System clock divider function
- synchronous serial I/O port (with automatic block transmit / receive function)
- asynchronous / synchronous serial I/O port
- 14-channel 8-bit AD converter
- Weak signal detector
- 21-source 10-vectored interrupt system
All of the above functions are fabricated on a single chip.
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Features
(1) Read-Only Memory (ROM): LC876764A 65536 8 bits
LC876748A
49152 8 bits
(2) Random Access Memory (RAM): LC876764A/48A
1536 9 bits
(3) Minimum Bus Cycle Time: 100ns (10MHz)
Note: The bus cycle time indicates ROM read time.
(4) Minimum Instruction Cycle Time: 300ns (10MHz)
(5) Ports
- Input/output ports
Data direction programmable for each bit individually : 20 (P1n, P70 to P73, P8n)
- 15V withstand input/output ports
Data direction programmable in nibble units :
8 (P0n)
(When N-channel open drain output is selected, data can be input in bit units.)
Data direction programmable for each bit individually : 8 (P3n)
- Input ports :
2 (XT1,XT2)
- VFD output ports
Large current outputs for digits :
9 (S0 / T0 to S8 / T8)
Large current outputs for digits / segments :
7 (S9 / T9 to S15 / T15)
digit / segment outputs :
8 (S16 to S23)
segment outputs :
28 (S24 to S51)
Other functions
Input/output ports :
12(PFn, PG0 to 3)
Input ports :
24 (PCn, PDn, PEn)
- Oscillator pins :
2 (CF1,CF2)
- Reset pin :
1 (RES#)
- Power supply :
6 (VSS1 to 2, VDD1 to 4)
(6) VFD automatic display controller
- Programmable segment/digit output pattern
Output can be switched between digit/segment waveform output (pins 9 to 24 can be used for
output of digit waveforms).
parallel-drive available for large current VFD.
- 16-step dimmer function available
(7) Weak signal detection (MIC signals etc)
- Counts pulses with width greater than a preset value
- 2 bit counter
(8) Timers
- Timer 0: 16 bit timer / counter with capture register
Mode 0: 2 channel 8-bit timer with programmable 8 bit prescaler and 8 bit capture register
Mode 1: 8 bit timer with 8 bit programmable prescaler and 8 bit capture register + 8 bit
Counter with 8-bit capture register
Mode 2: 16 bit timer with 8 bit programmable prescaler and 16 bit capture register
Mode 3: 16 bit counter with 16 bit capture register
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- Timer 1: PWM / 16 bit timer toggle output
Mode 0: 2 channel 8 bit timer (with toggle output)
Mode 1: 2 channel 8 bit PWM
Mode 2: 16 bit timer (with toggle output) Toggle output also possible using lower order 8 bits.
Mode 3: 16 bit timer (with toggle output) Lower order 8 bits can be used as PWM output.
- Timer 4: 8 bit timer with 6 bit prescaler
- Timer 5: 8 bit timer with 6 bit prescaler
- Timer 6: 8 bit timer with 6 bit prescaler
- Timer 7: 8 bit timer with 6 bit prescaler
- Base Timer
1) The clock signal can be selected from any of the following.
Sub-clock (32.768kHz crystal oscillator), system clock, and prescaler output from timer 0
2) Interrupts can be selected to occur at one of five different times.
(9) High speed clock counter
1) Capable of counting maximum: 20MHz clock (Using main clock 10MHz)
2) Real time output
(10) Serial-interface
- SIO 0: 8 bit synchronous serial Interface
1) LSB first / MSB first function available
2) Internal 8 bit baud-rate generator (maximum transmit clock period 4 / 3 Tcyc)
3) Continuous automatic data communication (1-256 bits)
- SIO 1: 8 bit asynchronous / synchronous serial interface
Mode 0: Synchronous 8 bit serial IO (2-wire or 3-wire, transmit clock 2512 Tcyc)
Mode 1: Asynchronous serial IO (half duplex, 8 data bits, 1 stop bit, baud rate 82048Tcyc)
Mode 2: Bus mode 1 (start bit, 8 data bits, transmit clock 2512 Tcyc)
Mode 3: Bus mode 2 (start detection, 8 data bits, stop detection)
(11) AD converter
-8 bits 14 channels
(12) Remote control receiver circuit (connected to P73 / INT3 / T0IN terminal)
-Noise rejection function (noise rejection filter time constant can selected from 1 / 32 / 128 Tcyc)
(13) Watchdog timer
- The watching timer period is set using an external RC.
- Watchdog timer can produce interrupt, system reset
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(14) Interrupts: 21-source, 10-vectored interrupts
1) Three priority (low, high and highest) multiple interrupts are supported. During interrupt handling,
an equal or lower priority interrupt request is refused.
2) If interrupt requests to two or more vector addresses occur at once, the higher priority interrupt takes
precedence. In the case of equal priority levels, the vector with the lowest address takes
precedence.
No. Vector
Selectable
Level
Interrupt
signal
1
00003H
X or L
INT0
2
0000BH
X or L
INT1
3
00013H
H or L
INT2/ T0L/ INT4
4
0001BH
H or L
INT3/ Base timer/ INT5
5
00023H
H or L
T0H
6
0002BH
H or L
T1L/ T1H
7
00033H
H or L
SI00
8
0003BH
H or L
SI01
9
00043H
H or L
ADC/ MIC/ T6/ T7
10
0004BH
H or L
VFD automatic display controller/ Port0/ T4/ T5
Priority Level: X>H>L
For equal priority levels, vector with lowest address takes precedence.
(15) Subroutine stack levels: 768 levels max. Stack is located in RAM.
(16) Multiplication and division
- 16 bit 8 bit (executed in 5 cycles)
- 24 bit 16 bit (12 cycles)
- 16 bit 8 bit (8 cycles)
- 24 bit 16 bit (12 cycles)
(17) Oscillation circuits
- On-chip RC oscillation circuit for system clock use.
- On-chip CF oscillation circuit for system clock use. (R
f
built in)
- On-chip Crystal oscillation circuit low speed system clock use. (Rd, R
f
external)
- On-chip frequency -variable RC oscillation circuit for system clock use
(18) System clock divider function
- Able to reduce current consumption
Available minimum instruction cycle time: 300ns, 600ns, 1.2s, 2.4
s, 4.8s, 9.6s, 19.2s,
38.4s, 76.8s. (Using 10MHz main clock)
(19) Standby function
- HALT mode
HALT mode is used to reduce power consumption. Program execution is stopped. Peripheral
circuits still operate but VFD display and some serial transfer operations stop.
1) Oscillation circuits are not stopped automatically.
2) Release occurs on system reset or by interrupt.
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-HOLD mode
HOLD mode is used to reduce power consumption. Both program execution and peripheral
circuits are stopped.
1)CF, RCand crystal oscillation circuits stop automatically.
2) Release occurs on any of the following conditions.
(1) input to the reset pin goes low
(2) a specified level is input at least one of INT0, INT1, INT2, INT4, INT5
(3) an interrupt condition arises at port 0
-X'tal HOLD made
X'tal HOLD mode is used to reduce power consumption. Program execution is stopped.
All peripheral circuits except the base timer are stopped.
1) CF and RC oscillation circuits stop automatically.
2) Crystal oscillator is maintained in its state at HOLD mode inception.
3) Release occurs on any an any of the following conditions
(1) input to the reset pin goes low
(2) a specified level is input to at least one of INT0, INT1, INT2, INT4, INT5
(3) an interrupt condition arises at port 0
(4) an interrupt condition arises at the base-timer
(20) Factory shipment
-delivery form QIP100E
(21) Development tools
- Evaluation chip: LC876093
- Emulator: EVA62S + ECB876600 (Evaluation chip board) + SUB876700 + POD100QFP
: ICE-B877300 + SUB876700 + POD100QFP
- Flash ROM version: LC87F67C8A
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