LC877448A/40A/32A/24A
No.7776-2/22
Features
(1) Read-Only Memory (ROM)
49152 8 bits (LC877448A)
40960 8 bits (LC877440A)
32768 8 bits (LC877432A)
24576 8 bits (LC877424A)
(2) Random Access Memory (RAM): 1536 9 bits (LC877448A, LC877440A, LC877432A, LC877424A)
(3) Minimum Bus Cycle Time: 100 ns (10MHz)
Note: The bus cycle time indicates ROM read time.
(4) Minimum Instruction Cycle Time: 300 ns (10MHz)
(5) Ports
Input / output ports
Data direction programmable for each bit individually:
26 (P1n, P30 to P35, P70 to P73, P8n)
Data direction programmable in nibble units:
8 (P0n)
(When N-channel open drain output is selected, data can be input in bit units.)
Input ports:
2 (XT1, XT2)
LCD ports
Segment output:
48 (S00 to S47)
Common output:
4 (COM0 to COM3)
Bias terminals for LCD driver:
3 (V1 to V3)
Other functions
Input / output ports:
48 (PAn, PBn, PCn, PDn, PEn, PFn)
Input ports:
7 (PLn)
Oscillator pins:
2 (CF1, CF2)
Reset pin:
1 (RES)
Power supply:
6 (VSS1 to 3, VDD1 to 3)
(6) LCD controller
Seven display modes are available (static, 1/2, 1/3, 1/4 duty 1/2, 1/3 bias)
Segment output and common output can be switched to general purpose input / output ports.
(7) Small signal detection (MIC signals etc)
Counts pulses with the level which is greater than a preset value
2 bit counter
(8) Timers
Timer 0: 16 bit timer / counter with capture register
Mode 0: 2 channel 8 bit timer with programmable 8 bit prescaler and 8 bit capture register
Mode 1: 8 bit timer with 8 bit programmable prescaler and 8 bit capture register + 8 bit
counter with 8 bit capture register
Mode 2: 16 bit timer with 8 bit programmable prescaler and 16 bit capture register
Mode 3: 16 bit counter with 16 bit capture register
Timer 1: PWM / 16 bit timer / counter with toggle output function
Mode 0: 8 bit timer (with toggle output) + 8 bit timer / counter (with toggle output)
Mode 1: 2 channel 8 bit PWM
Mode 2: 16 bit timer / counter (with toggle output) Toggle output from lower 8 bits is also possible.
Mode 3: 16 bit timer (with toggle output) Lower order 8 bits can be used as PWM.
Timer 4: 8 bit timer with 6 bit prescaler
Timer 5: 8 bit timer with 6 bit prescaler
Timer 6: 8 bit timer with 6 bit prescaler
Timer 7: 8 bit timer with 6 bit prescaler
Continued on next page.
LC877448A/40A/32A/24A
No.7776-3/22
Continued from preceding page.
Base Timer
1) The clock signal can be selected from any of the following:
Sub-clock (32.768kHz crystal oscillator), system clock, and prescaler output from timer 0
2) Interrupts of five different time intervals are possible.
(9) High-speed clock counter
Countable up to 20MHz clock (when using 10MHz main clock)
Real time output
(10) Serial-interface
SIO 0: 8 bit synchronous serial interface
1) LSB first / MSB first is selectable
2) Internal 8 bit baud-rate generator (fastest clock period 4 / 3 tCYC)
3) Consecutive automatic data communication (1 to 256 bits)
SIO 1: 8 bit asynchronous / synchronous serial interface
Mode 0: Synchronous 8 bit serial IO (2-wire or 3-wire, transmit clock 2 to 512 tCYC)
Mode 1: Asynchronous serial IO (half duplex, 8 data bits, 1 stop bit, baud rate 8 to 2048 tCYC)
Mode 2: Bus mode 1 (start bit, 8 data bits, transmit clock 2 to 512 tCYC)
Mode 3: Bus mode 2 (start detection, 8 data bits, stop detection)
(11) AD converter
8 bits 15 channels
(12) Remote control receiver circuit (connected to P73 / INT3 / T0IN terminal)
Noise rejection function (noise rejection filter's time constant can be selected from 1 / 32 / 128 tCYC)
(13) Watchdog timer
The watching time period is determined by an external RC.
Watchdog timer can produce interrupt or system reset
(14) Interrupts: 20 sources, 10 vectors
1) Three priority (low, high and highest) multiple interrupts are supported.
During interrupt handling, an equal or lower priority interrupt request is postponed.
2) If interrupt requests to two or more vector addresses occur at once, the higher priority interrupt takes precedence.
In the case of equal priority levels, the vector with the lowest address takes precedence.
No.
Vector
Selectable level
Interrupt signal
1
00003H
X or L
INT0
2
0000BH
X or L
INT1
3
00013H
H or L
INT2 / T0L / INT4
4
0001BH
H or L
INT3 / Base timer / INT5
5
00023H
H or L
T0H
6
0002BH
H or L
T1L / T1H
7
00033H
H or L
SIO0
8
0003BH
H or L
SIO1
9
00043H
H or L
ADC / MIC / T6 / T7
10
0004BH
H or L
Port 0 / T4 / T5
Priority Level: X > H > L
For equal priority levels, vector with lowest address takes precedence.
(15) Subroutine stack levels: 768 levels max. Stack is located in RAM.
(16) Multiplication and division
16 bit 8 bit (executed in 5 cycles)
24 bit 16 bit (12 cycles)
16 bit 8 bit (8 cycles)
24 bit 16 bit (12 cycles)
LC877448A/40A/32A/24A
No.7776-4/22
(17) Oscillation circuits
On-chip RC oscillation for system clock use.
CF oscillation for system clock use. (Rf built in, Rd external)
Crystal oscillation low speed system clock use. (Rf built in, Rd external)
On-chip frequency variable RC oscillation circuit for system clock use.
(18) System clock divider
Low power consumption operation is available
Minimum instruction cycle time (300ns, 600ns, 1.2
s, 2.4
s, 4.8
s, 9.6
s, 19.2
s, 38.4
s, 76.8
s can be
switched by program (when using 10MHz main clock)
(19) Standby function
HALT mode
HALT mode is used to reduce power consumption. During the HALT mode, program execution is stopped but
peripheral circuits keep operating (some parts of serial transfer operation stop.)
1) Oscillation circuits are not stopped automatically.
2) Released by the system reset or interrupts.
HOLD mode
HOLD mode is used to reduce power consumption. Program execution and peripheral circuits are stopped.
1) CF, RC and crystal oscillation circuits stop automatically.
2) Released by any of the following conditions.
(1) Low level input to the reset pin
(2) Specified level input to one of INT0, INT1, INT2, INT4, INT5
(3) Port 0 interrupt
X'tal HOLD mode
X'tal HOLD mode is used to reduce power consumption. Program execution is stopped.
All peripheral circuits except the base timer are stopped.
1) CF and RC oscillation circuits stop automatically.
2) Crystal oscillator operation is kept in its state at HOLD mode inception.
3) Released by any of the following conditions
(1) Low level input to the reset pin
(2) Specified level input to one of INT0, INT1, INT2, INT4, INT5
(3) Port 0 interrupt
(4) Base-timer interrupt
(20) Package
QIP100E
TQFP100
(21) Development tools
Evaluation chip: LC876093
Emulator: EVA62S + ECB876600 (Evaluation chip board) + SUB877400 + POD100QFP or
POD100SQFP (Type B)
: ICE-B877300 + SUB877400 + POD100QFP or POD100SQFP (Type B)
Flash ROM version: LC87F74C8A
LC877448A/40A/32A/24A
No.7776-5/22
Pin Assignment
S20/PC4
S19/PC3
S18/PC2
S17/PC1
S16/PC0
S15/PB7
S14/PB6
S13/PB5
S12/PB4
S11/PB3
S10/PB2
S9/PB1
S8/PB0
S7/PA7
S6/PA6
S5/PA5
S4/PA4
S3/PA3
S2/PA2
S1PA1
V2/PL5/AN13
V1/PL4/AN12
COM0/PL0
COM1/PL1
COM2/PL2
COM3/PL3
P30/INT4/T1IN
P31/INT4/T1IN
VSS3
VDD3
P32/INT4/T1IN
P33/INT4/T1IN
P34/INT5/T1IN
P35/INT5/T1IN
P00
P01
P02
P03
P04
P05
P06 P07
P10/SO0
P11/SI0/SB0
P12/SCK0
P13/SO1
P14/SI1/SB1
P15/SCK1
P16/T1PWML
P17/T1PWMH/BUZ
RES
XT1/AN10 XT2/AN11
V
SS
1
CF1 CF2
V
DD
1
P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4 P85/AN5 P86/AN6
P87/AN7/MICIN
P70/INT0/T0LCP/AN8 P71/INT1/T0HCP/AN9
P72/INT2/T0IN P73/INT3/T0IN
S0/PA0
V3/PL6/AN14 S47/PF7 S46/PF6 S45/PF5 S44/PF4 S43/PF3 S42/PF2 S41/PF1 S40/PF0 S39/PE7 S38/PE6 S37/PE5 S36/PE4 S35/PE3 S34/PE2 S33/PE1 S32/PE0 S31/PD7 S30/PD6 S29/PD5 S28/PD4 S27/PD3 S26/PD2 S25/PD1 S24/PD0 V
SS
2
V
DD
2
S23/PC7 S22/PC6 S21/PC5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
LC877448A
LC877440A
LC877432A
LC877424A
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SANYO : QIP100E
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