Ordering number : EN
*
5240
22896HA (OT) No. 5240-1/8
Overview
The LC895124 is the next-generation version of the
LC89512 and is a CD-ROM decoder that includes a SCSI
interface that supports the high-speed transfers (10 MB/s)
of the FAST SCSI standard.
Functions
CD-ROM ECC function, subcode read function, SCSI
interface
Features
On-chip SCSI interface (with built-in SCAM selection
register)
Supports 8
playback - Using
16 80-ns DRAMs
Supports 4
playback - Using
16 80-ns DRAMs or
8
70-ns DRAMs
Transfer rates: 10 MB/s (synchronous), 5 MB/s
(asynchronous) using
16 80-ns DRAMs
*1
Transfer rates: 8.467 MB/s (synchronous), 4.2336 MB/s
(asynchronous) using
8 70-ns DRAMs
*2
PSRAM can be used, providing 5 MB/s transfers in
synchronous mode and 5 MB/s transfers in
asynchronous mode .
Supports the connection of up to 32 Mb of buffer RAM
(using DRAM) (Up to 2 Mb when PSRAM is used)
The user can freely set the CD main channel, C2 flag,
and other areas in buffer RAM.
Batch transfer function (transfers the CD main channel
and C2 flag data in a single operation)
Multi-block transfer function (automatically transfers
multiple blocks in a single operation)
High-speed transfer mode supports a 10-MB/s
(synchronous) transfer rate using
8 80-ns DRAMs
Subcode ECC function
Note: 1. For speeds up to 8
speed, use a SCSI master
clock frequency of 20 MHz.
Note:
2. For speeds up to 4
speed, use a SCSI master
clock frequency of 16.9344 MHz.
Package Dimensions
unit: mm
3214-SQFP144
Preliminary
SANYO: SQFP144
[LC895124]
LC895124
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-0005 JAPAN
CD-ROM Driver with On-Chip SCSI Interface and
Subcode Functions
CMOS LSI
Specifications
Absolute Maximum Ratings
at V
SS
= 0 V
Parameter
Symbol
Conditions
Ratings
Unit
Maximum supply voltage
V
DD
max
Ta = 25C
0.3 to +7.0
V
I/O voltages
V
I
, V
O
Ta = 25C
0.3 to V
DD
+ 0.3
V
Allowable power dissipation
Pd max
Ta
70C
450
mW
Operating temperature
Topr
30 to +70
C
Storage temperature
Tstg
55 to +125
C
Soldering heat resistances (pins only)
10 seconds
260
C
Allowable Operating Ranges
at Ta = 30 to +70C, V
SS
= 0 V
DC Characteristics
at V
SS
= 0 V, V
DD
= 4.5 to 5.5 V, Ta = 30 to +70C
Note: The subcode-related pins in group (1) are not provided by the LC895124.
SCSI Pin Input Characteristics
Sample Recommended Oscillator Circuit
R1 = 120 k
R2 = 47
C1 = 30 pF
Crystal oscillator frequencies: XTALCK0 = 16.9344 MHz and XTALCK1 = 20 MHz
or:
R1 = 3.3 k
R2 = None
C1 = 5 pF
Crystal oscillator frequency: XTALCK0 = 33.8688 MHz
If third harmonic overtones appear when using a 33.8688 MHz frequency with the
recommended circuit example, consult with the manufacturer of the crystal
element, since detailed values of the circuit constants will be influenced by the
printed circuit board.
No. 5240-2/8
LC895124
Parameter
Symbol
Applicable Pins
min
typ
max
Unit
Input high level voltage
V
IH
1
All input pins other than (1), (3), and XTALCK
2.2
V
Input low level voltage
V
IL
1
0.8
V
Input high level voltage
V
IH
2
RESET, IO0 to IO15, D0 to D7, RD, CS, WR, WFCK,
2.5
V
Input low level voltage
V
IL
2
SBSO, SCOR (1)
0.6
V
Input high level voltage
V
IH
3
Input pins (3), ACK, and ATN
2.0
V
Input low level voltage
V
IL
3
0.8
V
Output high level voltage
V
OH
1
I
OH
1 = 2 mA: All output pins except (2), (3),
2.4
V
and XTALCK, IO0 to IO15, and D0 to D7
Output low level voltage
V
OL
1
I
OL
1 = 2 mA: All output pins except (2), (3),
0.4
V
and XTALCK, IO0 to IO15, and D0 to D7
Output low level voltage
V
OL
2
I
OL
2 = 2 mA: INT1, INT0, and ZSWAIT
0.4
V
(open-drain outputs with pull-up resistors) (2)
Output low level voltage
V
OL
3
I
OL
3 = 48 mA: DB0, to DB7, DBP, BSY, I/O, MSG,
0.4
V
SEL, RST, REQ, C/D (3)
Input leakage current
I
L
V
I
= V
SS
, V
DD
: All input pins
25
+25
A
Pull-up resistance
R
UP
IO0 to IO15, D0 to D7, INT0, INT1, ZSWAIT
40
80
160
k
Parameter
Symbol
Conditions
min
typ
max
Unit
Supply voltage
V
DD
4.5
5.0
5.5
V
Input voltage range
V
IN
0
V
DD
V
Parameter
Symbol
Conditions
min
typ
max
Unit
Input threshold voltage
V
t + t1
V
DD
= 4.5 to 5.5 V
1.60
2.00
V
V
t t1
0.80
1.11
V
Hysteresis width
V
tt1
V
DD
= 5.0 V
0.41
0.49
V
Block Diagram
Note: 1 BCK, SDATA, LRCK, C2PO
2. DB0 to DB7, DBP, BSY, MSG, SEL, RST, REQ, I/O, C/D
3. ACK, ATN
4. ZRD, ZWR, SUA0 to SUA6, ZCS, CSCTRL
5. D0 to D7
6. IO0 to IO15
7. RA0 to RA16, ZRAS0, ZRAS1, ZCAS0, ZCAS1, ZOE, ZUWE, ZLWE
Note: IO8 to IO15 and RA9 to RA16 are the same pins.
Subcode pins are connected to CD-DSP or to V
SS
.
No. 5240-3/8
LC895124
Pin Functions
Type: I: Input pin, O: Output pin, B: Bidirectional pin, P: Power supply pin, NC: No connection pin
Note: 1. NC pins must be left open. Do not connect any signal to these pins.
2. Pin names that start with Z are negative-logic signals.
3. V
SS0
is the logic system ground and V
SS1
is the SCSI interface ground.
4. Applications that use DRAM must insert resistors in the CAS and RAS lines, connect capacitors between these lines and ground, and take any
other measures necessary to prevent undershoot in the DRAM related circuits.
5. Since these circuits include buffers that sink 48 mA, adequate noise prevention measures must be applied.
No. 5240-4/8
LC895124
Pin No.
Symbol
Type
Function
1
V
SS0
P
2
V
SS0
P
3
V
SS0
P
4
V
SS0
P
5
ZRAS0
O
Buffer RAM RAS signal output pin 0 (Normally, pin 0 is used)
6
ZRAS1
O
Buffer RAM RAS signal output pin 1
7
ZCAS0
O
Buffer RAM CAS signal output pin 0 (Normally, pin 0 is used)
8
ZCAS1
O
Buffer RAM CAS signal output pin 1
9
ZOE
O
Buffer RAM output enable
10
ZUWE
O
Buffer RAM upper write enable
11
ZLWE
O
Buffer RAM lower write enable
12
V
SS0
P
13
RA0
O
14
RA1
O
15
RA2
O
Buffer RAM address signal outputs
16
RA3
O
17
RA4
O
18
V
DD
P
19
V
SS0
P
20
RA5
O
21
RA6
O
Buffer RAM address signal outputs
22
RA7
O
23
RA8
O
24
RA9 (IO15)
B
25
RA10 (IO14)
B
Address outputs for the buffer RAM or data I/O pins
26
RA11 (IO13)
B
The pin circuits include pull-up resistors.
27
RA12 (IO12)
B
28
V
SS0
P
29
RA13 (IO11)
B
30
RA14 (IO10)
B
Address outputs for the buffer RAM or data I/O pins
31
RA15 (IO9)
B
The pin circuits include pull-up resistors.
32
RA16 (IO8)
B
33
IO7
B
34
IO6
B
Buffer RAM data I/O. The pin circuit includes a pull-up resistor.
35
IO5
B
36
V
SS0
P
37
V
DD
P
38
IO4
B
39
IO3
B
Address outputs for the buffer RAM or data I/O pins
40
IO2
B
The pin circuits include pull-up resistors.
41
IO1
B
42
IO0
B
43
V
SS0
P
44
XTALCK0
I
Crystal oscillator input
45
XTAL0
O
Crystal oscillator output
46
V
DD
P
47
MCK
O
Outputs the XTALCK0 frequency, or that frequency divided by 2.
48
TEST0
I
49
TEST1
I
Test pins. These pins must be connected to V
SS0
.
50
TEST2
I
Continued on next page.
Continued from preceding page.
Type: I: Input pin, O: Output pin, B: Bidirectional pin, P: Power supply pin, NC: No connection pin
Note: 1. NC pins must be left open. Do not connect any signal to these pins.
2. Pin names that start with Z are negative-logic signals.
3. V
SS0
is the logic system ground and V
SS1
is the SCSI interface ground.
4. Applications that use DRAM must insert resistors in the CAS and RAS lines, connect capacitors between these lines and ground, and take any
other measures necessary to prevent undershoot in the DRAM related circuits.
5. Since these circuits include buffers that sink 48 mA, adequate noise prevention measures must be applied.
No. 5240-5/8
LC895124
Pin No.
Symbol
Type
Function
51
TEST3
I
Test pins. These pins must be connected to V
SS0
.
52
TEST4
I
53
ZRESET
I
LSI reset. The LSI is reset on a 0 input.
54
V
DD
P
55
V
SS0
P
56
CSCTRL
I
Selects active-high or active-low for the microcontroller CS logic.
57
X1EN
I
Selection pin that must be set to 1 when XTALCK1 is used.
58
XTALCK1
I
SCSI block oscillator circuit input. Selected by X1EN.
59
XTAL1
O
SCSI block oscillator circuit output.
60
ZSWAIT
O
WAIT signal output to the microcontroller
61
V
DD
P
62
V
SS0
P
63
D0
B
64
D1
B
65
D2
B
66
D3
B
67
D4
B
Microcontroller data signals
68
D5
B
69
D6
B
70
D7
B
71
ZRD
I
Microcontroller data read signal input
72
V
SS0
P
73
V
DD
P
74
ZWR
I
Microcontroller data write signal input
75
ZCS
I
Input for the register chip select signal from the microcontroller
76
SUA0
I
77
SUA1
I
78
SUA2
I
79
SUA3
I
Register chip select signal from the microcontoller
80
SUA4
I
81
SUA5
I
82
SUA6
I
83
ZINT0
O
Interrupt request output to the microcontroller (ECC side. Set with a register.)
84
ZINT1
O
Interrupt request output to the microcontroller (SCSI side. Set with a register.)
85
NC
86
NC
87
NC
88
NC
89
NC
90
V
DD
P
91
V
SS1
P
92
NC
93
NC
94
NC
95
DB0
B
SCSI connection
96
V
SS1
P
97
DB1
B
SCSI connection
98
DB2
B
99
V
SS1
P
100
DB3
B
SCSI connection
Continued on next page.
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