1
8 Megabit FlashBank Memory
LE28DW8102T
1
SANYO Electric Co.,Ltd. Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan
R.1.01(2/15/2000) No.xxxx-1/19
FEATURES:
Single 3.0-Volt Read and Write Operations
Separate Memory Banks by Address Space
Simultaneous Read and Write Capability
Superior Reliability
Endurance: 10,000 Cycles
Data Retention: 10 years
Low Power Consumption
Active Current, Read:
10 mA (typical)
Active Current,
Read & Write:
30 mA
(typical)
Standby Current:
5A (typical)
Auto Low Power Mode Current: 5A (typical)
Fast Write Operation
Bank Erase + Program:
4.5 sec (typical)
Block Erase + Program:
500 ms (typical)
Sector Erase + Program:
30 ms (typical
)
Fixed Erase, Program, Write Times
Does not change after cycling
Read Access Time
80/90 ns
Latched Address and Data
End of Write Detection
Toggle Bit
Data # Polling
Flash Bank: Two Small Erase Element Sizes
1K Words per Sector or 32K Words per Block
Erase either element before Word Program
CMOS I/O Compatibility
Packages Available
48-Pin TSOP
Continuous Hardware and Software Data
Protection (SDP)
Product Description
The LE28DW8102T consists of two memory banks, 2 each
256K x 16 bits sector mode flash EEPROM manufactured with
SANYO's proprietary, high performance FlashTechnology.
The LE28DW8102T writes with a 3.0-volt-only power supply.
The LE28DW8102T is divided into two separate memory
banks, 2 each 512K x 16 Flash banks. Each Flash bank is
typically used for program code storage and contains 256
sectors, each of 1K words or 8 blocks, each of 32K words. The
Flash banks may also be used to store data.
Any bank may be used for executing code while writing data
to a different bank. Each memory bank is controlled by separate
Bank selection address (A18) lines.
The LE28DW8102T inherently uses less energy during Erase,
and Program than alternative flash technologies. The total
energy consumed is a function of the applied voltage, current,
and time of application. Since for any given voltage range, the
Flash technology uses less current to program and has a
shorter Erase time, the total energy consumed during any Erase
or Program operation is less than alternative flash technolo-
gies. The Auto Low Power mode automatically reduces the
active read current to approximately the same as standby; thus,
providing an average read current of approximately 1 mA/MHz
of Read cycle time.
The Flash technology provides fixed Erase and Program times,
independent of the number of erase/program cycles that have
occurred. Therefore the system software or hardware does not
have to be modified or de-rated as is necessary with alternative
flash technologies, whose Erase and Program times increase
with accumulated erase/program cycles.
Device Operation
The LE28DW8102T operates as two independent 4Megabit
Word Pogram, Sector Erase flash EEPROMs.
All memory banks share common address lines, I/O lines,
WE#, and OE#. Memory bank selection is by bank select
address. WE# is used with SDP to control the Erase and
Program operation in each memory bank.
The LE28DW8102T provides the added functionality of
being able to simultaneously read from one memory bank
while erasing, or programming to one other memory bank.
Once the internally controlled Erase or Program cycle in a
memory bank has commenced, a different memory bank can
be accessed for read. Also, once WE# and CE# are high
during the SDP load sequence, a different bank may be
accessed to read. LE28DW8102T which selectes a bank by
a address. It can be used as a normal conventinal flash
memory when operats erase or program operation to only a
bank at non-concurrent operation.
The device ID cannot be accessed while any bank is writing,
erasing, or programming.
The
Auto Low Power Mode
automatically puts the
LE28DW8102T in a near standby mode after data has been
accessed with a valid Read operation. This reduces the I
DD
active read current from typically 10mA to typically 5A.
The Auto Low Power mode reduces the typical I
DD
active
Preliminary Specifications
The Flash Bank product family was jointly developed by SANYO and Sillicon Storage Technology,Inc.(SST),under SST's technology license. This preliminary specification is subject to change without notice.
2
8 Megabit FlashBank Memory
LE28DW8102T
2
SANYO Electric Co.,Ltd. Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan
R.1.01(2/15/2000) No.xxxx-2/19
read current to the range of 1mA/MHz of Read cycle time.
If a concurrent Read while Write is being performed, the I
DD
is reduced to typically 40mA. The device exits the Auto Low
Power mode with any address transition or control signal
transition used to initiate another Read cycle, with no access
time penalty.
Read
The Read operation of the LE28DW8102T Flash banks is
controlled by CE# and OE#, a chip enable and output enable
both have to be low for the system to obtain data from the
outputs. OE# is the output control and is used to gate data
from the output pins. The data bus is in high impedance state
when OE# is high. Refer to the timing waveforms for further
details (Figure 3).
When the read operation is executed without address
change after power switch on, CE# should be changed the
level high to low. If the read operation is executed after
programing , CE# should be changed the level high to low.
Write
All Write operations are initiated by first issuing the Soft-
ware Data Protect (SDP) entry sequence for Bank, Block, or
Sector Erase. Word Program in the selected Flash bank.
Word Program and all Erase commands have a fixed dura-
tion, that will not vary over the life of the device, i.e., are
independent of the number of Erase/Program cycles en-
dured.
Either Flash bank may be read to another Flash Bank during
the internally controlled write cycle.
The device is always in the Software Data Protected mode for
all Write operations Write operations are controlled by
toggling WE# or CE#. The falling edge of WE# or CE#,
whichever occurs last, latches the address. The rising edge of
WE# or CE#, whichever occurs first, latches the data and
initiates the Erase or Program cycle.
For the purposes of simplification, the following descrip-
tions will assume WE# is toggled to initiate an Erase or
Program. Toggling the applicable CE# will accomplish the
same function. (Note, there are separate timing diagrams to
illustrate both WE# and CE# controlled Program or Write
commands.)
Word Program
The Word Program operation consists of issuing the SDP
Word Program command, initiated by forcing CE# and WE#
low, and OE# high. The words to be programmed must be in
the erased state, prior to programming. The Word Program
command programs the desired addresses word by word.
During the Word Program cycle, the addresses are latched by
the falling edge of WE#. The data is latched by the rising edge
of WE#. ( See Figure 4-1 for WE# or 4-2 for CE# controlled
Word Program cycle timing waveforms, Table 3 for the
command sequence, and Figure 15 for a flowchart. )
During the Erase or Program operation, the only valid reads
from that bank are Data# Polling and Toggle Bit. The other
bank may be read.
The specified Bank, Block, or Sector Erase time is the only
time required to erase. There are no preprogramming or
other commands or cycles required either internally or
externally to erase the bank, block, or sector.
Erase Operations
The Bank Erase is initiated by a specific six-word load sequence
(See Tables 3). A Bank Erase will typically be less than 70 ms.
An alternative to the Bank Erase in the Flash bank is the Block
or Sector Erase. The Block Erase will erase an entire Block (32K
words) in typically 15 ms. The Sector Erase will erase an entire
sector (1024 words) in typically 15 ms. The Sector Erase
provides a means to alter a single sector using the Sector Erase
and Word Program modes. The Sector Erase is initiated by a
specific six-word load sequence (see Table 3).
During any Sector, Block, or Bank Erase within a bank, any
other bank may be read.
Bank Erase
The LE28DW8102T provides a Bank Erase mode, which allows
the user to clear the Flash bank to the "1"state. This is useful
when the entire Flash must be quickly erased.
The software Flash Bank Erase mode is initiated by issuing the
specific six-word loading sequence, as in the Software Data
Protection operation. After the loading cycle, the device enters
into an internally timed cycle.( See Table 3 for specific codes,
Figure 5-1 for the timing waveform, and Figure12 for a flow-
chart. )
Block Erase
The LE28DW8102T provides a Block Erase mode, which allows
the user to clear any block in the Flash bank to the "1"state.
The software Block Erase mode is initiated by issuing the
specific six-word loading sequence, as in the Software Data
Protect operation. After the loading cycle, the device enters
into an internally timed Erase cycle. (See Table 3 for specific
codes, Figure 5-2 for the timing waveform, and Figure 13 for a
flowchart.) During the Erase operation, the only valid reads are
Data# Polling and Toggle Bit from the selected bank, other
banks may perform normal read.
Sector Erase
The LE28DW8102T provides a Sector Erase mode, which
allows the user to clear any sector in the Flash bank to the "1"
state.
3
8 Megabit FlashBank Memory
LE28DW8102T
3
SANYO Electric Co.,Ltd. Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan
R.1.01(2/15/2000) No.xxxx-3/19
The software Sector Erase mode is initiated by issuing the
specific six-word loading sequence, as in the Software Data
Protect operation. After the loading cycle, the device enters
into an internally timed Erase cycle.( See Table 3 for specific
codes, Figure 5-3 for the timing waveform, and Figure 14 for a
flowchart.) During the Erase operation, the only valid reads are
Data# Polling and Toggle Bit from the selected bank, other
banks may perform normal read.
Write Operation Status Detection
The LE28DW8102T provides two software means to detect the
completion of a Flash bank Program cycle, in order to optimize
the system Write cycle time. The software detection includes
two status bits : Data# Polling (DQ
7
) and Toggle Bit (DQ
6
). The
end of Write Detection mode is enabled after the rising edge of
WE#, which initiates the internal Erase or Program cycle.
The actual completion of the nonvolatile write is a synchro-
nous with the system; therefore, either a Data# Polling or
Toggle Bit read may be simultaneous with the completion of the
Write cycle. If this occurs, the system will possibly get an
erroneous result, i.e. valid data may appear to conflict with
either DQ
7
or DQ
6
. In order to prevent spurious device rejec-
tion, if an erroneous result occurs, the software routine should
include a loop to read the accessed location an additional two
(2) times. If both reads are valid, then the device has completed
the Write cycle, otherwise the rejection is valid.
There is no provision to abort an Erase or Program operation,
once initiated. For the SANYO Flash technology, the associ-
ated Erase and Program times are so fast, relative to system
reset times, there is no value in aborting the operation. Note,
reads can always occur from any bank not performing an Erase
or Program operation.
Should the system reset, while a Block or Sector Erase or Word
Program is in progress in the bank where the boot code is
stored, the system must wait for the completion of the operation
before reading that bank. Since the maximum time the system
would have to wait is 25 ms (for a Block Erase), the system ability
to read the boot code would not be affected.
Data# Polling (DQ
7
)
When the LE28DW8102T is in the internal Flash bank Program
cycle, any attempt to read DQ
7
of the last word loaded during
the Flash bank Word Load cycle will receive the complement
of the true data. Once the Write cycle is completed, DQ
7
will
show true data. The device is then ready for the next operation.
(See Figure 6 for the Flash bank Data Polling timing waveforms
and Figure 16 for a flowchart.)
Toggle Bit (DQ
6
)
During the Flash bank internal Write cycle, any consecutive
attempts to read DQ
6
will produce alternating 0's and 1's, i.e.
toggling between 0 and 1. When the Write cycle is completed,
the toggling will stop. The device is then ready for the next
operation. (See Figure 7 for Flash bank Toggle Bit timing
waveforms and Figure 16 for a flowchart.)
Data Protection
The LE28DW8102T provides both hardware and software
features to protect nonvolatile data from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# pulse of less than 5 ns will not
initiate a Write cycle.
V
DD
Power Up/Down Detection: The Write operation is inhib-
ited when V
DD
is less than 1.5 volts.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high
will inhibit the Write operation. This prevents inadvertent
writes during power-up or power-down.
Software Data Protection (SDP)
The LE28DW8102T provides the JEDEC approved software
data protection scheme as a requirement for initiating a Write,
Erase, or Program operation. With this scheme, any Write
operation requires the inclusion of a series of three word-load
operations to precede the Word Program operation. The three-
word load sequence is used to initiate the Program cycle,
providing optimal protection from inadvertent Write opera-
tions, e.g., during the system power-up or power-down. The
six-word sequence is required to initiate any Bank, Block, or
Sector Erase operation.
The requirements for JEDEC compliant SDP are in byte format.
The LE28DW8102T is organized by word; therefore, the con-
tents of DQ
8
to DQ
15
are "Don't Care"during any SDP (3-word
or 6-word) command sequence.
During the SDP load command sequence, the SDP load cycle
is suspended when WE# is high. This means a read may occur
to any other bank during the SDP load sequence.
The bank reserve in SDP load sequence is reserved by the bus
cycle of command materialization. If the command sequence
is aborted, e.g., an incorrect address is loaded, or incorrect data
is loaded, the device will return to the Read mode within T
RC
of execution of the load error.
Concurrent Read and Write Operations
The LE28DW8102T provides the unique benefit of being able
to read any bank, while simultaneously erasing, or program-
ming one other bank. This allows data alteration code to be
executed from one bank, while altering the data in another bank.
The next table lists all valid states.
4
8 Megabit FlashBank Memory
LE28DW8102T
4
SANYO Electric Co.,Ltd. Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan
R.1.01(2/15/2000) No.xxxx-4/19
the write algorithm requirements for each bank. (For de-
tails, see Table 3 for software operation and Figures 8 for
timing waveforms. )
Product Identification Table
Device ID codes are unique to each bank. Should a chip ID
be required, any of the bank IDs may be used as the chip
ID. While in the read software ID mode, no other operation
is allowed until after exiting these modes.
Product Identification Mode Exit
In order to return to the standard Read mode, the Product
Identification mode must be exited. Exit is accomplished by
issuing the Software ID exit command, which returns the
device to normal operation. This command may also be
used to reset the device to the Read mode after any
inadvertent transient condition that apparently causes the
device to behave abnormally, e.g., not read correctly. For
details, (see Table 3 for software operation and Figures 9 for
timing waveforms.)
Concurrent Read/Write State Table
Note:
For the purposes of this table, write means to Block, Sector, or Bank Erase, or Word
Program as applicable to the appropriate bank.
The device will ignore all SDP commands and toggling of WE#
when an Erase or Program operation is in progress. Note,
Product Identification entry commands use SDP; therefore,
this command will also be ignored while an Erase or Program,
operation is in progress.
Product Identification
The product identification mode identifies the device manufac-
turer as SANYO and provides a code to identify each bank. The
manufacturer ID is the same for each bank; however, each bank
has a separate device ID. Each bank is individually accessed
using the applicable Bank Address and a software command.
Users may wish to use the device ID operation to identify
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Figure 1 : Pin Description : TSOP-1 (10mm x 14mm)
1
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13
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DQ0
OE#
VSS
A0
A1
NC
TSOP
Type-I
Normal Bend
(10mm x 14mm)
5
8 Megabit FlashBank Memory
LE28DW8102T
5
SANYO Electric Co.,Ltd. Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan
R.1.01(2/15/2000) No.xxxx-5/19
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Table1: Pin Description
Figure2: Functinaly Block Diagram
A18-A0
CE#
OE#
WE#
DQ15-DQ0
256Kx16
256Kx16
X-Decoder
Y-Decoder
Charge Pump
&
Vref.
Address Buffer
&
Latches
Control Logic
I/O Buffers
&
Data Latches
Flash Bank1
Flash Bank2
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