Line Card Protection Switch
for SONET or SDH Network Elements
ACS8515 LC/P
Description
Features
Block Diagram
The ACS8515 is a highly integrated, single-chip
solution for hit-less protection switching of SEC
clocks from Master and Slave SETS clockcards
in a SONET or SDH Network Element. The
ACS8515 has fast activity monitors on the in-
puts and will implement automatic system pro-
tection switching against master clock failure. A
further input is provided for an optional standby
SEC clock. The ACS8515 is fully compliant with
the required specifications and standards.
The ACS8515 can perform frequency translation
from a SEC input clock distributed along a back
plane to a different local line card clock, e.g. 8
kHz distributed on the back plane and 19.44 MHz
generated on the line cards.
An SPI serial port is incorporated, providing ac-
cess to the configuration and status registers for
device setup.
The ACS8515 can utilise either a low cost XO
oscillator module, or a TCXO with full tempera-
ture calibration - as required by the application.
ADVANCED COMMUNCIATIONS
FINAL
Revision 2.05/Jan 2001 2001 Semtech Corp
www.semtech.com
Suitable for Stratum 3, 4E and 4 SONET
or SDH Equipment Clock (SEC) applications
Meets AT&T, ITU-T, ETSI and Telcordia
specifications
Three SEC input clocks, from 2 kHz to 155.52
MHz
Generates two SEC output clocks, up to 311.04
MHz
Frequency translation of SEC input clock to a
different local line card clock
Robust input clock source frequency and
activity monitoring on all inputs
Supports Free-Run, Locked and Holdover
modes of operation
Automatic hit-less source switchover on loss
of input
External force fast switch between SEC inputs
Phase build-out for output clock phase
continuity during input switchover
SPI compatible serial microprocessor interface
Programmable wander and jitter tracking/
attenuation 0.1 Hz to 20 Hz
Single 3.3 v operation. 5 v I/O compatible
Operating temperature (ambient) -40C to
+85C
Available in 64 pin LQFP package
Monitors
Chip C lock
Generator
TCXO or XO
DP LL
Frequency Synthes is
3 x S EC Input
Mas ter/Slave
+ Standby:
N x 8kHz
1.544MHz
2.048MHz
6.48M Hz
19.44MHz
38.88MHz
51.84MHz
77.76MHz
155.52MHz
P lus :
MFrSync
APLL
Frequency
Dividers
Output
Ports
2xSEC
FrSync
MFrSync
Input
Ports
3xSEC
MFrSync
2 x SEC Output
including:
1.544/2.048MHz
3.088/4.096MHz
6.176/8.192MHz
12.352/16.384MHz
19.44M Hz
38.88M Hz
155.52M Hz
311.04M Hz
Plus :
2kHz MF rSync
8kHz FrSync
SPI Compatible Serial
M icroprocessor Port
Priority
T able
Register
Set
Priority
T able
Register
Set
Revision 2.05/Jan 2001 2001 Semtech Corp
www.semtech.com
2
ACS8515 LC/P
ADVANCED COMMUNCIATIONS
FINAL
Table of Contents
Pin diagram................................................................................................................................................3
Pin descriptions.........................................................................................................................................4
Functional description...............................................................................................................................6
Electrical specification............................................................................................................................33
Microprocessor interface timing characteristics.......................................................................................41
Package information................................................................................................................................43
Application information............................................................................................................................45
Revision History.......................................................................................................................................46
Order information....................................................................................................................................47
Local oscillator clock..........................................................................................................................................................6
Input Interfaces..................................................................................................................................................................7
Input reference clock ports................................................................................................................................................7
Input wander and jitter tolerance......................................................................................................................................9
Output clock ports...........................................................................................................................................................10
Output wander and jitter..................................................................................................................................................11
Phase variation.................................................................................................................................................................13
Phase build-out.................................................................................................................................................................15
Microprocessor interface................................................................................................................................................15
Interrupt enable and clear...............................................................................................................................................16
Register map.....................................................................................................................................................................17
Register map description.................................................................................................................................................20
Selection of input reference clock sources...................................................................................................................27
Activity monitoring...........................................................................................................................................................28
Modes of operation..........................................................................................................................................................30
Power on reset - PORB.....................................................................................................................................................31
Absolute maximum range...............................................................................................................................................33
Operating conditions.......................................................................................................................................................33
TTL DC characterisitics...................................................................................................................................................33
PECL DC characteristics..................................................................................................................................................35
LVDS DC characteristics..................................................................................................................................................36
Jitter characteristics........................................................................................................................................................37
Serial mode.......................................................................................................................................................................41
Simplified application schematic...................................................................................................................................45
Revision 2.05/Jan 2001 2001 Semtech Corp
www.semtech.com
3
ACS8515 LC/P
ADVANCED COMMUNCIATIONS
FINAL
Top view of 64 pin LQFP package.
NC - Not Connected, IC - Internally Connected
Pin Diagram
1
AGND
2
IC
3
AGND
4
VA1+
5
INTREQ
6
REFCLK
7
DGND
8
VD+
9
VD+
10
DGND
11
DGND
12
VD+
13
SRCSW
14
VA2+
15
AGND
16
IC
17
FrSync
18
MFrSync
19
O1POS
20
O1NEG
21
GND_DIFF
22
VDD_DIFF
23
SEC1_POS
24
SEC1_NEG
25
SEC2_POS
26
SEC2_NEG
27
VDD5
28
Sync2k
29
SEC1
30
SEC2
31
DGND
32
VDD
64
SONSDHB
63
IC
62
IC
61
IC
60
IC
59
NC
58
DGND
57
VDD
56
O2
55
NC
54
VDD
53
DGND
52
SDO
51
IC
50
IC
49
IC
48
PORB
47
SCLK
46
VDD
45
VDD
44
CSB
43
SDI
42
CLKE
41
IC
40
DGND
39
VDD
38
VDD
37
IC
36
VDD
35
IC
34
SEC3
33
IC
ACS8515
LC/P
Rev 2.0
1
Revision 2.05/Jan 2001 2001 Semtech Corp
www.semtech.com
4
ACS8515 LC/P
ADVANCED COMMUNCIATIONS
FINAL
Pin Descriptions
Power
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d
Revision 2.05/Jan 2001 2001 Semtech Corp
www.semtech.com
5
ACS8515 LC/P
ADVANCED COMMUNCIATIONS
FINAL
Others
Note: I = input, O = output, P = power, TTL
U
= TTL input with pull-up resistor, TTL
D
= TTL input with pull-down resistor
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Revision 2.05/Jan 2001 2001 Semtech Corp
www.semtech.com
6
ACS8515 LC/P
ADVANCED COMMUNCIATIONS
FINAL
Functional description
The ACS8515 is a highly integrated, single-chip
solution for hit-less protection switching of
SEC clocks from Master and Slave SETS clock
cards in a SONET or SDH Network Element.
The ACS8515 has fast activity monitors on the
inputs and will implement automatic system
protection switching for Master/Slave SEC clock
failure. The standby SEC clock will be selected
if both the Master and Slave input clocks fail.
The selection of the Master/Slave input can
also be forced by a Force Fast Switch pin.
The ACS8515 can perform frequency translation
from a SEC input clock distributed along a back
plane to a different local line card - e.g. 8 kHz
distributed on the back plane and 19.44 MHz
generated on the line cards.
The ACS8515 has three SEC clock inputs
(Master, Slave and Standby) and a single Multi-
Frame Sync input, for synchronising the frame
and multi-frame sync outputs.
The ACS8515 generates two SEC clock outputs
via PECL/LVDS and TTL ports, with spot
frequencies from 1.544/2.048 MHz up to
311.04 MHz. The ACS8515 also provides an 8
kHz Frame Sync and 2 kHz Multi-Frame Sync
output clock.
The ACS8515 has a high tolerance to input
jitter and wander. The output jitter and wander
are low, where the wander transfer is
programmable (0.1 Hz up to 20 Hz cut-off
points).
The ACS8515 includes an SPI compatible serial
microprocessor port, providing access to the
configuration and status registers for device
setup.
Local Oscillator Clock
The Master system clock on the ACS8515
should be provided by an external clock oscillator
of frequency 12.80 MHz. The exact clock
specification is dependent on the quality of
Holdover performance required in the
application.
In most Line Card protection switching
applications where there is a high chance that
at least one SEC reference input will be
available, the long term stability requirement
for Holdover is not appropriate and an
inexpensive crystal local oscillator can be used.
In other applications where there may be a
requirement for longer term Holdover stability
to meet the ITU standards for Stratum 3, a
higher quality oscillator can be used.
Please contact Semtech for information on
crystal oscillator suppliers.
Crystal Frequency Calibration
The absolute crystal frequency accuracy is less
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Revision 2.05/Jan 2001 2001 Semtech Corp
www.semtech.com
7
ACS8515 LC/P
ADVANCED COMMUNCIATIONS
FINAL
important than the stability since any frequency
offset can be compensated by adjustment of
register values in the IC. This allows for
calibration and compensation of any crystal
frequency variation away from its nominal value.
+/- 50 ppm adjustment would be sufficient to
cope with most crystals, in fact the range is an
order of magnitude larger due to the use of
two 8 bit register locations. The setting of the
conf_nominal_frequency register allows for this
adjustment. An increase in the register value
increases the output frequencies by 0.02 ppm
for each LSB step. The default value (in decimal)
is 39321. The minimum being 0 and the
maximum 65535, gives a +500 ppm to -700
ppm adjustment range of the output
frequencies.
For example, if the crystal was oscillating at
12.8 MHz + 5ppm, then the calibration value
in the register to give a -5 ppm adjustment in
output frequencies to compensate for the
crystal inaccuracy, would be : 39321 - (5 /
0.02) = 39071 (decimal).
Input Interfaces
The ACS8515 supports up to three individual
input reference clock sources via TTL/CMOS
and PECL/LVDS technologies. These interface
technologies support 3.3 V and 5 V operation.
Input Reference Clock Ports
The input reference clock ports are arranged in
groups. Group one comprises a TTL port (SEC1)
and a PECL/LVDS port (SEC1POS and
SEC1NEG). Group two comprises a TTL port
(SEC2) and a PECL/LVDS port (SEC2POS and
SEC2NEG). Group three comprises a TTL port
(SEC3). For group one and group two, only one
of the two input ports types must be active at
any time, the other must not be driven by a
reference input. Unused PECL/LVDS differential
inputs should be fixed with one input high (VDD)
and the other low (GND), or set in LVDS mode
and left floating (in which case one input is
internally pulled high and the other low).
SDH and SONET networks use different default
frequencies; the network type is selectable
using the config_mode register 34 Hex, bit 2.
For SONET, config_mode register 34 Hex, bit 2
= 1, for SDH config_mode register 34 Hex, bit
2 = 0. On power-up or by reset, the default will
be set by the state of the SONSDHB pin (pin
64). Specific frequencies and priorities are set
by configuration.
The TTL ports (compatible also with CMOS
signals) support clock speeds up to 100 MHz,
with the highest spot frequency being 77.76
MHz. Clock speeds above 100 MHz should not
be applied to the TTL ports. The PECL/LVDS
ports support the full range of clock speeds,
up to 155.52 MHz.
The actual spot frequencies supported are; 8
kHz (and N x 8 kHz), 1.544 MHz/2.048 MHz,
6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz,
51.84 MHz, 77.76 MHz, and 155.52 MHz. The
frequency selection is programmed via the
cnfg_ref_source_frequency register. The
internal DPLL will normally lock to the selected
input at the frequency of the input, eg. 19.44
MHz will lock the DPLL phase comparisons at
19.44 MHz. It is, however, possible to utilise
an internal pre-divider to the DPLL to divide the
input frequency before it is used for phase
comparisons in the DPLL. This pre-divider can
be used in one of 2 ways;
(i) any of the supported spot frequencies can be divided to
8 kHz by setting the "lock8K" bit (bit 6) in the appropriate
cnfg_ref_source_frequency register location
(ii) any multiple of any supported frequency can be
supported by using the "DivN" feature (bit 7 of the
cnfg_ref_source_frequency register). Any reference input
can be set to lock at 8 kHz independently of the
frequencies and configurations of the other inputs.
Any reference input with the "DivN" bit set in
the cnfg_ref_source_frequency register will
employ the internal pre-divider prior to the DPLL
Revision 2.05/Jan 2001 2001 Semtech Corp
www.semtech.com
8
ACS8515 LC/P
ADVANCED COMMUNCIATIONS
FINAL
locking. The cnfg_freq_divn register contains
the divider ratio N where the reference input
will get divided by (N+1) where 0<N<2
14
-1. The
cnfg_ref_source_frequency register must be set
to the closest supported spot frequency to the
input frequency, but must be lower than the
input frequency. When using the DivN feature
the post-divider frequency must be 8 kHz, which
is indicated by setting the lock8k bit high (bit
6 in cnfg_ref_source_frequency register). Any
input set to DivN must have the frequency
monitors disabled (if the frequency monitors
are disabled, they are disabled for all inputs
regardless of the input configurations, in this
case only activity monitoring will take place).
Whilst any number of inputs can be set to use
the DivN feature, only one N can be
programmed, hence all inputs using the DivN
feature must require the same division to get
to 8 kHz.
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Table 1: Input Reference Source Selection and Group allocation
Notes for Table 1.
Note 1. TTL ports (compatible also with CMOS signals) support clock speeds up to 100 MHz, with the highest spot frequency
being 77.76 MHz. The actual spot frequencies are 8 kHz (N x 8 kHz), 1.544/2.048 MHz, 6.48 MHz, 19.44 MHz, 25.92 MHz,
38.88 MHz, 51.84 MHz and 77.76 MHz.
Note 2. PECL and LVDS ports support the spot clock frequencies listed above plus 155.52 MHz. There are different output
clock frequencies available for SONET and SDH applications. F
1
/F
2
means that the output frequency is F
1
for SONET mode
selection and F
2
for SDH mode selection.
Note 3. The default priority values in brackets are the default numbers reported in the register map, which match up with the
ACS8510.
On power up, or by reset, the default will be set by the SONSDHB pin. Specific frequencies and priorities are set by
configuration. For SONET, config_mode register 34 Hex, bit 2 = 1. For SDH config_mode register 34 Hex, bit 2 = 0.
Revision 2.05/Jan 2001 2001 Semtech Corp
www.semtech.com
9
ACS8515 LC/P
ADVANCED COMMUNCIATIONS
FINAL
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Table 2: Input Reference Source Jitter Tolerance.
Notes for Table 2.
Note 1. The frequency acceptance and generation range will be +/-4.6 ppm around the required frequency when the
external crystal frequency accuracy is within a tolerance of +/- 4.6 ppm.
Note 2. The fundamental acceptance range and generation range is +/- 9.2 ppm with an exact external crystal
frequency of 12.8 MHz.
Note 3. The power up default PDLL range is as stated in note 2, but the range is also programmable from 0 to 80 ppm
in 0.08 ppm steps.
PECL and LVDS ports support the spot clock
frequencies listed above plus 155.52 MHz. The
choice of PECL or LVDS compatibility is
programmed via the cnfg_differential_inputs
register.
Unused PECL/LVDS differential inputs should
be fixed with one input high (VDD) and the other
input low (GND), or set in LVDS mode and left
floating, in which case one input is internally
pulled high and the other low.
Input Wander and Jitter Tolerance
The ACS8515 is compliant to the requirements
of all relevant standards, principally ITU
Recommendation G.825, ANSI T1.101-1994
and ETS 300 462-5 (1997).
All reference clock inputs have a tight frequency
tolerance but a generous jitter tolerance. Pull-
in, hold-in and pull-out ranges are specified for
each input port in Table 2. Minimum jitter
tolerance masks are specified in Figures 1 and
2, and Tables 3 and 4, respectively. The
ACS8515 will tolerate wander and jitter
components greater than those shown in Figure
1 and Figure 2, up to a limit determined by a
combination of the apparent long-term
frequency offset caused by wander and the
eye-closure caused by jitter (the input source
will be rejected if the offset pushes the
frequency outside the hold-in range for long
enough to be detected, whilst the signal will
also be rejected if the eye closes sufficiently to
affect the signal purity). The 8klocking mode
should be engaged for high jitter tolerance
according to these masks.
All reference clock ports are monitored for
quality, including frequency offset and general
activity. Single short-term interruptions in
selected reference clocks may not cause
rearrangements, whilst longer interruptions, or
multiple, short-term interruptions, will cause
rearrangements, as will frequency offsets which
are sufficiently large or sufficiently long to cause
loss-of-lock in the phase-locked loop. The failed
reference source will be removed from the
priority table and declared as unserviceable,
until its perceived quality has been restored to
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Figure 1: Minimum Input Jitter Tolerance for inputs supporting G.783 compliant sources
Table 3: Amplitude and Frequency values for Jitter Tolerance for inputs supporting G.783 compliant sources
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an acceptable level.
The registers reg sts_curr_inc_offset (address
0C, 0D, 07) report the frequency of the DPLL
with respect to the external TCXO frequency.
This is a 19 bit signed number with one LSB
representing 0.0003 ppm (range of +/- 80
ppm). Reading this regularly can show how the
currently locked source is varying in value e.g.
due to wander on its input.
The ACS8515 performs automatic frequency
monitoring with an acceptable input frequency
offset range of +/- 16.6 ppm. The ACS8515
DPLL has a programmable frequency limit of
+/- 80 ppm. If the range is programmed to be
> 16.6 ppm, the activity monitors should be
disabled so the input reference source is not
automatically rejected as out of frequency
range.
Output Clock Ports
The ACS8515 supports two SEC output clocks
on both TTL and PECL/LVDS ports and a pair
of secondary output clocks, Frame-Sync and
Multi-Frame-Sync. The two output clocks are
individually controllable. The Frame-Sync and
Multi-Frame-Sync are derived from the main
SEC clock. The frequencies of the output clock
are selectable from a range of pre-defined spot
frequencies, and a variety of output
technologies are supported, as defined in Table
5.
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Figure 2: Minimum Input Jitter Tolerance for inputs supporting G.703 compliant sources
Table 4: Amplitude and Frequency values for Jitter Tolerance for inputs supporting G.703 compliant sources
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Low-speed Output Clock
The O2 SEC clock is supplied on a TTL port with
a fixed frequency of 19.44 MHz.
High-speed Output Clock
The O1 SEC clock is supplied on a PECL/LVDS
port with spot frequencies of 19.44 MHz, 38.88
MHz, 155.52 MHz, 311.04 MHz and Dig 1
(where Dig 1 is 1.544/2.048 MHz and multiples
of 2, 4 and 8 depending on SONET/SDH mode
setting). The actual frequency is selectable via
the cnfg_differential_outputs register. The O1
port can also support 311.04 MHz, which is
enabled via the cnfg_T0_output_enable
register. The O1 port can be made LVDS or
PECL
compatible
via
the
cnfg_differential_outputs register.
Frame Sync and Multi-Frame Sync Clocks
Frame Sync (8 kHz) and Multi-Frame Sync (2
kHz) clocks will be provided on outputs FrSync
and MFrSync. The FrSync and MFrSync clocks
have a 50:50 mark space ratio.
Output Wander and Jitter
Wander and jitter present on the output clocks
are dependent on:
The magnitude of wander and jitter on the selected
input reference clock (in locked mode);
The internal wander and jitter transfer characteristic
(in locked mode);
The jitter on the local oscillator clock;
The wander on the local oscillator clock (in Hold-Over
mode).
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Table 5: Output Reference Source Selection table
Notes for Table 5.
Note 1. There are different output clock frequencies available for SONET and SDH applications. Dig 1 can be configured for
either frequency F
1
/F
2
, where the output frequency is F
1
when the SONET mode is selected, and F
2
when the SDH mode is
selected.
On power up, or by reset, the default will be set by the SONSDHB pin. Specific frequencies and priorities are set by
configuration. For SONET, config_mode register 34 Hex, bit 2 = 1. For SDH config_mode register 34 Hex, bit 2 = 0.
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Wander and jitter are treated in different ways
to reflect their differing impacts on network
design. Jitter is always strongly attenuated,
whilst wander attenuation can be varied to suit
the application and operating state. Wander and
jitter attenuation is performed by using a digital
phase locked loop (DPLL) with a programmable
bandwidth. This gives a transfer characteristic
of a low pass filter, with a programmable pole.
It is sometimes necessary to change the filter
dynamics to suit particular circumstances - one
example being when locking to a new source,
the filter can be opened up to reduce locking
time and can then be gradually tightened again
to remove wander. Since wander represents a
relatively long-term deviation from the nominal
operating frequency, it affects the rate of supply
of data to the network element. Strong wander
attenuation limits the rate of consumption of
data to within a smaller range, so a larger buffer
store is required to prevent data loss. But, since
any buffer store potentially increases latency,
wander may often only need to be removed at
specific points within a network where buffer
stores are acceptable, such as at digital cross
connects. Otherwise, wander is sometimes not
required to be attenuated and can be passed
through transparently. The ACS8515 has
programmable wander transfer characteristics
in a range from 0.1 Hz to 20 Hz. The wander
and jitter transfer characteristic is shown in
Figure 3.
Wander on the local oscillator clock will not
have significant effect on the output clock whilst
in locked mode, so long as the DPLL bandwidth
is set high enough so that the DPLL can
compensate quickly enough for any frequency
changes in the crystal. In free-running or
Holdover mode wander on the crystal is more
significant. Variation in crystal temperature or
supply voltage both cause drifts in operating
frequency, as does ageing. These effects must
be limited by careful selection of a suitable
component for the local oscillator, as specified
in the section Local Oscillator Clock.
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Figure 3: Wander and Jitter Transfer Characteristsics
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Phase Variation
There will be a phase shift across the ACS8515
between the selected input reference source
and the output clock. This phase shift may vary
over time but will be constrained to lie within
specified limits. The phase shift is characterised
using two parameters, MTIE (Maximum Time
Interval Error), and TDEV (Time Deviation), which,
although being specified in all relevent
specifications, differ in acceptable limits in each
one. Typical measurements for the ACS8515
are shown in Figures 4 and 5, for locked mode
operation. Figure 6 shows a typical
measurement of Phase Error accumulation in
Holdover mode operation.
The required performance for phase variation
during Holdover is specified in several ways
depending upon the particular circumstances
pertaining:
1. ETSI 300 462-5, Section 9.1, requires that the short-
term phase error during switchover (i.e., Locked to
Holdover to Locked) be limited to an accumulation rate
no greater than 0.05 ppm during a 15 second interval.
2. ETSI 300 462-5, Section 9.2, requires that the long-
term phase error in the Holdover mode should not
exceed {(a1+a2)S+0.5bS
2
+c}, where
a1 = 50 ns/s (allowance for initial frequency offset)
a2 = 2000 ns/s (allowance for temperature variation)
b = 1.16x10
-4
ns/s
2
(allowance for ageing)
c = 120 ns (allowance for entry into Holdover mode).
3. ANSI Tin1.101-1994, Section 8.2.2, requires that
the phase variation be limited so that no more than
255 slips (of 125 s each) occur during the first day of
Holdover. This requires a frequency accuracy better
than:
((24x60x60)+(255x125s))/(24x60x60) = 0.37 ppm.
Temperature variation is not restricted, except to within
the normal bounds of 0 to 50 Celsius.
4. Bellcore GR.1244.CORE, Section 5.2. Table 4. shows
that an initial frequency offset of 50 ppb is permitted
on entering Holdover, whilst a drift over temperature
of 280 ppb is allowed; an allowance of 40 ppb is
permitted for all other effects.
5. ITU G.822, Section 2.6, requires that the slip rate
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Figure 4: Maximum Time Interval Error of T
OUT0
output port
Figure 5: Time Deviation of T
OUT0
output port
Figure 6: Phase error accumulation of T
OUT0
output port in Holdover mode
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T im e
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ACS8515 LC/P
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during category(b) operation (interpreted as being
applicable to Holdover mode operation) be limited to
less than 30 slips (of 125 s each) per hour
((((60 x 60)/30)+125s)/(60x60)) = 1.042 ppm.
Phase Build Out
Phase Transient response and Holdover
Phase Build Out (PBO) is the function to minimise
phase transients on the output SEC clock during
input reference switching or mode switching. If
the currently selected input reference clock
source is lost (due to a short interruption, out
of frequency detection, or complete loss of
reference), the second, next highest priority
reference source will be selected. During this
transition, the Lost_Phase mode is entered.
The typical phase disturbance on clock
reference source switching will be less than 10
ns on the ACS8515. For clock reference
switching caused by the main input failing or
being disconnected, then the phase disturbance
on the output will still be less than the 120 ns
allowed for in the G.813 spec. The actual
value is dependant on the frequency being
locked to.
The PBO requirement, as specified in Telcordia
GR1244-CORE, Section 5.7, in that a phase
transient of greater than 3.5 s occuring in
less than 0.1 seconds should be absorbed, will
be implemented on a future version. ITU-T
G.813 states that the max allowable short term
phase transient response, resulting from a
switch from one clock source to another, with
Holdover mode entered in between, should be
a maximum of 1 s over a 15 second interval.
The maximum phase transient or jump should
be less than 120 ns at a rate of change of less
than 7.5 ppm and the Holdover performance
should be better than 0.05 ppm.
On the ACS8515, PBO can be enabled, disabled
or frozen using the P interface. By default, it
is enabled. When PBO is enabled, it can also
be frozen, which will disable the PBO operation
on the next input reference switch, but will
remain with the current offset. If PBO is
disabled while the device is in the Locked mode,
there will be a phase jump on the output SEC
clocks as the DPLL locks back to 0 degree
phase error.
Micro-Processor Interface
The ACS8515 incorporates a serial
microprocessor interface that is compatible with
the Serial Peripheral Interface (SPI) for device
setup.
Register Set
All registers are 8-bits wide, organised with the
most-significant bit positioned in the left-most
bit, with bit-significance decreasing towards the
right-most bit. Some registers carry several
individual data fields of various sizes, from
single-bit values (e.g., flags) upwards. Several
data fields are spread across multiple registers;
their organisation is shown in the register map.
Configuration Registers
Each configuration register reverts to a default
value on power-up or following a reset. Most
default values are fixed, but some will be pin-
settable. All configuration registers can be read
out over the microprocessor port.
Status Registers
The Status Registers contain readable registers.
They may all be read from outside the chip but
are not writable from outside the chip (except
for a clearing operation). All status registers
are read via shadow registers to avoid data
hits due to dynamic operation. Each individual
status register has a unique location.
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Register Access
Most registers are of one of two types,
configuration registers or status registers, the
exceptions being the Chip_revision register.
Configuration registers may be written to or read
from at any time (the complete 8-bit register
must be written, even if only one bit is being
modified). All status registers may be read at
any time and, in some status registers (such as
the sts_interrupts register), any individual data
field may be cleared by writing a "1" into each
bit of the field (writing a "0" value into a bit will
not affect the value of the bit). Details of each
register are given in the Register Map and
Register Description sections.
Interrupt Enable and Clear
Interrupt requests are flagged on pin INTREQ
(active High).
Bits in the interrupt status register are set (high)
by the following conditions;
(i) any reference source becoming valid or going invalid
(ii) a change in the operating state (eg. Locked,
Holdover etc.)
(iii) brief loss of the currently selected reference source
All interrupt sources are maskable via the mask
register (cnfg_interrupt_mask), each one being
enabled by writing a '1' to the appropriate bit.
Any unmasked bit set in the interrupt status
register will cause the interrupt request pin to
be asserted (high).
All interrupts are cleared by writing a '1' to the
bit(s) to be cleared in the status register.
When all pending unmasked interrupts are
cleared the interrupt pin will go inactive (low).
The loss of the currently selected reference
source will eventually cause the input to be
considered invalid, triggering an interrupt. The
time taken to raise this interrupt is dependant
on the leaky bucket configuration of the activity
monitors. The very fastest leaky bucket setting
will still take up to 128 ms to trigger the
interrupt. The interrupt caused by the brief
loss of the currently selected reference source
is provided to facilitate very fast source failure
detection if desired. It is triggered after missing
just a couple of cycles of the reference source.
Some applications require the facility to switch
downstream devices based on the status of
the reference sources. In order to provide extra
flexibility, it is possible to flag the "main
reference failed" interrupt (addr 06, bit 6) on
the pin TDO. This is simply a copy of the status
bit in the interrupt register and is independent
of the mask register settings. The bit is reset
by writing to the interrupt status register in the
normal way. This feature can be enabled and
disabled by writing to bit 6 of register 48Hex.
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Register map
Shaded areas in the map are dont care and writing either 0 or 1 will not affect any function of
the device.
Bits labelled Set to 0 or Set to 1 must be set as stated during initialisation of the device,
either following power up, or after a power on reset (POR). Failure to correctly set these bits may
result in the device operating in an unexpected way.
Some registers do not appear in this list, for example 07 and 08. These are either not used, or
have test functionality. Do not write to any undefined registers as this may cause the device to
operate in a test mode. If an undefined register has been inadvertently addressed, the device
should be reset to ensure the undefined registers are at default values.
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25
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Revision 2.05/Jan 2001 2001 Semtech Corp
www.semtech.com
27
ACS8515 LC/P
ADVANCED COMMUNCIATIONS
FINAL
the higher priority source until instructed to do
so by the software, by briefly setting the
Revertive mode bit. When there is a reference
available with higher priority than the selected
reference, there will be NO change of reference
source as long as the Non-Revertive mode
remains on. This is the case even of there are
lower priority references available or the
currently selected reference fails. When the
ONLY valid reference sources that are available
have a lower priority than the selected
reference, a failure of the selected reference
will always trigger a switch-over regardless of
whether Revertive or Non-revertive mode has
been chosen.
Automatic Control Selection
When automatic selection is required, the
'cnfg_ref_selection' registers must be set to all-
zero.
The
configuration
registers,
'cnfg_ref_selection_priority', held in the P port
are organised as 5, 4-bit registers with each
representing an input reference port. Unused
ports should be given the value, '0000' in the
relevant register to indicate they are not to be
included in the priority table. On power-up, or
following a reset, the whole of the configuration
file will be defaulted to the values defined by
Table 1. The selection priority values are all
relative to each other, with lower-valued
numbers taking higher priorities. Each reference
source should be given a unique number, the
valid values are 1 to 15(dec). A value of 0
disables the reference source. However if two
or more inputs are given the same priority
number those inputs will be selected on a first
in, first out basis. If the first of two same priority
number sources goes invalid the second will be
switched in. If the first then becomes valid
again, it becomes the second source on the
first in, first out basis, and there will not be a
switch. If a third source with the same priority
number as the other two becomes valid, it joins
the priority list on the same first in, first out
basis. There is no implied priority based on the
Selection of Input Reference Clock
Source
Under normal operation, the input reference
sources are selected automatically by an order
of priority, where SEC1 is the highest priority,
SEC2 is the second highest priority and SEC3
is the lowest priority. The priorities can be re-
assigned with external software. The SEC1
reference source has inputs via either a low
speed TTL input port or a high speed PECL/
LVDS input port. Similarly, the SEC2 reference
source has both a low speed TTL or a high
speed PECL/LVDS input port. The SEC3
(standby) reference source only has provision
via a low speed TTL input port. There is provision
for one sync clock input via a TTL port. Whilst
SEC1, SEC2 and SEC3 reference source inputs
can all be active at the same time, only one of
the TTL or PECL/LVDS input ports for the SEC1
and SEC2 reference sources may be used at
any time, the inactive port is ignored, by setting
the priority of that port to zero.
Restoration of repaired reference sources is
handled carefully to avoid inadvertent
disturbance of the output clock. The ACS8515
has two modes of operation; Revertive and non-
Revertive. In Revertive mode, if a re-validated
(or newly validated) source has a higher priority
than the reference source which is currently
selected, a switch over will take place. Many
applications prefer to minimise the clock
switching events and choose Non-Revertive
mode. In Non-Revertive mode , when a re-
validated (or newly validated) source has a
higher priority then the selected source will be
maintained. The re-validation of the reference
source will be flagged in the sts_sources_valid
register and, if not masked, will generate an
interrupt. Selection of the re-validated source
can only take place under software control -
the software should briefly enable Revertive
mode to affect a switch-over to the higher
priority source. If the selected source fails under
these conditions the device will still not select
Revision 2.05/Jan 2001 2001 Semtech Corp
www.semtech.com
28
ACS8515 LC/P
ADVANCED COMMUNCIATIONS
FINAL
events occur at a rate which is not sufficient to
overcome the decay, the alarm will not be
triggered. On the alarm-clearing side, if no defect
events occur for a sufficient time, the amplitude
will decay gradually and the alarm will be cleared
when the amplitude falls below the alarm-
clearing threshold. The ability to decay the
amplitude over time allows the importance of
defect events to be reduced as time passes
by. This means that, in the case of isolated
events, the alarm will not be set, whereas, once
the alarm becomes set, it will be held on until
normal operation has persisted for a suitable
time (but if the operation is still erratic, the
alarm will remain set).
The "leaky bucket" accumulators are
programmable for size, alarm set & reset
thresholds and decay rate. Each source is
monitored over a 128 ms period. If, within a
128 ms period, an irregularity occurs that is
not deemed to be due to allowable jitter/wander,
then the accumulator is incremented. The
accumulator will continue to increment up to
the point that it reaches the programmed
bucket size. The "fill rate" of the leaky bucket
is, therefore, 8 units/second. The "leak rate"
channel numbers.
Activity Monitoring
The ACS8515 has a combined inactivity and
irregularity monitor. The ACS8515 uses a "leaky
bucket" accumulator, which is a digital circuit
which mimics the operation of an analog
integrator, in which input pulses increase the
output amplitude but die away over time. Such
integrators are used when alarms have to be
triggered either by fairly regular defect events,
which occur sufficiently close together, or by
defect events which occur in bursts. Events
which are sufficiently spread out should not
trigger the alarm. By controlling the alarm-
setting threshold, the point at which the alarm
is triggered can be controlled. The point at which
the alarm is cleared depends upon the decay
rate and the alarm-clearing threshold. On the
alarm-setting side, if several events occur close
together, each event adds to the amplitude
and the alarm will be triggered quickly; if events
occur a little more spread out, but still
sufficiently close together to overcome the
decay, the alarm will be triggered eventually. If
Figure 7: Inactivity and irregularity monitoring
reference
leaky bucket
source
response
alarm
bucket_size
upper_threshold
lower_threshold
(all programmable)
programmable fall slopes
inactivities/irregularities
Revision 2.05/Jan 2001 2001 Semtech Corp
www.semtech.com
29
ACS8515 LC/P
ADVANCED COMMUNCIATIONS
FINAL
The time taken to raise an inactivity alarm on a reference source that has previously been fully active (leaky
bucket empty) will be:
(cnfg_activ_upper_threshold N)
8
where N is the number of the relevent leaky bucket configuration. If an input is intermittently inactive then
this time can be longer. The default setting of cnfg_activ_upper_threshold is 6, therefore the default time is
0.75 s.
The time taken to cancel the activity alarm on a previously completely inactive reference source is calculated
as:
2
x ((cnfg_bucket_size N) - (cnfg_activ_lower_thrshold N))
8
where N is the number of the relevent leaky bucket configuration in each case. The default setting are shown
in the following:
2 x (8-4) = 1.0 s
8
secs
secs
(cnfg_decay_rate N)
Leaky bucket timing
1
of the leaky bucket is programmable to be in
multiples of the fill rate (x1, x0.5, x0.25 and
x0.125) to give a programmable leak rate from
8 units/sec down to 1 unit/sec. A conflict
between trying to leak at the same time as a
fill is avoided by preventing a leak when a
fill event occurs.
Disqualification of a non-selected reference
source is based on inactivity, or on an out of
band result from the frequency monitors. The
currently selected reference source can be
disqualified for phase, frequency, inactivity or if
the source is outside the DPLL lock range. If
the currently selected reference source is
disqualified, the next highest priority, active
reference source is selected.
Restoration of repaired reference sources is
handled carefully to aviod inadvertant disruption
of the output clock. The ACS8515 operates in
a Non-revertive mode by default. In this mode,
if the restored reference source has a higher
priority than the reference source which is
currently selected, a switch-over to the restored
source will not tale place automatically. A
restored reference source will assume its
correct place in the priority table but a switch-
over will only take place automatically upon
failure of the currently selected source. It is
possible to invoke a switch-over by external
control or by enabling revertive mode.
Ultra Fast Switching
A reference source is normally disqualified after
the leaky bucket monitor thresholds have been
crossed. An option for a faster disqualification
has been implemented, whereby if register 48H,
bit 5 (Ultra Fast Switching), is set then a loss of
activity of just a few reference clock cycles will
set the no activity alarm and cause a
reference switch. This can be chosen to cause
an interrupt to occur instead of or as well as
causing the reference switch.
Revision 2.05/Jan 2001 2001 Semtech Corp
www.semtech.com
30
ACS8515 LC/P
ADVANCED COMMUNCIATIONS
FINAL
Free-Run mode
The Free-Run mode is typically used following a
power-on-reset or a device reset before
network synchronisation has been achieved. In
the Free-Run mode, the timing and
synchronisation signals generated from the
ACS8515 are based on the Master clock
frequency provided from the external oscillator
and are not synchronised to an input reference
source. The frequency of the output clock is a
fixed multiple of the frequency of the external
oscillator, and the accuracy of the output clock
is equal to the accuracy of the Master clock.
The transition from Free-Run to Pre-locked(1)
occurs when the ACS8515 selects a reference
source.
Pre-Locked(1) mode
The ACS8515 will enter the Locked state in a
maximum of 100 seconds, as defined by GR-
1244-CORE specification, if the selected
reference source is of good quality. If the device
cannot achieve lock within 100 seconds, it
reverts to Free-Run mode and another
reference source is selected.
Locked mode
The Locked mode is used when an input
reference source has been selected and the
PLL has had time to lock. When the Locked
mode is achieved, the output signal is in phase
and locked to the selected input reference
source. The selected input reference source is
determined by the priority table. When the
ACS8515 is in Locked mode, the output
frequency and phase follows that of the
selected input reference source. Variations of
the external crystal frequency have a minimal
effect on the output frequency. Only the
minimum to maximum frequency range is
affected. Note that the term, 'in phase', is not
applied in the conventional sense when the
ACS8515 is used as a frequency translator (e.g.,
when the input frequency is 2.048 MHz and
External Protection Switching
Fast external switching between inputs SEC1
and SEC2 can also be triggered directly from a
dedicated pin (SRCSW). This mode can be
activated either by holding this pin high during
reset, or by writing to bit 4 of register address
48Hex.
Once external protection switching is enabled,
then the value of this pin directly selects either
SEC1 (SRCSW high) or SEC2 (SRCSW low). If
this mode is activated at reset by pulling the
SRCSW pin high, then it configures the default
frequency tolerance of SEC1 and SEC2 to +/-
80 ppm (register address 41Hex and 42Hex).
Any of these registers can be subsequently set
by external s/w if required.
When external protection switching is enabled,
the device will operate as a simple switch. All
clock monitoring is disabled and the DPLL will
simply be forced to try to lock on to the
indicated reference source. The operating state
(sts_operating_mode register) will always
indicate locked in the mode.
Modes of Operation
The ACS8515 has three primary modes of
operation (Free-Run, Locked and Holdover)
supported by three secondary, temporary
modes (Pre-Locked, Lost_Phase and Pre-
Locked2). These are shown in the State
Transition Diagram, Figure 6.
The ACS8515 can operate in Forced or
Automatic control. On reset, the ACS8515
reverts to Automatic Control, where transitions
between states are controlled completely
automatically. Forced Control can be invoked
by configuration, allowing transitions to be
performed under external control. This is not
the normal mode of operation, but is provided
for special occasions such as testing, or where
a high degree of hands-on control is required.
Revision 2.05/Jan 2001 2001 Semtech Corp
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31
ACS8515 LC/P
ADVANCED COMMUNCIATIONS
FINAL
the output frequency is 19.44 MHz) as the input
and output cycles will be constantly moving past
each other; however, this variation will itself be
cyclical over time unless the input and output
are not locked.
Lost_Phase mode
Lost_Phase mode is used whenever the
selected reference source suffers most kinds
of anomalous behaviour. Clock generation is
performed in the same way as in the Holdover
mode. If the leaky bucket accumulator
calculates that the anomaly is serious, the
device rejects the reference source and one of
the following transitions takes place:
Go to Pre-Locked(2);
- If a known-good standby source is available.
Go to Holdover;
- If no standby sources are available.
Holdover mode
The Holdover mode is used when the circuit
was in Locked mode but the selected reference
source has become unavailable and a
replacement has not yet been selected.
The Holdover performance is mainly limited by
what is happening to the TCXO. The ACS8515
has 3 ways of determining Holdover, either;
1. By external frequency setting (cnfg_holdover_offset
register)
2. By an internal frequency measuring and averaging
system which averages the last 20 minutes
3. By just using the last frequency (as reported by the
sts_curr_inc_offset register). This value can be read
out of the device and used to build up a longer term
average using an external averaging circuit. This value
can then to readback into the device and used as the
Holdover offset (via cnfg_holdover_offset register).
By default it uses the internal averager. This
means that if the TCXO frequency is varying
due to temperature fluctuations in the room,
then the instantaneous value can be different
from the average value, and then it may be
possible to exceed the 0.05 ppm limit
(depending on how extreme the temperature
fluctuations are). It is advantageous to shield
the TCXO to slow down frequency changes due
to drift and external temperature fluctuations.
In Holdover mode, the ACS8515 provides the
timing and synchronisation signals to maintain
the Network Element (NE), but they are not
phase locked to any input reference source.
The timing is based on a stored value of the
frequency ratio obtained during the last Locked
mode period.
The frequency accuracy of Holdover mode has
to meet the ITU-T, ETSI and Telcordia
performance requirements. The performance
of the external oscillator clock is critical in this
mode, although only the frequency stability is
important - the stability of the output clock in
Holdover is directly related to the stability of
the external oscillator.
Pre-Locked(2) mode
This state is very similar to the Pre-Locked(1)
state. It is entered from the Holdover state
when a reference source has been selected
and applied to the phase locked loop. It is also
entered if the device is operating in revertive
mode and a higher-priority reference source is
restored.
PORB
The Power On Reset (PORB) pin resets the
device if forced Low for a power-on-reset to be
initiated. The reset is asynchronous, the
minimum Low pulse width is 5 ns. Reset is
needed to initialize all of the register values to
their defaults. Asserting Reset (POR) is required
at power on, and may be re-asserted at any
time to restore defaults. This is implemented
Revision 2.05/Jan 2001 2001 Semtech Corp
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32
ACS8515 LC/P
ADVANCED COMMUNCIATIONS
FINAL
pre-locked
w ait f or up to 100s
(state 110)
locked
keep ref
(state 100)
holdover
select ref
(state 010)
(2) all refs evaluated
&
at least one ref valid
(5) selected ref
phase locked
(3) no valid standby ref
&
(main ref invalid
or out of lock >100s)
(14) all refs evaluated
&
at least one ref valid
pre-locked2
w ait f or up to 100s
(state 101)
(10) selected source phase
locked
(6) no valid standby ref
&
main ref invalid
free-run
select ref
(state 001)
(1)Reset
Reference sources are flagged as 'valid' when
active, 'in-band' and have no phase alarm set.
All sources are continuously checked for
activity and frequency.
Only the main source is checked for phase.
A phase lock alarm is only raised on a
reference when that reference has lost phase
whilst being used as the main reference. The
micro-processor can reset the phase lock
alarm.
A source is considered to have phase locked
when it has b een continuously in phase lock
for between 1 and 2 seconds
Lost phase
w ait f or up to 100s
(state 111)
(7) phase lost
on main ref
(8) phase
regained within
100s
(12) valid standby ref
&
(main ref invalid
or out of lock >100s)
(13) no valid standby ref
&
(main ref invalid
or out of lock >100s)
(11) no valid standby ref
&
(main ref invalid
or out of lock >100s)
(9) valid standby ref
&
[ main ref invalid or
(higher-priority ref valid
& in revertive mode) ]
(15) valid standby ref
&
[ main ref invalid or
(higher-priority ref valid
& in revertive mode) or
out of lock >100s]
(4) valid standby ref
&
[ main ref invalid or
(higher-priority ref valid
& in revertive mode) or
out of lock >100s]
Figure 8: Automatic Mode Control State Diagram.
most simplistically by an external capacitor to
GND along with the internal pull-up resistor.
The ACS8510 is held in a reset state for 250
ms after the PORB pin has been pulled High. In
normal operation PORB should be held High.
Revision 2.05/Jan 2001 2001 Semtech Corp
www.semtech.com
33
ACS8515 LC/P
ADVANCED COMMUNCIATIONS
FINAL
Electrical Specification
Important Note: The "Absolute Maximum Ratings" are stress ratings only, and functional operation
of the device at conditions other than those indicated in the "Operating Conditions" sections of
this specification are not implied. Exposure to the absolute maximum ratings for an extended
period may reduce the reliability or useful lifetime of the product.
ABSOLUTE MAXIMUM RATINGS
OPERATING CONDITIONS
P
R
E
T
E
M
A
R
A
S
L
O
B
M
Y
M N
I
M X
A
U
S
T
I
N
p
p
u
S
e
g
a
tl
o
V
y
l
V
D
D
V
,
D
V
,
+
A
,
+
1 V
A
+
2
V
D
D
5
.
0
-
6
.
3
V
e
g
a
tl
o
V
t
u
p
n
I
)
s
n
i
p
y
l
p
p
u
s
-
n
o
n
(
n
i
V
-
5
.
5
V
e
g
a
tl
o
V
t
u
p
t
u
O
)
s
n
i
p
y
l
p
p
u
s
-
n
o
n
(
t
u
o
V
-
5
.
5
V
e
r
u
t
a
r
e
p
m
e
T
g
n
it
a
r
e
p
O
t
n
e
i
b
m
A
e
g
n
a
R
T
A
0
4
-
5
8
C
e
r
u
t
a
r
e
p
m
e
T
e
g
a
r
o
t
S
T
r
o
t
s
0
5
-
0
5
1
C
R
E
T
E
M
A
R
A
P
L
O
B
M
Y
S
N
I
M
P
Y
T
X
A
M
S
T
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N
U
V
n
i
h
g
i
H
V
h
i
0
.
2
-
-
V
V
n
i
w
o
L
V
li
-
-
8
.
0
V
t
n
e
rr
u
c
t
u
p
n
I
I
n
i
-
-
0
1
A
DC CHARACTERISTICS: TTL Input pad.
Across operating conditions, unless otherwise stated
P
R
E
T
E
M
A
R
A
S
L
O
B
M
Y
N
I
M
P
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M
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)
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g
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(
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P
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+
2
A
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,
+
1
A
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,
+
D
V
,
F
F
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D
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,
D
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0
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3
3
.
3
6
.
3
V
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(
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5
/
3
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3
5
.
5
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0
4
-
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5
8
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t
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rr
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p
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H
M
9
1
e
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o
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l
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/
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b
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0
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it
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tf
a
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1
,
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it
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it
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5
1
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0
9
1
A
m
n
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a
p
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d
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w
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p
l
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t
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T
P
T
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T
-
0
6
3
5
8
6
W
m
Revision 2.05/Jan 2001 2001 Semtech Corp
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34
ACS8515 LC/P
ADVANCED COMMUNCIATIONS
FINAL
DC CHARACTERISTICS: TTL Input pad with internal pull-up.
Across operating conditions, unless otherwise stated
R
E
T
E
M
A
R
A
P
L
O
B
M
Y
S
N
I
M
P
Y
T
X
A
M
S
T
I
N
U
V
n
i
h
g
i
H
V
h
i
0
.
2
-
-
V
V
n
i
w
o
L
V
li
-
-
8
.
0
V
r
o
t
s
i
s
e
r
p
u
-l
l
u
P
U
P
0
3
-
0
8
W
k
t
n
e
rr
u
c
t
u
p
n
I
I
n
i
-
-
0
2
1
A
DC CHARACTERISTICS: TTL Input pad with internal pull-down.
Across operating conditions, unless otherwise stated
R
E
T
E
M
A
R
A
P
L
O
B
M
Y
S
N
I
M
P
Y
T
X
A
M
S
T
I
N
U
V
n
i
h
g
i
H
V
h
i
0
.
2
-
-
V
V
n
i
w
o
L
V
li
-
-
8
.
0
V
r
o
t
s
i
s
e
r
n
w
o
d
u
-l
l
u
P
D
P
0
3
-
0
8
W
k
t
n
e
rr
u
c
t
u
p
n
I
I
n
i
-
-
0
2
1
A
DC CHARACTERISTICS: TTL Output pad.
Across operating conditions, unless otherwise stated
R
E
T
E
M
A
R
A
P
L
O
B
M
Y
S
N
I
M
P
Y
T
X
A
M
S
T
I
N
U
w
o
L
t
u
o
V
A
m
4
=
l
o
I
l
o
V
0
-
4
.
0
V
h
g
i
H
t
u
o
V
A
m
4
=
h
o
I
h
o
V
4
.
2
-
V
t
n
e
rr
u
c
e
v
ir
D
D
I
-
-
4
A
m
Revision 2.05/Jan 2001 2001 Semtech Corp
www.semtech.com
35
ACS8515 LC/P
ADVANCED COMMUNCIATIONS
FINAL
DC CHARACTERISTICS: PECL Input/Output pad.
Notes:
Unused differential input ports should be left floating and set in LVDS mode, or the positive and negative inputs
tied to VDD and GND respectively.
Note 1. Assuming a differential input voltage of at least 100 mV.
Note 2. Unused differential input terminated to VDD-1.4v.
Note 3. With 50W load on each pin to VDD-2v. i.e. 82W to GND and 130W to VDD.
Across operating conditions, unless otherwise stated
R
E
T
E
M
A
R
A
P
L
O
B
M
Y
S
N
I
M
P
Y
T
X
A
M
S
T
I
N
U
e
g
a
tl
o
v
w
o
L
t
u
p
n
I
L
C
E
P
s
t
u
p
n
i
l
a
it
n
e
r
e
ff
i
D
)
1
e
t
o
N
(
V
L
C
E
P
L
I
-
D
D
V
5
.
2
-
5
.
0
-
D
D
V
V
e
g
a
tl
o
v
h
g
i
H
t
u
p
n
I
L
C
E
P
s
t
u
p
n
i
l
a
it
n
e
r
e
ff
i
D
)
1
e
t
o
N
(
V
L
C
E
P
H
I
-
D
D
V
4
.
2
-
4
.
0
-
D
D
V
V
e
g
a
tl
o
v
l
a
it
n
e
r
e
ff
i
D
t
u
p
n
I
V
L
C
E
P
D
I
1
.
0
-
4
.
1
V
e
g
a
tl
o
v
w
o
L
t
u
p
n
I
L
C
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P
t
u
p
n
i
d
e
d
n
e
e
l
g
n
i
S
)
2
e
t
o
N
(
V
S
_
L
C
E
P
L
I
-
D
D
V
4
.
2
-
5
.
1
-
D
D
V
V
e
g
a
tl
o
v
h
g
i
H
t
u
p
n
I
L
C
E
P
t
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p
n
i
d
e
d
n
e
e
l
g
n
i
S
)
2
e
t
o
N
(
V
S
_
L
C
E
P
H
I
1
-
D
D
V
3
.
-
5
.
0
-
D
D
V
V
t
n
e
rr
u
c
h
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p
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it
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r
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ff
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t
u
p
n
I
V
D
I
v
4
.
1
=
I
L
C
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P
H
I
0
1
-
-
0
1
+
A
t
n
e
rr
u
c
w
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L
t
u
p
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d
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p
n
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V
D
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v
4
.
1
=
I
L
C
E
P
L
I
0
1
-
-
0
1
+
A
e
g
a
tl
o
v
w
o
L
t
u
p
t
u
O
L
C
E
P
)
3
e
t
o
N
(
V
L
C
E
P
L
O
-
D
D
V
0
1
.
2
-
2
6
.
1
-
D
D
V
V
e
g
a
tl
o
v
h
g
i
H
t
u
p
t
u
O
L
C
E
P
)
3
e
t
o
N
(
V
L
C
E
P
H
O
5
2
.
1
-
D
D
V
-
8
8
.
0
-
D
D
V
V
e
g
a
tl
o
v
l
a
it
n
e
r
e
ff
i
D
t
u
p
t
u
O
L
C
E
P
)
1
e
t
o
N
(
V
L
C
E
P
D
O
0
8
5
-
0
0
9
V
m
Revision 2.05/Jan 2001 2001 Semtech Corp
www.semtech.com
36
ACS8515 LC/P
ADVANCED COMMUNCIATIONS
FINAL
130R
I6POS
I6NEG
I5NEG
I5POS
T06POS
T06NEG
T07POS
T07NEG
Z
O
=50
Z
O
=50
Z
O
=50
Z
O
=50
Z
O
=50
Z
O
=50
82R
DD
V
82R
130R
Z
O
=50
Z
O
=50
130R
82R
82R
130R
DD
V
DD
82R
130R
V
82R
130R
130R
82R
82R
130R
DD
V
GND
GND
GND
GND
8kHz, 1.544/2.048,
6.48, 19.44, 38.88,
51.84, 77.76 or
155.52 MHz
51.84, 77.76 or
155.52 MHz
8kHz, 1.544/2.048,
6.48, 19.44, 38.88,
19.44, 38.88, 155.52,
311.04 MHz & DIG1
19.44, 51.84, 77.76,
155.52 MHz
Recommended line termination for PECL Input/Output ports for VDD = 3.3V
DC CHARACTERISTICS: LVDS Input/Output pad.
Across operating conditions, unless otherwise stated
R
E
T
E
M
A
R
A
P
L
O
B
M
Y
S
N
I
M
P
Y
T
X
A
M
S
T
I
N
U
L S
D
V
e
g
n
a
r
e
g
a
tl
o
v
t
u
p
n
I
V
m
0
0
1
=
e
g
a
tl
o
v
t
u
p
n
i
l
a
it
n
e
r
e
ff
i
D
V
S
D
V
L
R
V
0
-
0
4
.
2
V
d
l
o
h
s
e
r
h
t
t
u
p
n
i
l
a
it
n
e
r
e
ff
i
D
S
D
V
L
V
H
T
I
D
0
0
1
-
-
0
0
1
+
mV
e
g
a
tl
o
v
l
a
it
n
e
r
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ff
i
D
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p
n
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D
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L
V
S
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L
D
I
1
.
0
-
4
.
1
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e
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n
a
t
s
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it
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t
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e
c
a
l
p
e
b
t
s
u
M
.
0
1
5
8
S
C
A
f
o
s
n
i
p
t
u
p
n
i
-
/
+
S
D
V
L
%
5
h
ti
w
W
0
0
1
e
b
d
l
u
o
h
s
r
o
t
s
i
s
e
R
e
c
n
a
r
e
l
o
t
R
M
R
E
T
5
9
0
0
1
5
0
1
W
e
g
a
tl
o
v
h
g
i
h
t
u
p
t
u
O
S
D
V
L
)
1
e
t
o
N
(
V
S
D
V
L
H
O
-
-
5
8
5
.
1
V
e
g
a
tl
o
v
w
o
l
t
u
p
t
u
O
S
D
V
L
)
1
e
t
o
N
(
V
S
D
V
L
L
O
5
8
8
.
0
-
-
V
e
g
a
tl
o
v
t
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t
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o
l
a
it
n
e
r
e
ff
i
D
S
D
V
L
)
1
e
t
o
N
(
V
S
D
V
L
D
O
0
5
2
-
0
5
4
V
m
L S
D
V
f
o
e
d
u
ti
n
g
a
m
n
i
e
g
r
a
h
C
r
o
f
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g
a
tl
o
v
t
u
p
t
u
o
l
a
it
n
e
r
e
ff
i
d
s
e
t
a
t
s
y
r
a
t
n
e
m
il
p
m
o
c
)
1
e
t
o
N
(
V
S
D
V
L
S
O
D
-
-
5
2
V
m
L S
D
V
e
g
a
tl
o
v
t
e
s
ff
o
t
u
p
t
u
o
C
5
2
=
e
r
u
t
a
r
e
p
m
e
T
)
1
e
t
o
N
(
V
S
D
V
L
S
O
5
2
1
.
1
-
5
7
2
.
1
V
Note 1. With 100W load between the differential outputs.
Revision 2.05/Jan 2001 2001 Semtech Corp
www.semtech.com
37
ACS8515 LC/P
ADVANCED COMMUNCIATIONS
FINAL
I6POS
I6NEG
I5NEG
I5POS
T06POS
T06NEG
T07POS
T07NEG
Z
O
=50
Z
O
=50
Z
O
=50
Z
O
=50
Z
O
=50
Z
O
=50
100R
Z
O
=50
Z
O
=50
8kHz, 1.544/2.048,
6.48, 19.44, 38.88,
51.84, 77.76 or
155.52 MHz
51.84, 77.76 or
155.52 MHz
8kHz, 1.544/2.048,
6.48, 19.44, 38.88,
19.44, 38.88, 155.52,
311.04 MHz & DIG1
19.44, 51.84, 77.76,
155.52 MHz
100R
100R
100R
Recommended line termination for LVDS Input/Output ports
Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8MHz
TCXO on ICT Flexacom + 10MHz reference from Wavetek 905.
n
o
i
t
i
n
i
f
e
d
t
s
e
T
d
e
s
u
r
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t
li
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p
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5
1
5
8
S
C
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m
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2
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p
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5
5
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8
G
z
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3
.
1
o
t
z
H
0
0
5
I
U
p
p
5
.
0
=
)
2
e
t
o
N
(
8
5
0
.
0
1
n
o
it
p
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z
H
M
2
5
.
5
5
1
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3
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1
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t
z
H
k
5
6
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p
p
1
.
0
=
)
3
e
t
o
N
(
8
4
0
.
0
)
2
e
t
o
N
(
8
4
0
.
0
2
n
o
it
p
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z
H
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2
5
.
5
5
1
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z
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3
.
1
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H
k
2
1
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p
p
1
.
0
=
)
4
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t
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N
(
3
5
0
.
0
)
5
e
t
o
N
(
3
5
0
.
0
)
6
e
t
o
N
(
8
5
0
.
0
)
7
e
t
o
N
(
3
5
0
.
0
)
2
e
t
o
N
(
3
5
0
.
0
)
3
e
t
o
N
(
8
5
0
.
0
)
8
e
t
o
N
(
7
5
0
.
0
)
9
e
t
o
N
(
5
5
0
.
0
)
0
1
e
t
o
N
(
7
5
0
.
0
)
1
1
e
t
o
N
(
7
5
0
.
0
)
2
1
e
t
o
N
(
7
5
0
.
0
)
3
1
e
t
o
N
(
3
5
0
.
0
z
H
M
8
4
0
.
2
r
o
f
2
1
8
G
&
3
1
8
G
1
n
o
it
p
o
z
H
k
0
0
1
o
t
z
H
0
2
I
U
p
p
5
0
.
0
=
)
4
1
e
t
o
N
(
6
4
0
.
0
DC CHARACTERISTICS:
Output Jitter Generation
Across operating conditions, unless otherwise stated
Revision 2.05/Jan 2001 2001 Semtech Corp
www.semtech.com
38
ACS8515 LC/P
ADVANCED COMMUNCIATIONS
FINAL
n
o
it
i
n
if
e
d
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T
d
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p
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0
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0
=
)
4
1
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N
(
6
3
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0
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a
c
ir
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2
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2
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6
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(
6
4
0
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0
z
H
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2
5
.
5
5
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(
8
5
0
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0
z
H
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5
5
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3
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t
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N
(
8
4
0
.
0
Revision 2.05/Jan 2001 2001 Semtech Corp
www.semtech.com
39
ACS8515 LC/P
ADVANCED COMMUNCIATIONS
FINAL
n
o
it
i
n
if
e
d
t
s
e
T
d
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s
u
r
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tl
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F
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p
s
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5
1
5
8
S
C
A
n
o
t
n
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m
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u
s
a
e
m
I
U
2
v
e
R
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H
M
4
4
5
.
1
r
o
f
1
1
4
2
6
T
&
T
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)
z
H
k
8
o
t
z
H
0
1
c
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p
s
r
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tl
i
F
(
z
H
k
0
4
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t
z
H
0
1
I
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s
m
r
2
0
.
0
=
)
4
1
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t
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N
(
5
5
0
0
.
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H
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4
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2
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4
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(
5
5
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0
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H
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4
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5
5
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H
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5
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(
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0
n
o
it
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if
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d
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5
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2
5
.
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5
1
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5
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3
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8
4
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l
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N
(
8
5
0
.
0
I
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s
m
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1
0
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3
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t
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(
6
0
0
.
0
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/
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t
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l
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2
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5
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0
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4
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t
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2
1
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1
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)
3
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t
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N
(
7
1
0
.
0
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U
s
m
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1
0
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)
3
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t
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N
(
3
0
0
.
0
4
4
5
.
1
,f
/
i
1
S
D
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C
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3
5
2
-
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k
0
4
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t
z
H
0
1
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1
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4
1
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t
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N
(
6
3
0
.
0
I
U
s
m
r
1
0
.
0
=
)
4
1
e
t
o
N
(
5
5
0
0
.
0
Revision 2.05/Jan 2001 2001 Semtech Corp
www.semtech.com
40
ACS8515 LC/P
ADVANCED COMMUNCIATIONS
FINAL
Notes for the output jitter generation tables
Note 1.
Filter used is that defined by test definition unless otherwise stated
Note 2.
5 Hz bandwidth, 19.44 MHz input, direct lock
Note 3.
5 Hz bandwidth, 19.44 MHz input, 8 kHz lock
Note 4.
20 Hz bandwidth, 19.44 MHz input, direct lock
Note 5.
20 Hz bandwidth, 19.44 MHz input, 8 kHz lock
Note 6.
10 Hz bandwidth, 19.44 MHz input, direct lock
Note 7.
10 Hz bandwidth, 19.44 MHz input, 8 kHz lock
Note 8.
2.5 Hz bandwidth, 19.44 MHz input, direct lock
Note 9.
2.5 Hz bandwidth, 19.44 MHz input, 8 kHz lock
Note 10.
1.2 Hz bandwidth, 19.44 MHz input, direct lock
Note 11.
1.2 Hz bandwidth, 19.44 MHz input, 8 kHz lock
Note 12.
0.6 Hz bandwidth, 19.44 MHz input, direct lock
Note 13.
0.6 Hz bandwidth, 19.44 MHz input, 8 kHz lock
Note 14.
5 Hz bandwidth, 2.048 MHz input, 8 kHz lock
n
o
it
i
n
if
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T
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8
G
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0
-
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N
-
R
T
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4
5
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5
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N
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6
3
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.
0
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&
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6
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0
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Revision 2.05/Jan 2001 2001 Semtech Corp
www.semtech.com
41
ACS8515 LC/P
ADVANCED COMMUNCIATIONS
FINAL
t
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t
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t
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t
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SERIAL MODE
In SERIAL mode, the device is configured to interface with a serial microprocessor bus. The following figures
show the timing diagrams of write and read accesses for this mode.
During read access the output data SDO is clocked out on the rising edge of SCLK when the active edge selection
control bit CLKE is 0 and on the falling edge when CLKE = 1.
Address, read/write control bit and write data are always clocked into the interface on the rising edge of SCLK.
Both input data SDI and clock SCLK are oversampled, filtered and synchronized to the 6MHz internal clock.
The serial interface clock (SCLK) is not required to run between accesses (i.e., when CSB = 1).
Microprocessor interface timing
CLKE = 1; SDO data is clocked out on the falling edge of SCLK
CLKE = 0; SDO data is clocked out on the rising edge of SCLK
Read access timing in SERIAL Mode.
Revision 2.05/Jan 2001 2001 Semtech Corp
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42
ACS8515 LC/P
ADVANCED COMMUNCIATIONS
FINAL
Read access timing in SERIAL Mode.
Write access timing in SERIAL Mode.
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Revision 2.05/Jan 2001 2001 Semtech Corp
www.semtech.com
43
ACS8515 LC/P
ADVANCED COMMUNCIATIONS
FINAL
Package information
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D
A
A2
A1
b
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Section A-A
Section B-B
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B
B
The top package body may be smaller than the bottom package body by as much as 0.15 mm.
To be determined at seating plane.
Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side.
D1 and E1 are maximum plastic body size dimensions including mold mismatch.
Details of pin 1 identifier are optional but will be located within the zone indicated.
Exact shape of corners can vary.
A1 is defined as the distance from the seating plane to the lowest point of the package body.
These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip.
Shows plating.
1 2 3
Revision 2.05/Jan 2001 2001 Semtech Corp
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44
ACS8515 LC/P
ADVANCED COMMUNCIATIONS
FINAL
Thermal conditions
The device is rated for full temperature range when this package is used with a 4 layer or more
PCB. Copper coverage must exceed 50%. All pins must be soldered to the PCB. Maximum
operating temperature must be reduced when the device is used with a PCB with less than these
requirements.
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Revision 2.05/Jan 2001 2001 Semtech Corp
www.semtech.com
45
ACS8515 LC/P
ADVANCED COMMUNCIATIONS
FINAL
Figure 9: A simplified Application Schematic.
A simplified Application Schematic for the ACS8515 is illustrated in Figure 9.
Application information
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Revision 2.05/Jan 2001 2001 Semtech Corp
www.semtech.com
46
ACS8515 LC/P
ADVANCED COMMUNCIATIONS
FINAL
Changes from revision 2.04 to 2.05, January 2001.
Revision History
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Revision 2.05/Jan 2001 2001 Semtech Corp
www.semtech.com
47
ACS8515 LC/P
ADVANCED COMMUNCIATIONS
FINAL
Ordering information
ISO9001
CERTIFIED
For additional information, contact the following:
Semtech Corporation Advanced Communications Products
E-Mail:
AdvCom@semtech.com
Internet:
http://www.semtech.com
USA:
652 Mitchell Road, Newbury Park, CA 91320-2289
Tel: +1 805 498 2111, Fax: +1 805 498 3804
FAR EAST:
11F, No. 46, Lane 11, Kuang Fu North Road, Taipei, Taiwan, R.O.C.
Tel: +886 2 2748 3380, Fax: +886 2 2748 3390
EUROPE:
Delta House, Chilworth Science Park, Southampton, Hants, SO16 7NS, UK
Tel: +44 23 80 769008, Fax: +44 23 80 768612
Disclaimers
Life support - This product is not designed or intended for use in life suport equipment, devices or
systems, or other critical applications. This product is not authorized or warranted by Semtech
Corporation for such use.
Right to change - Semtech Corporation reserves the right to make changes, without notice, to this
product. Customers are advised to obtain the latest version of the relevant information before
placing orders.
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