EDGE HIGH-PERFORMANCE PRODUCTS
1
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Edge818
Octal 18V Pin Electronics
Driver/window Comparator
Description
Features
Functional Block Diagram
Applications
Revision 1/ May 23, 2000
The Edge818 is an octal pin electronics driver and window
comparator fabricated in a wide voltage CMOS process.
It is designed specifically for Test During Burn In (TDBI)
applications, where cost, functional density, and power
are all at a premium.
The Edge818 incor porates eight channels of
programmable drivers and window comparators into one
14 mm X 20 mm 100 pin MQFP package. Each channel
has per pin driver levels, data, and high impedance
control. In addition, each comparator has per pin high
and low threshold levels.
The Edge818 uses "Flex In" and "Flex Out" digital inputs,
and can therefore mate directly with any digital technology
providing a minimum 2V swing. The digital outputs can
mate directly with any digital technology.
The 18V driver output and receiver input range allow the
Edge818 to interface directly with TTL, ECL, CMOS (3V,
5V, and 7V), LVCMOS, and custom level circuitry, as well
as the high voltage (Super Voltage) level required for
many special test modes for Flash Devices.
18V I/O Range
50 MHz Operation
Per Pin Flexibility
Programmable Input Thresholds
Flex In Digital Inputs
Flex Out Digital Outputs
Small footprint (100 pin MQFP)
Burn In ATE
Low Cost ATE
Instrumentation
8
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DATA
EN*
QA
COMP HIGH
COMP LOW
QB
VH VL
DOUT
CVA
VINP
CVB
+
+
2
2000 Semtech Corp.
www.semtech.com
EDGE HIGH-PERFORMANCE PRODUCTS
Edge818
PIN Description
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3
2000 Semtech Corp.
www.semtech.com
EDGE HIGH-PERFORMANCE PRODUCTS
Edge818
PIN Description (continued)
D
ATA
0
COMP
LOW
COMP
HIGH
CV
A0
CVB0
CV
A1
CVB1
VEE
VEE
VCC
VCC
CV
A2
CVB2
CV
A3
CVB3
VBB
VCC
VEE
VCC
VINP0
D
ATA
7
COMP
LOW
COMP
HIGH
CV
A7
CVB7
CV
A6
CVB6
VEE
VEE
VCC
VCC
CV
A5
CVB5
CV
A4
CVB4
VBB
VCC
VEE
VCC
VINP7
VH0
DOUT0
VL0
VINP1
VH1
DOUT1
VL1
VINP2
VH2
DOUT2
VL2
VINP3
VH3
DOUT3
VL3
VL4
DOUT4
VH4
VINP4
VL5
DOUT5
VH5
VINP5
VL6
DOUT6
VH6
VINP6
VL7
DOUT7
VH7
QA0
QB0
EN*0
DATA1
QA1
QB1
EN*1
DATA2
QA2
QB2
EN*2
DATA3
QA3
QB3
EN*3
EN*4
QB4
QA4
DATA4
EN*5
QB5
QA5
DATA5
EN*6
QB6
QA6
DATA6
EN*7
QB7
QA7
1
31
51
81
100 Lead - 14 x 20 MQFP
4
2000 Semtech Corp.
www.semtech.com
EDGE HIGH-PERFORMANCE PRODUCTS
Edge818
Circuit Description
Driver Description
The Edge818 supports programmable high and low levels
and tristate per channel. There are no shared lines
between any drivers. The EN* and DATA signals are
wide voltage high impedance analog inputs capable of
receiving digital signals over a wide common mode range.
VBB is the high impedance analog input which sets the
threshold for EN* and DATA.
EN*, DATA
Status
> VBB
"1"
< VBB
"0"
With EN* high, the driver goes into a high impedance
state. With EN* low, DATA high forces the driver into a
high state, and DATA low forces the driver into a low
state.
EN*
DATA
DOUT
1
X
HiZ
0
1
VH
0
0
VL
Drive High and Low
VH and VL define the logical "1" and "0" levels of the
driver, and can be adjusted anywhere over the range
determined by VCC and VEE. There are no restrictions
between VH and VL, other than they must remain within
the power supply levels.
VEE
VH
VCC
VEE
VL
VCC
The VH and VL inputs are unbuffered in that they also
provide the driver output current (see Figure 3), so the
source of VH and VL must have ample current drive
capability.
Figure 3. Simplified Model of the
Unbuffered Output Stage
Driver Output Protection
In a functional testing environment, where a resistor is
added in series with the driver output to create a 50
driver, the Edge818 can withstand a short to any legal
voltage for an indefinite amount of time.
In a low impedance application, with no additional output
resistance, the system should be designed to check for
a short circuit prior to connecting the driver, and tristate
the driver if a short is detected.
Receiver Description
The Edge818 suppor ts a window comparator with
independent threshold levels per channel. There are no
shared comparator lines between channels. CVA and
CVB are high impedance analog voltage inputs which
define the threshold voltages for comparators A and B.
If VINP is more positive than CVA or CVB, QA and QB will
be high. Otherwise, QA and QB will be low.
VINP
QA
VINP > CVA
COMP HIGH
VINP < CVA
COMP LOW
VINP
QB
VINP > CVB
COMP HIGH
VINP < CVB
COMP LOW
VH
VL
DUT
5
2000 Semtech Corp.
www.semtech.com
EDGE HIGH-PERFORMANCE PRODUCTS
Edge818
Circuit Description (continued)
The comparator outputs are "Flex Out". They are
technology independent and may be adjusted over a wide
voltage common mode range. COMP HIGH and COMP
LOW are analog inputs which set the digital high and low
levels (respectively) of QA and QB. COMP HIGH and
COMP LOW are unbuffered inputs that provide the
necessary drive current, so the sources for these levels
must have adequate current capability.
Figure 4. Simplified Model of the
Unbuffered Comparator Output Stage
Typically, COMP HIGH and COMP LOW will be connected
to the digital power supplies of the chip receiving QA
and QB.
Receiver Headroom
There is ~2V of headroom required between the
comparator thresholds and both power supply levels.
VEE + 2.0
CVA, CVB
VCC 2.0
COMP HIGH
COMP LOW
QAX, QBX
6
2000 Semtech Corp.
www.semtech.com
EDGE HIGH-PERFORMANCE PRODUCTS
Edge818
Application Information
Power Supply Decoupling
VCC and VEE should be decoupled to GND with a .1
F
chip capacitor in parallel with a .001
F chip capacitor.
A VCC and VEE plane, or at least a solid power bus, is
recommended for optimal performance.
VH and VL Decoupling
As the VH and VL inputs are unbuffered and supply the
driver output current, which can be quite large during
edge transitions, decoupling capacitors for these inputs
are recommended in proportion to the amount of output
current requirements.
For applications where VH and VL are shared over multiple
channels, a solid power plane to distribute these levels
is preferred.
VBB
The two VBB pins are connected together on-chip.
Therefore, only one VBB needs to be connected to for
proper 818 operation.
The two pins may be used to daisy chain a VBB signal
across a PC Board without having to route the actual
signal underneath the 818.
Latchup Protection
The Edge818 has several power supply requirements to
protect the part in power supply fault situations, as well
as during power up and power down sequences. VCC
must remain greater than or equal to VDD (external supply
for the digital logic) at all times. Both VCC and VDD
must always be positive (above ground), and VEE must
always be negative (at or below ground).
The three diode configuration shown in Figure 5 should
be used on a once-per-board basis.
Figure 5.
Power Supply Protection Scheme
gure 5.
Warning: It is extremely important that the voltage on
any device pin does not exceed the range of VEE
0.5V to VCC +0.5V at any time, either during power up,
normal operation, or during power down. Failure to
adhere to this requirement could result in latchup of
the device, which could be destructive if the system
power supplies are capable of supplying large amounts
of current. Even if the device is not immediately
destroyed, the cumulative damage caused by the stress
of repeated latchup may affect device reliability.
VCC
VDD
VEE
1N5820 or
Equivalent
7
2000 Semtech Corp.
www.semtech.com
EDGE HIGH-PERFORMANCE PRODUCTS
Edge818
Package Information
PIN Descriptions
D2
E2
D
Z
D
Z
E
4
3
3
D
3
B
4
E
A
e
SEE DETAIL "A"
TOP VIEW
0.25
C
D
4X
A B
0.20
4X
C
D
A B
D1
2
5
7
5
7
5
7
E1
C
O O
BOTTOM VIEW
100-Pin MQFP
14 mm x 20 mm
8
2000 Semtech Corp.
www.semtech.com
EDGE HIGH-PERFORMANCE PRODUCTS
Edge818
Package Information (continued)
A, B, D
3
e / 2
DETAIL "A"
0.40 MIN.
0 7
0.13 / 0.30 R. TYP.
GAGE
PLANE
BASE
PLANE
SEATING
PLANE
0.25
1.60 REF.
L
C
C
A2
0.10 S
0.13
R. MIN.
DETAIL "B"
0 MIN.
A1
H
0.076
C
2
8
12
B
12 16
12 16
D
C
S
M
S
ccc
A B
A
SEE DETAIL "B"
B
1
BASE METAL
0.13 / 0.17
0.13 / 0.23
1.28 REF.
WITH LEAD FINISH
SECTION CC
Notes:
1. All dimensions and tolerances conform to ANSI Y14.5-1982.
2. Datum plane -H- located at mold parting line and coincident
with lead, where lead exits plastic body at bottom of parting
line.
3. Datums A-B and -D- to be determined where centerline between
leads exits plastic body at datum plane -H-.
4. To be determined at seating plane -C-.
5. Dimensions D1 and E1 do not include mold protrusion.
Allowable mold protrusion is 0.254 mm per side. Dimensions
D1 and E1 do include mold mismatch and are determined at
datum plane -H-.
6. "N" is the total # of terminals.
7. Package top dimensions are smaller than bottom dimensions
and top of package will not overhang bottom of package.
8. Dimension B does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08 mm total in excess of the
dimension at maximum material condition. Dambar cannot
be located on the lowerradius or the foot.
9. All dimensions are in millimeters.
10. Maximum allowable die thickness to be assembled in this
package family is 0.635 millimeters.
11. This drawing conforms to JEDEC registered outlines MS-108
and MS-022.
12. These dimensions apply to the flat section of the lead between
0.10 mm and 0.25 mm from the lead tip.
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Variations
(all dimensions in millimeters)
9
2000 Semtech Corp.
www.semtech.com
EDGE HIGH-PERFORMANCE PRODUCTS
Edge818
Recommended Operating Conditions
Absolute Maximum Ratings
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Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at these, or any other conditions
beyond those listed, is not implied. Exposure to absolute maximum conditions for extended periods may
affect device reliability.
10
2000 Semtech Corp.
www.semtech.com
EDGE HIGH-PERFORMANCE PRODUCTS
Edge818
DC Characteristics
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Test conditions (unless otherwise specified): "Recommended Operating Conditions".
Note 1:
DC output current is specified per individual driver.
Note 2:
Surge current capability for durations of < 2 seconds.
Note 3:
Offset voltage is tested at CVA, CVB = 1.5V.
11
2000 Semtech Corp.
www.semtech.com
EDGE HIGH-PERFORMANCE PRODUCTS
Edge818
AC Characteristics
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Test conditions (unless otherwise specified): "Recommended Operating Conditions".
Note 1:
Load = 10 mA and measured when a 1V change at the output is detected. (VH = 3V,
VL = 0V, VFLOAT = 1.5V, tested at 1V and 2V.)
Note 2:
Into 18 cm of 50
transmission line terminate with 1 K
, with proper series termination
resistor.Guaranteed by characterization. This parameter is not tested in production.
Note 3:
This parameter is production tested at 40 MHz.
12
2000 Semtech Corp.
www.semtech.com
EDGE HIGH-PERFORMANCE PRODUCTS
Edge818
Ordering Information
Contact Information
Semtech Corporation
Edge High-Performance Division
10021 Willow Creek Rd., San Diego, CA 92131
Phone: (858)695-1808 FAX (858)695-2633
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