HIGH-PERFORMANCE PRODUCTS ATE
1
www.semtech.com
Edge670
500 MHz
Window Comparator
Description
Features
Functional Block Diagram
Revision 3 / July 20, 2001
PRELIMINARY
The Edge670 is a monolithic ATE pin electronics
comparator manufactured in a high-performance
complementary bipolar process. In automatic test
equipment, the Edge670 offers a window comparator
suitable for very fast, bidirectional channels in Memory,
VLSI, and Mixed-Signal test systems.
The 670 is capable of tracking very fast edges and
passing sub-ns pulses over an 11V common mode range
while maintaining excellent timing accuracy. The
differential digital outputs are adjustable to
accommodate ECL levels, PECL levels, or custom levels
to interface directly with a CMOS ASIC.
The Edge670 is pin compatible with the Edge672, except
no load is present.
QA*
VINP
CVA
CVB
QA
IPD
QB
QB*
PECL
+
+
11V Common Mode Range
Input Tracking > 6 V/ns with <
25 ps
dispersion
Low Leakage (<1
A)
Input Power Down Mode
(for extremely low leakage operation (<250 nA))
Small footprint (32 pin TQFP)
2
2000 Semtech Corp.
www.semtech.com
HIGH-PERFORMANCE PRODUCTS ATE
Edge670
PRELIMINARY
PIN Description
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3
2000 Semtech Corp.
www.semtech.com
HIGH-PERFORMANCE PRODUCTS ATE
PRELIMINARY
Edge670
PIN Description (continued)
N/C
N/C
N/C
N/C
VCC
VINP
VEE
VCC
N/C
N/C
VCC
QA
QA*
VEE
QB*
QB
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
VCC
GND
PECL
CA
THODE
ANODE
IPD
CV
A
CVB
32
25
17
9
1
4
2000 Semtech Corp.
www.semtech.com
HIGH-PERFORMANCE PRODUCTS ATE
Edge670
PRELIMINARY
Circuit Description
Window Comparator
Introduction
The Edge670 has two comparators connected on-chip
as a window comparator to determine whether the DUT
is in a high, low, or indeterminate state.
Power Supply Sequencing
The following sequence should be used when powering
up the Edge670.
1. VEE
2. VCC
3. Analog Inputs (VINP, CVA, CVB)
Functionality
The VINP pin is tied to the positive inputs of both
comparators (see Figure 1).
Input Condition
Output Condition
VINP > CVA
QA = High; QA* = Low
VINP < CVA
QA = Low; QA* = High
VINP > CVB
QB = High; QB* = Low
VINP < CVB
QB = Low; QB* = High
Figure 1. Comparator Functionality
Thresholds
CVA and CVB are the two comparator threshold levels.
These inputs are high impedance voltage controlled
inputs that determine at which VINP input voltage the
comparator will change states.
Hysteresis
Hysteresis is a measure of the change in threshold
voltage as a function of the comparator output state
(see Figure 2). Typically, hysteresis is used to prevent
multiple comparator output transitions due to slow input
slew rates in a noisy environment. These slower inputs
remain in the transition region for longer periods of time,
allowing any noise present to cause repeated threshold
crossings.
The Edge670 is designed with 4 mV of hysteresis. This
hysteresis is non-adjustable and requires no external
support. The amount of hysteresis was chosen to allow
stable and reliable transitions in most system
environments, without noticeably affecting the
comparator performance.
Figure 2. Hysteresis
The effects of hysteresis are visible in two categories -
offset voltage and propagation delay. The amount of
hysteresis must be large enough to overcome the system
noise floor, yet small enough not to increase offset
voltage effects significantly.
Input Protection
The VINP pin has an internal 50
series resistor and
two over-voltage diodes capable of shunting up to 100
mA (see Figure 3) and, therefore, requires no external
protection circuitry. The over-voltage input range that
the comparator can withstand is determined by the power
supply rails and the following equations:
VEE .7 (100 mA * 50
) < VINP <
VCC + .7 + (100 mA * 50
)
or
VEE 5.7V < VINP < VCC + 5.7V.
QA*
VINP
CVA
CVB
QA
QB
QB*
+
+
Actual Threshold Voltage
Programmed Threshold
Voltage
2 mV
4 mV
5
2000 Semtech Corp.
www.semtech.com
HIGH-PERFORMANCE PRODUCTS ATE
PRELIMINARY
Edge670
Circuit Description (continued)
Figure 3. Input Protection
For a wider protected input range, an additional external
series resistor may be added.
Comparator PECL Output Capability
PECL is a variable analog voltage power supply that
determines the common mode voltage of the comparator
digital outputs. With PECL connected to ground, the
Edge670 generates standard differential ECL outputs.
However, the outputs will track the PECL input, and
remaining one diode drop below it as PECL is varied
between ground and +5V. By setting PECL appropriately,
a fully differential comparator output may interface
directly to a CMOS ASIC without any translators.
Input Power Down
The Edge670 comparator has a mechanism where it can
drastically reduce the input bias current flowing into the
VINP pin, while still maintaining a functional comparator.
In this mode, however, the comparator slows down
significantly and can no longer track fast edges, in
particular, fast falling edges.
The IPD pin is a TTL compatible input which controls the
two modes. With IPD = low, the comparator is in its
normal high speed mode, supporting maximum AC
performance.
With IPD = high, the comparator is in Power Down Mode.
The input bias current decreases to < 100 nA. The
comparator still functions, but can track edges only up
to 25 mV/ns.
Thermal Monitor
The Edge670 includes an on-chip thermal monitor
accessible through the CATHODE and ANODE. These
nodes connect to five diodes in series (see Figure 4)
and may be used to accurately measure the junction
temperature at any time.
An external bias current of 100
A is injected through
the string, and the measured voltage corresponds to a
specific junction temperature with the following equation:
Tj[
C] = {(ANODE - CATHODE)/5 - .7} / (-.00208).
Figure 4. Thermal Diode String
Bias Current
Temperature coefficient = 10 mV/
C
ANODE
CATHODE
VINP
VCC
VEE
+
+
50
6
2000 Semtech Corp.
www.semtech.com
HIGH-PERFORMANCE PRODUCTS ATE
Edge670
PRELIMINARY
Circuit Description (continued)
Delay Dispersion
Given a constant temperature and voltage environment
(within the bounds of the recommended operating
conditions), the propagation delay dispersion (TSD)
indicates how much variation in propagation delay time
can be expected for one comparator over a wide range
of input conditions. Thus, the propagation delay of a
comparator can be described as:
Tpd
TSD
where TPD is the nominal delay that will vary with
temperature and voltage, and part to part. In many ATE
applications, Tpd is calibrated or compensated for on a
channel-by-channel basis. TSD includes factors that
normally may be difficult to calibrate, and therefore
directly impact overall system timing accuracy.
Propagation delay dispersion is defined as the maximum
deviation of the propagation delay taken at the eight
measurement points (see Figure 10) for 1V and 3V input
signals described below. The parameters of interest are:
Slew rate
Edge direction
Overdrive
Common mode voltage.
Low dispersion numbers indicate the accuracy of a
system under a variety of input conditions, and are an
important figure of merit for any comparator.
While not production tested, the Edg670 is designed
specifically to exhibit low dispersion. The typical Edge670
will show less than 25 ps Tpd dispersion.
3 V
2.7 V
.3 V
0 V
-0.8 V
-1.0 V
-1.6 V
-1.8 V
1V / NS
SLEW RATE
INPUT
THRESHOLD
LEVELS
3V / NS
SLEW RATE
1V
1V / NS
SLEW RATE
INPUT
THRESHOLD
LEVELS
3V / NS
SLEW RATE
3 V
Figure 10. Dispersion Measurement Conditions
7
2000 Semtech Corp.
www.semtech.com
HIGH-PERFORMANCE PRODUCTS ATE
PRELIMINARY
Edge670
Package Information
PIN Descriptions
b
D
3
4
4
e
N / 4 TIPS
4 X
E / 2
D / 2
SEE DETAIL "A"
E
0.20
C
A B
D
TOP VIEW
D1
E1
5
7
5
7
4 X
D1 / 2
E1 / 2
0.20
H
A B
D
BOTTOM VIEW
C
OO
32-Pin TQFP
7mm x 7 mm
8
2000 Semtech Corp.
www.semtech.com
HIGH-PERFORMANCE PRODUCTS ATE
Edge670
PRELIMINARY
Package Information (continued)
3
DETAIL "A"
e / 2
b
0 MIN.
0.08 / 0.20 R.
GAUGE PLANE
0.25
0 7
L
C.08
R. MIN.
0.20 MIN.
1.00 REF.
DATUM
PLANE
H
A1
0.05
A2
S
DETAIL "B"
9
;;;
;;;
S
S
D
C
ddd
M
A B
WITH LEAD FINISH
Lead
Cross Section
0.09 / 0.20
0.09 / 0.16
b
b
1
BASE METAL
2
8 PLACES
11 / 13
A
0.10
/ /
C
M
SEE DETAIL "B"
0.05
ccc
H
C
SECTION CC
Notes:
1.
All dimensions and tolerances conform to ANSI Y14.5-1982.
2.
Datum plane -H- located at mold parting line and coincident
with lead, where lead exits plastic body at bottom of parting
line.
3.
Datums A-B and -D- to be determined at centerline between
leads where leads exit plastic body at datum plane -H-.
4.
To be determined at seating plane -C-.
5.
Dimensions D1 and E1 do not include mold protrusion.
6.
"N" is the total # of terminals.
7.
These dimensions to be determined at the datum plane -H-.
8.
Package top dimensions are smaller than bottom dimensions
and top of package will not overhang bottom of package.
9.
Dimension b does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08 mm total in excess of the b
dimension at maximum material condition. Dambar cannot be
located on the lower radius or the foot.
10.
Controlling dimension: millimeter.
11.
Maximum allowable die thickness to be assembled in this
package family is 0.30 millimeters.
12.
This outline conforms to JEDEC publication 95, registration
MO-136, variations AC, AE, and AF.
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AC
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JEDEC VARIATION
9
2000 Semtech Corp.
www.semtech.com
HIGH-PERFORMANCE PRODUCTS ATE
PRELIMINARY
Edge670
Recommended Operating Conditions
Absolute Maximum Ratings
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Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the
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beyond those listed in the operational sections of this specification are not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
1 0
2000 Semtech Corp.
www.semtech.com
HIGH-PERFORMANCE PRODUCTS ATE
Edge670
PRELIMINARY
DC Characteristics
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DC test conditions (unless otherwise specified): "Recommended Operating Conditions".
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Assumes no digital output current
1 1
2000 Semtech Corp.
www.semtech.com
HIGH-PERFORMANCE PRODUCTS ATE
PRELIMINARY
Edge670
AC Characteristics
Ordering Information
Contact Information
Semtech Corporation
High-Performance Division
10021 Willow Creek Rd., San Diego, CA 92131
Phone: (858)695-1808 FAX (858)695-2633
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Guaranteed by characterization. This parameter is not production tested
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1 2
2000 Semtech Corp.
www.semtech.com
HIGH-PERFORMANCE PRODUCTS ATE
Edge670
PRELIMINARY
Revision History
#
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Current Revision: July 20, 2001
Previous Revision: March 5, 2001
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Current Revision: March 5, 2001
Previous Revision: August 12, 2000
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