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Электронный компонент: LCDA05TB

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1
www.semtech.com
PROTECTION PRODUCTS
LCDA05 THRU LCDA24
Low Capacitance TVS Diode Array
For High-Speed Data Interfaces
u
Transient protection for high-speed data lines to
IEC 61000-4-2 (ESD) 15kV (air), 8kV (contact)
IEC 61000-4-4 (EFT) 40A (tp = 5/50ns)
IEC 61000-4-5 (Lightning) 24A (tp = 8/20s)
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Protects two I/O lines
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Low capacitance for high-speed data lines
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Working voltages: 5V, 12V, 15V and 24V
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Low leakage current
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Low operating and clamping voltages
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Solid-state silicon avalanche technology
Description
Features
Circuit Diagram (Each Line Pair)
Schematic & PIN Configuration
Revision 9/2000
Applications
Mechanical Characteristics
SO-8 (Top View)
The LCDA series of TVS arrays are designed to protect
sensitive electronics from damage or latch-up due to
ESD and other voltage-induced transient events. Each
device will protect two high-speed lines. They are
available with operating voltages of 5V, 12V, 15V and
24V. They are bidirectional devices and may be used on
lines where the signal polarities are above and below
ground.
TVS diodes are solid-state devices designed specifically
for transient suppression. They offer desirable charac-
teristics for board level protection including fast re-
sponse time, low operating and clamping voltage and
no device degradation. The LCDA series devices
feature low capacitance compensation diodes in series
with standard TVS diodes to provide an integrated, low
capacitance solution for use on high-speed interfaces.
The LCDA series devices may be used to meet the
immunity requirements of IEC 61000-4-2, level 4.
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JEDEC SO-8 (MS-012AA) small outline package
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Molding compound flammability rating: UL 94V-0
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Marking : Part Number, Logo, Date Code
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Packaging : Tape and Reel per EIA 481
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High-Speed Data Lines
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Microprocessor Based Equipment
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Universal Serial Bus (USB) Port Protection
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Notebooks, Desktops, & Servers
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Instrumentation
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LAN/WAN Equipment
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Peripherals
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2000 Semtech Corp.
www.semtech.com
PROTECTION PRODUCTS
PROTECTION PRODUCTS
LCDA05 THRU LCDA24
Absolute Maximum Rating
Electrical Characteristics
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3
2000 Semtech Corp.
www.semtech.com
PROTECTION PRODUCTS
LCDA05 THRU LCDA24
5
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Electrical Characteristics (continued)
4
2000 Semtech Corp.
www.semtech.com
PROTECTION PRODUCTS
PROTECTION PRODUCTS
LCDA05 THRU LCDA24
Typical Characteristics
Non-Repetitive Peak Pulse Power vs. Pulse Time
Power Derating Curve
0
10
20
30
40
50
60
70
80
90
100
110
0
5
10
15
20
25
30
Time (
s)
Percent of I
PP
e
-t
td = I
PP
/2
Waveform
Parameters:
tr = 8
s
td = 20
s
Pulse Waveform
ESD Pulse Waveform (Per IEC 61000-4-2)
0.01
0.1
1
10
0.1
1
10
100
1000
Pulse Duration - tp (
s)
Peak Pulse Power - P
PP
(kW)
0
10
20
30
40
50
60
70
80
90
100
110
0
25
50
75
100
125
150
Ambient Temperature - T
A
(
o
C)
% of Rated Power or I
PP
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ESD Discharge Parameters Per IEC 61000-4-2
5
2000 Semtech Corp.
www.semtech.com
PROTECTION PRODUCTS
LCDA05 THRU LCDA24
Applications Information
Device Connection for Protection of Two High-Speed
Data Lines
The LCDAxx is designed to protect up to two high-speed
data lines. The LCDAxx utilizes a low capacitance
compensation diode in series with, but in opposite
polarity to a TVS diode in each line. The resulting
capacitance is less than 5pF per line. Each line will
only suppress transient events in one polarity. There-
fore, to achieve protection in both positive and nega-
tive polarity, a second TVS/rectifier pair is connected in
anti-parallel to the first. Pins 1, 2, 7, and 8 are used to
protect one data line. Pins 3, 4, 5, and 6 are used to
protect the second data line.
The device is connected as follows:
l
Pins 1 & 2 are tied together and pins 7 & 8 are tied
together providing the protection circuit for one I/O
line. Pins 3 & 4 are tied together and pins 5 & 6
are tied together providing the protection circuit for
the second I/O line. Since the device is electrically
symmetrical, either side of the connected pairs
may be used to protect the lines. The other side of
the pair is used to make the ground connection.
The ground connections should be made directly to
the ground plane for best results. The path length
is kept as short as possible to reduce the effects
of parasitic inductance in the board traces.
Circuit Board Layout Recommendations for Suppres-
sion of ESD.
Good circuit board layout is critical for the suppression
of ESD induced transients. The following guidelines are
recommended:
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Place the TVS near the input terminals or connec-
tors to restrict transient coupling.
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Minimize the path length between the TVS and the
protected line.
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Minimize all conductive loops including power and
ground loops.
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The ESD transient return path to ground should be
kept as short as possible.
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Never run critical signals near board edges.
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Use ground planes whenever possible.
I/O 1
I/O 2
I/O 1
I/O 2
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
Line 1
In/Out
Line 1
Ground
Line 2
In/Out
Line 2
Ground
From Connector
To Protected
Device
1
2
3
4
5
6
7
8
Line 1
In/Out
Ground
Line 2
In/Out
From Connector
To Protected
Device
Connection Options
I/O Line Protection
LCDA Connection Diagram