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POWER MANAGEMENT

Portable, VID Programmed Single

Phase Power Supply Controller

SC453

High speed hysteretic controller

Single phase operation

Selectable analog or VID controlled sleep setting

6 bit VID programmable output

Integrated drivers with soft high side turn-on

Programmable soft-start

Programmable boot voltage

Programmable sleep voltage with sleep mode

Under-voltage lock out on VCCA

Over-voltage protection on CORE

Current limit protection on CORE

Thermal protection

Power good fl ag with blanking during

CORE

changes

Automatic power save at light load

TSSOP-28 package

December 6, 2005

Description

Features

The SC453 IC is a single chip high-performance Hysteretic
PWM controller. With its integrated SmartDriverTM, it pow-
ers advanced graphics and core processors. It provides
sleep mode and boot voltage support. Automatic "power-
save" is present to prevent negative current flow in the
low-side FET during light loading conditions saving even
more power. The high side driver initially turns on with a
weak drive to reduce ringing, EMI, and capacitive turn-on
of the low side.

A 6-bit DAC, accurate to 0.85%, sets the output voltage
reference, and implements the 0.700V to 1.708V range
required by the processor. The hysteretic converter uses a
comparator without an error amplifier, and therefore pro-
vides the fastest possible transient response, while avoid-
ing the stability issues inherent to classical PWM control-
lers. The DAC is externally slew rate limited to minimize
transient currents and audible noise.

The SC453 operates from 5VDC and also features soft-
start, an open-drain PWRGD signal with power good blank-
ing, and an enable input. Programmable current limiting
shuts down the SC453 after 32 current limit pulses.

Low Power Notebook and Laptop Computers

Embedded Applications

Typical Application Circuit

Applications

Features

PowerStep IVTM and Smart DriverTM are trademarks
of Semtech Corporation.

SC453 Single Phase

Power Supply

Smart

Driver

PWM

Controller

VID Logic
and DAC

VID (5:0)

VIN

CCA

VCORE

0.700V-1.708V

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SC453

332

30p

DNP

IRF

7
8

2
1

330

u
F

7
8

2
1

330

u
F

.
2

+
V

_
D

E
L

OOT

PG_

DRN

_
I
N

SLP

PG#

BST

T
_

DRN

BST

BOOT

PG#

CCA

PGN

SC453

SLP

H
CS

.
9
K

3
1

1
4

0
L

330

p
F

10u

8
3

15n

7
8

3
2

.
5
K

330

0uF

0
5

3
0

0uF

Reference Design

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SC453

Absolute Maximum Ratings

Exceeding the specifi cations below may result in permanent damage to the device or device malfunction. Operation outside of the parameters specifi ed in the
Electrical Characteristics section is not implied.

Unless otherwise specifi ed: V

= 15V, V

CCA

= 5V, and V5 = 5V.

(1) Calculated from package in still air, mounted to 3" x 4.5", 4 layer FR4 PCB.
(2) Tested according to JEDEC standard JESD22-A114-B.

Parameter

Symbol

Conditions

Min

Max

Units

Supply Voltages

CCA,

-0.3

Input and Output Voltages

VSLPV, V SLP, V VID [0.5], V DAC, V REFIN,

V CMP, V HYS, V CORE, V CL, V CLRF, V PG#,

V BOOTV, V SS, V GND, V BG, V CLSET

-0.3

CCA

+0.3

BST to PGND

Static

-0.3

BST to PGND

Transicent < 100ns

BST to DRN

-0.3

DRN to PGND

Static

-2

DRN to PGND

Transient < 100ns

-5

STG

-2

BST
+0.3

PGND to AGND

-0.3

0.3

Thermal Resistance
Junction to Ambient

TSSOP-28

°C/W

Thermal Resistance
Junction to Case

TSSOP-28

°C/W

Lead Temperature
(Soldering) 10s

LEAD

TSSOP-28

TBD

°C

Peak IR Refl ow
Temperature 10 - 40s

PKG

TSSOP-28

260

°C

Parameter

Symbol

Conditions

Min

Typ

Max

Units

Supply (V

, V

CCA

, V

)

Supply

Voltage Range

3.0

Supply

Voltage Range

4.3

5.0

6.0

CCA

Voltage Range

CCA

4.5

5.0

6.0

CCA

Quiescent Current

CCQ

EN is low

EN is high in UVLO

400

Absolute Maximum Ratings

Electrical Characteristics

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SC453

Parameter

Symbol

Conditions

Min

Typ

Max

Units

CCA

Operating Current

Under-Voltage Lockout Circuits (V

CCA

, V

)

Threshold (V

CCA

falling)

HCCA

3.47

3.70

3.93

CCA

Hysteresis

HYST CCA

190

Threshold (V

falling)

HV5

3.85

4.00

4.25

Hysteresis

HYST V5

210

Fixed Over-Voltage Protection (CORE)

Threshold
(CORE Rising)

TH CORE

FIXED

1.95

2.00

2.05

Enable Input (EN)

Input High

iH (EN)

Input Low

(EN)

0.8

CORE

Power Good Generator (PG_DEL, PG#)

Core Input Threshold

TH CORE

DAC

= 0.6 - 1.75V

Note: during
UVLO, the
output level of
this signal is
undefi ned

Upper Threshold

1.1*

DAC

1.15*

DAC

Lower Threshold

0.86*

DAC

0.9*

DAC

Hysteresis

PG# Output Voltage

PG#

Pulled up with
external 680
resistor to
V

PULL-UP

CORE

= V

DAC

0.4

Either V

CORE

< 0.88*V

DAC

or, V

CORE

> 1.12*V

DAC

0.95*

PULL-UP

EN is low or EN is high
but UVLO condition

0.95*

PULL-UP

PG_DEL
Output Voltage

PG_DEL

CORE

= V

DAC

pulled-up with external

680 resistor to V

PULL-UP

1.2V

0.95*

PULL-UP

Either V

CORE

< 0.88*V

DAC

or, V

CORE

> 1.12*V

DAC

0.4

EN is low or EN is high
but UVLO condition

0.8

PG_DEL Delay
(at start-up)

Measured from PG# assertion

1007

Clocks

Electrical Characteristics (Cont.)

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SC453

Parameter

Symbol

Conditions

Min

Typ

Max

Units

Soft-Start & DAC Slew (SS)

Soft-Start/DAC
Slew Current

Note:
SS cap is not discharged
until EN goes low or
UVLO cuts in. To enable
the converter, SS has to
drop below V

SS_EN

Discharge (sink) Current

Soft-Start transition 0 < T

< 85°C,

- 40 < T

< 85° C

7.5

10.5

Sleep Exit, 0 < T

< 85°C

204

256

310

Sleep Exit, -40 < T

< 85°C

180

240

320

VID Transition, 0 < T

< 85°C

102

128

155

VID Transition, -40 < T

< 85°C

120

160

Soft-Start
Enable Threshold

SS_EN

100

DAC (VID [5:0])

VID Input Threshold

iH_VID

0.55

iL_VID

0.45

DAC Output
Voltage Accuracy

DAC_ERR

0° < T

< 85°C, VID [5:0] = 000000

"111111(1.708V" 0.812V)

-0.85

+0.85

-25°C < T

< 85°C, VID [5:0] = 000000

"111111 (1.708V" 0.700V)

-2.0

+2.0

Boot Voltage (BOOTV)

Input Voltage Offset

BOOTV

DAC

BOOTV = 1.2V

|±3|

BOOT Delay Time

(1)

TBOOT

Sleep (SLP, SLPV)

Input Voltage Offset

SLPV

-V

DAC

SLPV = 0.8V

|±3|

SLP Logic Threshold

iH_SLP

iL_SLP

0.8

CORE Comparator (CMP, REFIN, HYS)

Input Bias Current

REFIN

= 1.3V

|±2|

Input Voltage Offset

CMP

REFIN

|±1.5|

|±3|

Electrical Characteristics (Cont.)

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SC453

Parameter

Symbol

Conditions

Min

Typ

Max

Units

CORE Comparator (CMP, REFIN, HYS) (Cont.)

Hysteresis Setting
Current SLP = low

CMP

HYS

= 17K

CMP

< V

REFIN

-110

-100

-90

CMP

> V

REFIN

100

110

HYS

= 170K

CMP

< V

REFIN

-7

-10

-13

CMP

> V

REFIN

Hysteresis Setting
Current SLP = high

SLP_

CMP

HYS

= 17K

CMP

< V

REFIN

-83

-73

-63

CMP

> V

REFIN

Current Limit Comparator (CL, CLRF, HYS)

Input Bias Current

CL1, 2

= 1.3V

|±2|

Input Voltage Offset

CLRF

|±3|

|±5|

Current Limit Setting
Current SLP = low

CLRF

HYS

= 17K

< V

CLRF

150

200

250

> V

CLRF

250

300

350

HYS

= 170K

< V

CLRF

> V

CLRF

Current Limit Setting
Current SLP = high

SLP_CLRF

HYS

= 17K

< V

CLRF

120

150

180

> V

CLRF

195

230

265

Zero-Crossing (Powersave) Comparators (CL, CORE)

Offset

CORE

|±5|

High Side Driver (TG)

Peak Output Current

(1)

pkh

1.5

Output Resistance

SRC_TG

I = 100mA,

BST

-V

DRN

= 5V

DRN

< 1V

4.2

DRN

> 1V

SINK_TG

I = 100mA, V

BST

-V

DRN

= 5V

0.7

1.4

Rise Time

(1)

= 3nF, V

BST

-V

DRN

= 5V

Fall Time

(1)

= 3nF, V

BST

-V

DRN

= 5V

Electrical Characteristics (Cont.)

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Parameter

Symbol

Conditions

Min

Typ

Max

Units

High Side Driver (Cont.)

Propagation Delay TG
Going High

(1)

tpdh

CMP crossing REFIN to 10%
point of TG, C

= 3nF,

BG = 0V

Propagation Delay TG
Going Low

(1)

tpdl

CMP crossing REFIN to 90%

point of TG, C

= 3nF

Shoot-thru Protection
Delay Time

(1)

tspd

Low Side Driver (BG)

Peak Output Current

(1)

pkl

Output Resistance

SRC_BG

I = 100mA, V5 = 5V

1.0

2.6

SINK_BG

0.5

1.2

Rise Time

(1)

= 3nF, V5 = 5V

Fall Time

(1)

= 3nF, V = 5V

Propagation Delay TG
Going High

(1)

tpdh

CMP crossing REFIN to 10%
point of BG, C

= 3nF, DRN = 0V

Propagation Delay TG
Going Low

(1)

tpdl

CMP crossing REFIN to 90%
point of TG, C

= 3nF, DRN = 0V

Notes:
1) Guaranteed by design.

Electrical Characteristics (Cont.)

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SC453

Device

Package

Temp Range(T

)

SC453TSTRT

TSSOP-28

-40°C to + 125°C

Notes:

1. Only available in tape and reel packaging. A reel contains
2500 devices.
2. Lead-free package compliant with J-STD-020B. Qualifi ed
to support maximum IR refl ow temperature of 260°C for 30
seconds.
3. This device is ESD sensitive. Use of standard ESD handling
precautions is required.
4. All parameters subject to change without notice.
5. Lead-free product. This product is fully WEEE and RoHS
compliant.

Pin#

Pin Name

Pin Function

DRN

This pin connects to the junction of the switching and synchronous MOSFETs.

Output gate drive for the switching (high-side) MOSFET.

BST

Bootstrap pin. A capacitor is connected between BST and DRN pins to develop
the fl oating bootstrap voltage for the high-side MOSFET.

SLP

Sleep logic input signal.

SLPV

Connect this pin to V

CCA

to select "VID Sleep Mode". Otherwise, "SLPV Sleep Mode"

is selected and the voltage on this pin sets the DAC output during sleep.

BOOTV

The voltage on this pin sets the BOOT-Up voltage.

PG#

Start clock indicator - open drain output. Active low.

HYS

Core Comparator Hysteresis. Connect to ground thru an external resistor called R

HYS

Hysteresis current is established by an internal V

REF

voltage, 1.7V, divided by R

HYS

VID5

VID most signifi cant bit main controller voltage programming DAC input.

VID4

VID input.

Pin Confi guration

Ordering Information

Pin Descriptions

DRN

TOP VIEW

(28 Pin TSSOP)

PGND

BST

SLP

SLPV

CMP

BOOTV

CLRF

PG#

VCCA

HYS

REFIN

VID5

GND

VID4

DAC

VID3

CORE

VID2

PG_DEL

VID1

VID0

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Pin Confi guration

Pin Descriptions (Cont.)

Pin#

Pin Name

Pin Function

VID3

VID input.

VID2

VID input.

VID1

VID input.

VID0

VID least signifi cant bit main controller voltage programming DAC input.

Soft-start. An external cap defi nes the soft-start ramp.

PG_DEL

Delayed power good - open drain output. When the Main Converter Output approaches
and stays within ± 14% of the VID_DAC setting, and the t

CPU_PWRGD

period has terminated.

This signal is pulled high by an external resistor.

CORE

Main CORE converter output feedback to the power good generator. A small RC fi lter
should be used to fi lter out any HF component to prevent faulty trip condition.

DAC

Main controller digital-to-analog output.

GND

Analog ground.

REFIN

Core Comparator reference input pin. Connect to DAC.

VCCA

5V supply for precision analog circuitry.

CLRF

Current limit reference input pin

CMP

Core Comparator input pin.

Current limit input pin.

Enable - active high. This is capable of accepting a 5.0V signal level.

PGND

Power ground. Connect to the synchronous FET power ground.

Output drive for the synchronous (low-side) FET.

5VDC supply for the driver. A capacitor should be connected from V5 to GND.

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SC453

Applications Information (Cont.)

SUPPLY, BIAS, UVLO, POWER GOOD GENERATOR

Supply
The chip is optimized to operate from a 5V ± 5% rail but
also designed to work up to 6V maximum supply voltage.

Under-Voltage Lock-Out Circuit
The Under-Voltage Lock-Out Circuit consists of compara-
tors which monitor the VCCA and V5 voltage levels. The
SC453 is in UVLO mode while either supply has not
ramped above the upper threshold or has dropped below
the lower threshold. During UVLO, the external FETs are
held off, tri-stating the output (DRN).

Over-Voltage Protection
If the CORE voltage is greater than +14% of the DAC (i.e.,
out of the power good window), the SC453 will latch off
and hold the low-side driver on permanently. Either the
power or EN must be recycled to clear the latch. The latch
is disabled during soft-start and VID/Sleep transitions.
For safety, the latch is enabled if the CORE voltage ex-
ceeds 2V even during VID/Sleep transitions.

Thermal Shutdown
The device will be disabled and latched off when the inter-
nal junction temperature reaches approximately 160°C.
Either the power or EN must be recycled to clear the
latch.

Band Gap Reference
A ± 0.85% precision Band Gap reference acts as the in-
ternal reference voltage standard of the chip, which all
critical biasing voltages and currents are derived from.

All

references to VREF in the equations to follow will assume
VREF = 1.7V.

Precision DAC
This 6-bit digital-to-analog converter (DAC) serves as the
programmable reference source of the Core Comparator.
Programming is accomplished by logic voltage levels ap-
plied to the DAC inputs. The VID code vs. the DAC output
is shown in the following table. The accuracy of the VID
/DAC is maintained on the same level as the Band Gap
reference.

VID

DAC

VID

DAC

1.708

1.196

1.692

1.180

1.676

1.164

1.660

1.148

1.644

1.132

1.628

1.116

1.612

1.100

1.596

1.084

1.580

1.068

1.564

1.052

1.548

1.036

1.532

1.020

1.516

1.004

1.500

0.988

1.484

0.972

1.468

0.956

1.452

0.940

1.436

0.924

1.420

0.908

1.404

0.892

1.388

0.876

1.372

0.860

1.356

0.844

1.340

0.828

1.324

0.812

1.308

0.796

1.292

0.780

1.276

0.764

1.260

0.748

1.244

0.732

1.228

0.716

1.212

0.700

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SC453

DAC Slew Control
The output of the DAC will slew at a rate defi ned by the
current in the SS pin and the capacitor applied externally
to the SS pin. The slew rate (charge current) applied de-
pends on which mode (soft-start, VID or sleep transition)
is in effect. The SS capacitor together with the DAC ca-
pacitor will determine the stability of the DAC, a 1nF ca-
pacitor is recommended for the DAC pin.

Blanking During VID Changes
On any VID change or Sleep change, the PG# and PG_
DEL signals are blanked for 62 switching cycles to prevent
glitching during the transition.

Sleep Function
In sleep mode, the DAC output is set by the voltage on
the SLPV pin when the SLP pin is held high. In "VID Sleep"
mode, the DAC output is set by the VID bits when SLP is
held high. During sleep, the hysteresis and current limit
hysteresis currents are reduced to 70% of their nominal
values.

SLPV/VID Sleep Mode
By default, the controller is in "SLPV controlled Sleep"
mode. In this mode, the voltage applied to the SLPV pin
appears at the DAC output when SLP is asserted.

By holding the SLPV pin at VCCA during start-up, "VID con-
trolled sleep" mode is engaged. In this mode, the DAC out-
put continues to be set by the VID inputs even when SLP
is asserted.

CORE CONVERTER CONTROLLER

Core Comparator
This is an ultra-fast hysteretic comparator with a typical
propagation delay of about 20ns at a 20mV overdrive.
Hysteresis is generated by the current set at the HYS pin
impressed upon an external resistor connected to the
CMP pin.

Current Limit Comparator

The Current Limit Comparator monitors the core converter
output current and turns off the high side FETs when the
current exceeds the upper current limit threshold, VHCL
and is re-enabled only if the phase current drops below
the lower current limit threshold, VLCL.

The current is

sensed by monitoring the voltage drop across the current
sense resistor, RCS connected in series with the core con-
verter inductor. VHCL and VLCL are fi xed by the current
set at the HYS pin impressed upon an external resistor
connected to the CLRF pin.

Current Limit Latch
If the CORE voltage goes lower than 14% below the VID
(i.e., out of the power good window), then sustained cur-
rent limiting (32 current limit pulses) will cause the part
to permanently latch off. The latch is inhibited during soft-
start.

Core Converter Soft-Start Timer
This block controls the start-up ramp time of the CORE
voltage up to the boot voltage. The primary purpose is to
reduce the initial in-rush current on the core input voltage
(battery) rail.

Cycle-by-Cycle Power-Save
A zero crossing comparator detects when the currents
through the external sense resistor reduces to zero. When
the current in the external sense resistor reaches zero,
the bottom FET is latched off. The latch is reset when the
controller decides to switch on the top FET. This prevents
excessive switching at light loads and hence saves switch-
ing power losses.

Applications Information (Cont.)

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SC453

Applications Information (Cont.)

PG# Output
This is an open-drain output and should be pulled up ex-
ternally. This signal is asserted (pulled low) by the SC453
whenever the core voltage is within ±14% of the VID
programmed value. If the chip is disabled or enabled in
UVLO, then PG# is de-asserted. During start-up PG# re-
mains de-asserted until the core voltage has reached the
defi ned boot voltage and remains there for the BOOT pe-
riod (10S minimum). This signal is forced low (asserted)
during VID and sleep transitions.

PG_DEL Output
This signal is delayed a minimum of 3mS from fi rst as-
sertion of the PG# signal. This is an open drain output

and should be pulled up externally. This signal is asserted
(open drain) by the SC453 whenever the core is within
±14% of the VID programmed value. If the chip is disabled
or enabled in UVLO, then PG_DEL is de-asserted. The sig-
nal is forced high (open drain) during VID and sleep transi-
tions.

Start-Up and Sequencing
On start-up, V

CORE

ramps to the boot voltage set by the

BOOTV pin irrespective of the status of the VID pins. After
a minimum of 10s, PG# asserts, and V

CORE

responds to

the VID inputs. The controller will then count 1007 switch-
ing cycles before asserting PG_DEL.

Summary of Fault Conditions

Driver Timing Diagram

CMP

CMPRF

tpdl

tpdh tr

tpdl tf tspd

tpdh

(4)

Note (4): subtract a typical value of 17ns for the core comparator delay since this parameter is specifi ed from a CMP edge.

Protection Mode

Latched?

When Active

Driver Status

SS Pin Status

Supply UVLO (VCCA, V5)

Always

All low

Low

32 Cycle Current Limit

Yes

SS has terminated and PGDEL is low

TG low

Sawtooth

114% V

CORE

OVP

Yes

SS has terminated and PGDEL is low

BG high

High

2.0V

CORE

OVP

Yes

Always

BG high

High

Thermal Shutdown

Yes

Always

BG, TG low

High

REFIN

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Applications Information (Cont.)

DESIGN PROCEDURE

Step 1: Defi ne Constants

Maximum input voltage

Minimum input voltage

Maximum load current,

highest

output

voltage

Leakage current, highest

output

voltage

The highest V

CORE

voltage

The lowest V

CORE

voltage

SC453 Internal reference voltage

Output capacitance per cap

ESR per cap

Current sense resistor

Parasitic resistance from the

current sense resistor to the

processor

Voltage droop allowed for a low

current to high current transient

Voltage rise allowed for a high

current to low current transient

Desired maximum output ripple

Step 2: Output Inductor and Capacitor Selection
The SC453 has "passive" droop. The voltage at full load is
less than the DAC voltage by the voltage drop across the
current sense resistor and any PCB copper losses from
the sense resistor to the processor socket. The steady-
state voltage at full load is:

MAX_FL

MAX_NL

(

)

MAX_FL

1.182 V

Output capacitance and ESR values are a function of
transient requirements and output inductor value. Figure
1 illustrates the response of a hysteretic converter to a
positive transient. In a hysteretic converter with passive
droop, like the SC453, two conditions determine if you
meet the positive transient requirements.

ESR

POS_TRANS

MAX_FL

LKGMAX

(

)

NEG_TRANS

deltaV C

OUT

( )

Figure 1 - Hysteretic Converter Response to a

Positive Transient

The fi rst condition is easy to see; if the ESR is too high, the
transient response will fail.

INMAX

20V

INMIN

MAX_FL

20A

LKGMAX

MAX_NL

1.212V

MIN_NL

0.956 V

REF

1.7V

OUT

330

ESR

0.5m

POS_TRANS

50mV

NEG_TRANS

50mV

RIPPLE

20m V

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In the second condition, because the hysteretic converter
responds in < 100ns, the capacitor does not droop very
far before the inductor current starts ramping up. (This is
not true of control schemes where time constants in the
error amplifi er cause delays.) Once the inductor current
starts to rise, the increasing V of the capacitor is offset
by reduced V from the ESR, so V is constant. If the V
due to the charge taken from the capacitor before the in-
ductor current reaches the load current (note the shaded
area on the graph) is less than VPOS_TRANS, then the
transient response passes.

Since the highest output voltage has the most severe re-
quirements, any other modes are satisfi ed by a design op-
timized for the highest output voltage.

For the second condition, we need to know the inductor
value, which is a function of the highest desired switching
frequency. The maximum frequency occurs at the high-
est input voltage. As a reasonable compromise between
effi ciency and component size, a maximum switching fre-
quency of 350kHz is desired.

Based on the following four factors: 1) minimum induc-
tance requirement; 2) device availability at the time we
designed the evaluation board; 3) low DCR ; 4) height and
package size consideration. Keep in mind, the choice you
make should be based upon the requirement of the con-
verter design, including minimum inductance, minimum
saturation current, effi ciency, foot area, maximum allow-
able height, and of course, device availability. In the cur-
rent demo board design,

G.

This value of inductance is required up to maximum load.
Inductors with a "swinging choke" characteristic, where
the zero current value of inductance is much less than the
full load current inductance can be used, as long as the
above restriction is met. Then, the worst-case (low input
voltage) response time (the time for the current to reach
the new transient value) is:

Add ~100ns for the propagation delay from a change at
the output to the MOSFET switch turning on in reaction.
Since the shaded area is triangular, the total charge taken
out of the capacitor = (dI / dt) / 2. Q = C / dV = (dI / dt) /
2, therefore;

MINP

MAX_FL

LKGMAX

(

)

1 10

sec

(

)

POS_TRANS

MINP

4.278

This condition applies only to the positive transient.

MIN

INMAX

MAX_NL

(

)

ESR

MAX

(

)

RIPPLE

ESR

MAX

ESR

MAX

MIN

5.422

MIN

MAX_NL

INMAX

Applications Information (Cont.)

ESR

MAX

POS_TRANS

MAX_FL

LKGMAX

(

)

ESR

MAX

3.333

0.60

350K Hz

MAX_FL

LKGMAX

(

)

INMIN

MAX_NL

dT 1.326

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POWER MANAGEMENT

SC453

LOAD RELEASE
The worst-case for the transient load release to happen is
when the hysteresis has just reached the maximum, (i.e.,
the high-side switch has just turned of); at this time the
inductor has reached its peak current.

RIPPLE

INMAX

MAX_FL

(

)

MIN

MAX_FL

RIPPLE

Load is stepping from high to low.

Immediately after the load steps down from I

MAX

to I

MIN

, the

high side FET is turned off, and the bottom FET is turned
on after the dead time. We assume for the worst-case
condition, at t = 0, the output inductor is sitting at its max-
imum; after t = 0, the inductor discharges at a rate equal

to V

/ L.

(without the consideration of the secondary or-

der effect, such as, Rds_on drop, current sense resistor
and copper losses). The energy released from the output
inductor during load step-down,

charges

the output ca-

pacitors and is dissipated through the following means:
Rds_on, Rcs, Rcu, Rcu_rt, ESR of the output capacitors
and load.

Applications Information (Cont.)

Since the output inductor is discharging at a fi xed rate,
there are two terms contributing to the increase of the
voltage on the output capacitors: 1) is due to the ESR of
the output capacitor; 2) is due to the added charge con-
tributed by the inductor current.

ESR

t N

CAP

(

)

CAP

( )

ESR

CAP

t N

CAP

(

)

CAP

( ) t

OUT

CAP

TOTAL

t N

CAP

(

)

ESR

t N

CAP

(

)

CAP

t N

CAP

(

)

The chart above shows the system response for the ca-
pacitors defi ned in Step 1 and the chart to follow shows
the details of the response for the chosen number of out-
put capactors.

ESR_eq

MAX

MIN

Cout_eq

Rcu_rt

Rds_ON

R_LOAD

0 10n s

( )

MAX_FL

CAP

( )

LKGMAX

RIPPLE

6.01 A

23.005 A

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POWER

MANAGEMENT

SC453

Applications Information (Cont.)

Step 3: Setting RHYS
The next step is to calculate R

HYS

. Since the SC453 is a

hysteretic controller, it regulates the amount of output
ripple according to a hysteresis value set by R

HYS

. The de-

signer must therefore decide upon the amount of desired
output ripple, and then set R

HYS

accordingly.

The hysteresis controls the amount of ripple at the point
of regulation, which is the point between the inductor and
the current sense resistor. The amount of ripple at the
output is defi ned by the current sense resistor and the
output cap, ESR. This factor is taken into account in the
equation shown below relating V

RIPPLE

to V

HYS

To achieve tight accuracy, it is recommended that the out-
put ripple be set to 20mV peak-to-peak.

ESR

CAP

ESR 1.5

RIPPLE

0.02 V

HYS

RIPPLE

ESR

(

)

ESR

HYS

0.033 V

HYS

is created by a current source, I

HYS

, through R9 (see

the diagram below). The current source value is con-
trolled via R

HYS

. For simplicity it is easier to select a value

for R7 (the resistor in series with the CMP pin) fi rst, and
then calculate R

HYS

, as follows:

HYS

2 V

REF

HYS

102.0 K

In the SC453 application circuit, R

HYS

consists of three re-

sistors (R3, R4 and R5). These resistors also form the
dividers for BOOTV and SLPV. Note also that depending
on circuit layout and parasitics, R

HYS

may have to be ad-

justed slightly to obtain optimum performance. (We will
come back to calculate the above resistors after we set
the PBOOT and Deeper Sleep voltages). To increase hys-
teresis without having to change the divider resistors, a
fourth resistor (R14), can be added. Additional hysteresis
is needed when inductances in the current sense paths
cause additional signal that add to the resistive signal,
limiting the accuracy of the calculations.

R14

HYS

BOOTV

SLPV

SC453

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POWER MANAGEMENT

SC453

Step 4: BOOTV Design
The boot-up voltage for V

CORE

is set at 1.2V. For the SC453

typical application circuit, R3, R4, and R5 form a voltage
divider off V

REF

and are used to set the boot voltage. For

simplicity, we defi ne R

BOOT

: = R3 + R4.

BOOT

1.2V

HYS

BOOT

REF

BOOT

Step 5: Sleep Voltage Design
The sleep voltage is set at 0.750V nominally using the R3
- R4 - R5 divider.

SLP

0.750V

R3, R4 and R5 are calculated using a matrix to solve the
simultaneous equations. R14 is set at 1M as a place-
holder:

1000 K

SLP

REF

SLP

BOOT

REF

BOOT

SLP

REF

SLP

Applications Information (Cont.)

From the standard 1% resistor value table, we choose
the following values according to the calculation results:

R5 = 33.2K.
R4 = 30.1K
R3 = 49.9K

Step 6: Current Limit Calculation
Setting the threshold for current limit is a relatively
straightforward process. To do this we must calculate the
peak current based on the maximum DC value plus the
worst-case ripple current. The following calculations apply
for a single phase. Worst-case ripple occurs at the high-
est input voltage. Since ripple is also inversely proportion-
al to inductance, it is recommended that the minimum
inductance value be used based on the manufacturer's
specifi ed tolerance:

LOW

20%

(

)

LOW

4.8

RIPPLE_MAX

INMAX

MAX_NL

(

)

MIN

LOW

HYS

soln

lsolve M

( )

soln

5.011

3.007

3.341

3.007

0 1 0

(

) soln

3.341

0 0 1

(

) soln

1 0 0

(

) soln

5.011

SLP

(

)

REF

SLP

RIPPLE_MAX

6.777 A

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POWER

MANAGEMENT

SC453

Applications Information (Cont.)

To calculate the maximum DC value of current we must
add the maximum DC current and the maximum ripple
value to obtain peak current:

It is recommended that the current limit be set at 120%
of the peak value to allow for inductor current overshoot
during load transients:

The Current Limit Comparator internal to the SC453 moni-
tors the output current and turns the high side switch off
when the current exceeds the upper current limit thresh-
old, I

CLMAX

and re-enables only if the load current drops be-

low the lower current limit threshold, I

CLMIN

. The current is

sensed by monitoring the voltage drop across the current
sense resistor R

Current limiting will cycle from I

CLMAX

to I

CLMIN

for 32 switch-

ing cycles to allow for short term transients, then the con-
verter is latched off. I

CLMAX

and I

CLMIN

are set according to

the following equations:

U.

We set the current limit at I

CLIM

= ICLMAX, and then solve

for R

, which is R6 in the typical applications circuit. For

balance, R8, in series with the CLRF pin is kept the same
value as R6.

CLIM

HYS

2.5 V

REF

673.59

681

Step 7: Small Capacitors/Resistor Selection
Several small capacitors are required for signal fi ltering.
Use SMT ceramic capacitors with an X7R or better tem-
perature coeffi cient. COG is preferred.

C11, which fi lters the output voltage feedback, is sized to
provide fi ltering beyond the 5th harmonic of the funda-
mental.

C11

9.095

In the evaluation board design, we use 100pF, 603, X7R
ceramic caps for C11. The DAC output requires a 1nF,
X7R or COG capacitor (C23) for high frequency noise fi l-
tering. The values for C12 and C13 are calculated in a
similar manner, though they are returned to the CORE pin
because that is the reference point for the current limit
comparator.

1.335

PEAK

23.389 A

PEAK

MAX_FL

RIPPLE_MAX

CLIM

120% I

PEAK

CLIM

28.066 A

CLMAX

3 V

REF

HYS

CLMIN

2 V

REF

HYS

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POWER MANAGEMENT

SC453

Based on the above calculations, we choose N = 4 for the
input capacitor.

Step 9: OVP
No calculations are necessary for Over-Voltage Protection.
If V

CORE

is greater than +14% of the DAC (i.e., out of the

power good window), the SC453 will latch off and hold the
low-side driver on permanently (for each phase). Either
the power or EN must be recycled to clear the latch. The
latch is disabled during soft-start and VID/DeeperSleep
transitions. The latch is enabled if V

CORE

exceeds 2V even

during VID/DeeperSleep transitions to ensure that the
processor maximum is not exceeded.

The table on Page

13 is a summary of fault conditions using SC453.

Step 10: Soft-Start/DAC Slew Control
The soft-start cap C21 in the SC453 design serves three
conditions: 1) to defi ne the soft-start ramp; 2) to defi ne
the DAC slew rate during sleep and VID transitions (dur-
ing VID transitions the SS current is

nominally

+/- 120A.

During sleep transitions the SS current increases to +/-
240A); 3) during start-up, the SS current is normally +/-
6.5A.

We will be doing three soft-start exercises based on the
above three conditions for SC453 application:

Step 8: Calculate Input RMS Current
In order to calculate the worst-case input RMS current, we
need to assume the effi ciency at V

IN_MIN

and full load. From

the measurement result, we are safe to assume 80%,
(this number is very conservative, actual effi ciency should
be much higher). The actual converter effi ciency depends
on component selection, layout, airfl ow, etc.

OUT

MAX_FL

OUT

23.64 W

OUT

85%

IN_DC

INMIN

MAX_FL

INMIN

IN_DC

3.476 A

RMS

MAX_FL

(

)

IN_DC

(

)

RMS

7.116 A

I_RMS

10F@25V, MLCC cap from Panasonic is rated 2A RMS.

I_NUM

ceil

RMS

I_RMS

I_NUM

The calculation indicates four of these MLCC caps satisfy
the worst-case RMS current requirement.

Input Capacitance Calculation:
(based on ripple voltage)
dVin is the allowable input ripple voltage contributed by
the amount of input capacitance. For this exercise, we
use 250mV as the allowable input ripple voltage. The
maximum value occurs at D = 0.5

Applications Information (Cont.)

dVin

250mV

MAX

0.5

IN_MIN

PEAK

MAX

dVin

IN_MIN

3.341

IN_MIN_RIPPLE

ceil

IN_MIN

IN_MIN_RIPPLE

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POWER

MANAGEMENT

SC453

Applications Information (Cont.)

1. Start-Up:

6.5

3 m s

dacSU

MAX_NL

SS_max_startup

dacSU

SS_max_startup

1.609

2. VID Change:

SSV

120

100

dacV

MAX_NL

MIN_NL

SS_max_VID

SSV

dacV

SS_max_VID

4.687

3. Sleep Entry/Exit:

SSS

240

dacS

MAX_NL

SLP

SS_max_drs

SSS

dacS

SS_max_drs

1.714

Exercise #1 predicts the max capacitance allowed. In
order to allow tolerance, we choose C22 = 15nF.

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POWER MANAGEMENT

SC453

bxN

.378

9.60

.386

9.70

9.80

PLANE

bbb

C A-B D

ccc C

DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS

OR GATE BURRS.

DATUMS AND TO BE DETERMINED AT DATUM PLANE

CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).

-B-

NOTES:

-A-

-H-

SIDE VIEW

e/2

(.039)

.008

.004

.024

0°

(L1)

GAGE

PLANE

SEE DETAIL

DETAIL

0.25

.026 BSC

.252 BSC

.004

.169

.173

.007

0.10

0.65 BSC

6.40 BSC

4.40

.177

4.30

.012

0.19

4.50

0.30

.382

2X N/2 TIPS

SEATING

aaa C

E/2

INDICATOR

PIN 1

.018

.003

.031

.002

8°

0°

0.20

0.10

8°

0.45

0.09

0.80

0.05

.030

.007

.047

.042

.006

0.60

(1.0)

0.75

0.20

1.20

1.05

0.15

REFERENCE JEDEC STD MO-153, VARIATION AE.

INCHES

bbb

aaa

ccc

DIM

A1
A2

MIN

MAX

MILLIMETERS

DIMENSIONS

MIN

MAX

NOM

Marking Information

Outline Drawing - TSSOP-28

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