1
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Revision 2 / January 30, 2003
TEST AND MEASUREMENT PRODUCTS
SK44XX Family Functional Block Diagram
SK44XX Family
Quad Buffer/Receiver
1
0
OUT3*
OUT3
D
D*
Q
Q*
1
0
OUT2*
OUT2
D
D*
Q
Q*
1
0
OUT1*
OUT1
D
D*
Q
Q*
1
0
OUT0*
OUT0
D
D*
Q
Q*
IN0
IN0*
IN1
IN1*
IN2
IN2*
IN3
IN3*
CLK
CLK*
SEL*
SEL
EN
EN*
Revision 2 / January 30, 2003
2
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TEST AND MEASUREMENT PRODUCTS
SK44XX Family Product Selection Guide
Logic Family
Logic / Translation Family
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SK44XX Family
Quad Buffer/Receiver
Quad Buffer/Receiver
3 GHz
Synch / Asynch Operation
3
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Revision 2 / January 30, 2003
TEST AND MEASUREMENT PRODUCTS
SK44XX Family Package Information
5mm x 5mm TQFP
8
D1, E1
2
4
3
D, E
See
Figure 3.
b
e
A
A1
10
b
SEATING
PLANE
A2
Side View
Top View
SK44XX Family
Quad Buffer/Receiver
Revision 2 / January 30, 2003
4
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TEST AND MEASUREMENT PRODUCTS
L
11
(L1)
R2
GAGE PLANE
25
R1
01
02
2
S
03
00
9
7
9
b
c
9
b1
9
c1
WITH
PLATING
e / 2
b
See Detail in
Figure 2
1. All dimensions and tolerancing conforms to ANSI
Y14.5M-1982.
2. The top package body size may be smaller than the
bottom package body size by as much as 0.15 mm.
3. To be determined at seating plane.
4. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is 0.25 mm per side. D1 and E1
are maximum plastic body size dimensions including
mold mismatch.
5. Details of Pin 1 identifier optional, but must be located
within the zone indicated.
6. All dimensions are in millimeters.
7. Dimension b does not include Dambar protrusion.
Allowable Dambar protrusion shall not cause the lead
width to exceed the maximum b dimension by more
than 0.08 mm. Dambar cannot be located on the lower
radius or the foot. Minimum space between protrusion
and an adjacent lead is 0.07 mm for 0.4 mm and 0.5
mm pitch packages.
8. Exact shape of each corner is optional.
9. These dimensions apply to the flat section of the lead
between 0.10 mm and 0.25 mm from the lead tip.
10.A1 is defined as the distance from the seating plane to
the lowest point of the package body.
SK44XX Family Package Information (continued)
5mm x 5mm TQFP
Figure 2.
Figure 3.
SK44XX Family
Quad Buffer/Receiver
Figure 1.
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JEDEC Variation
All Dimensions in Millimeters
5
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Revision 2 / January 30, 2003
TEST AND MEASUREMENT PRODUCTS
SK44XX Family
Quad Buffer/Receiver
* Maximum Ratings are those values beyond which damage to the device may occur.
Note:
1. Device is ESD sensitive and requires protective handling.
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Absolute Maximum Ratings*
Revision 2 / January 30, 2003
6
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TEST AND MEASUREMENT PRODUCTS
Features
The SK4400 is an extremely fast, stable and accurate
low skew quad buffer or cable driver / receiver. It can
asychronously pass four distinct signals, or it can
resynchronize them to a common clock. In addition, all
four outputs may be asynchronously enabled or
disabled. All of the D flip-flops are triggered on the
rising edge of the CLK input.
The SK4400 uses standard open emitter ECL outputs
optimized for:
Standard, general purpose ECL applications
Multiple destinations (daisy chain).
Functional Block Diagram
Quad Buffer/Receiver
3 GHz Fmax
3.3V / 5.2V Compatible
Available in 32 lead, 5mm X5mm, TQFP
Package
SK4400
Quad Buffer/Receiver
1
0
OUT3*
OUT3
D
D*
Q
Q*
1
0
OUT2*
OUT2
D
D*
Q
Q*
1
0
OUT1*
OUT1
D
D*
Q
Q*
1
0
OUT0*
OUT0
D
D*
Q
Q*
IN0
IN0*
IN1
IN1*
IN2
IN2*
IN3
IN3*
CLK
CLK*
SEL*
SEL
EN
EN*
Pin Description
Description
32 pin, 5 mm X 5 mm
TQFP Package
Package Information
V
CC
OUT1*
OUT1
V
EE
OUT2*
OUT2
V
CC
V
EE
V
CC
SEL
SEL*
CLK*
CLK
EN
EN*
V
CC
V
CC
V
EE
IN0
INO*
OUT0*
OUT0
IN1
IN1*
V
CC
OUT3*
OUT3
V
EE
IN3
IN3*
IN2
IN2*
Input Options
OUT
OUT*
VCC
Open Emitter
IN
<
0 - 3
>
IN
<
0 - 3
>
*
Output Options
Open
Application Notes
AN1001 - EPIC Family Product Line
AN1003 - Termination Techniques for ECL /
LVECL / PECL / LVPECL Devices
AN1004 - Interfacing Between LVDS and ECL /
LVECL / PECL / LVPECL
7
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Revision 2 / January 30, 2003
TEST AND MEASUREMENT PRODUCTS
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DC TEST CONDITIONS: Outputs terminated with 50
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SK4400
Quad Buffer/Receiver
AC TEST CONDITIONS: Outputs terminated with 50
to VCC 2V
Note 1. Guaranteed by characterization. Not production tested.
(VCC - VEE = 3.0V to 5.5V; TA = 0
o
C to 70
o
C)
AC Characteristics
(VCC - VEE = 3.0V to 5.5V; TA = 0
o
C to 70
o
C)
DC Characteristics
Revision 2 / January 30, 2003
8
www.semtech.com
TEST AND MEASUREMENT PRODUCTS
The SK4401 is an extremely fast, stable and accurate
low skew quad buffer or cable driver / receiver. It can
asychronously pass four distinct signals, or it can
resynchronize them to a common clock. In addition, all
four outputs may be asynchronously enabled or
disabled. All of the D flip-flops are triggered on the
rising edge of the CLK input.
The SK4401 uses open emitter outputs with a double
amplitude swing suitable for the following applications:
TTL compatible destinations
Double termination situations that require a
full swing at the destination
Long cables
Features
Pin Description
Quad Buffer/Receiver
2 GHz Fmax
4.5V / 5.2V Compatible
Available in 32 lead, 5mm X5mm, TQFP
Package
SK4401
Quad Buffer/Receiver
1
0
OUT3*
OUT3
D
D*
Q
Q*
1
0
OUT2*
OUT2
D
D*
Q
Q*
1
0
OUT1*
OUT1
D
D*
Q
Q*
1
0
OUT0*
OUT0
D
D*
Q
Q*
IN0
IN0*
IN1
IN1*
IN2
IN2*
IN3
IN3*
CLK
CLK*
SEL*
SEL
EN
EN*
Package Information
Functional Block Diagram
Description
V
CC
OUT1*
OUT1
V
EE
OUT2*
OUT2
V
CC
V
EE
V
CC
SEL
SEL*
CLK*
CLK
EN
EN*
V
CC
V
CC
V
EE
IN0
INO*
OUT0*
OUT0
IN1
IN1*
V
CC
OUT3*
OUT3
V
EE
IN3
IN3*
IN2
IN2*
32 pin, 5 mm X 5 mm
TQFP Package
OUT
OUT*
VCC
Input Options
Open Emitter
IN
<
0 - 3
>
IN
<
0 - 3
>
*
Output Options
Open
AN1001 - EPIC Family Product Line
AN1003 - Termination Techniques for ECL /
LVECL / PECL / LVPECL Devices
AN1004 - Interfacing Between LVDS and ECL /
LVECL / PECL / LVPECL
Application Notes
9
www.semtech.com
Revision 2 / January 30, 2003
TEST AND MEASUREMENT PRODUCTS
AC Characteristics
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SK4401
Quad Buffer/Receiver
AC Test Conditions: Outputs terminated with 50
to VCC 3.3V
Note 1. Guaranteed by characterization. Not production tested.
DC Characteristics
(VCC - VE E = 4.2V to 5.5V; TA = 0
o
C to 70
o
C)
(VCC - VE E = 4.2V to 5.5V; TA = 0
o
C to 70
o
C)
Revision 2 / January 30, 2003
10
www.semtech.com
TEST AND MEASUREMENT PRODUCTS
V
CC
OUT1*
OUT1
V
EE
OUT2*
OUT2
V
CC
V
EE
V
CC
SEL
SEL*
CLK*
CLK
EN
EN*
V
CC
V
CC
V
EE
IN0
INO*
OUT0*
OUT0
IN1
IN1*
V
CC
OUT3*
OUT3
V
EE
IN3
IN3*
IN2
IN2*
The SK4404 is an extremely fast, stable and accurate
low skew quad buffer or cable driver / receiver. It can
asychronously pass four distinct signals, or it can
resynchronize them to a common clock. In addition, all
four outputs may be asynchronously enabled or
disabled. All of the D flip-flops are triggered on the
rising edge of the CLK input.
The SK4404 uses 50
outputs with sink/source
capability, and is optimized for applications that require:
Point to point, double terminated, timing
critical lines
Point to point, series terminated, timing
critical lines
Package Information
Functional Block Diagram
Quad Buffer/Driver
3 GHz Fmax
3.3V / 5.2V Compatible
Available in 32 lead, 5mm X5mm, TQFP
Package
1
0
OUT3*
OUT3
D
D*
Q
Q*
1
0
OUT2*
OUT2
D
D*
Q
Q*
1
0
OUT1*
OUT1
D
D*
Q
Q*
1
0
OUT0*
OUT0
D
D*
Q
Q*
IN0
IN0*
IN1
IN1*
IN2
IN2*
IN3
IN3*
CLK
CLK*
SEL*
SEL
EN
EN*
SK4404
Quad Buffer/Receiver
Features
Description
32 pin, 5 mm X 5 mm
TQFP Package
Output Options
50
Source / Sink
Input Options
IN
<
0 - 3
>
IN
<
0 - 3
>
*
Open
OUT
OUT
VEE
VEE
VCC
*
50
50
10 mA
10 mA
AN1001 - EPIC Family Product Line
AN1003 - Termination Techniques for ECL / LVECL
PECL / LVPECL Devices
AN1004 - Interfacing Between LVDS and ECL /
LVECL / PECL / LVPECL
Pin Description
Application Notes
11
www.semtech.com
Revision 2 / January 30, 2003
TEST AND MEASUREMENT PRODUCTS
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C
SK4404
Quad Buffer/Receiver
DC Characteristics
AC Characteristics
AC Test Conditions: Outputs terminated with 50
to VCC 2V
Note 1. Guaranteed by characterization. Not production tested.
(VCC - VEE = 3.0V to 5.5V; TA = 0
o
C to 70
o
C)
(VCC - VEE = 3.0V to 5.5V; TA = 0
o
C to 70
o
C)
Revision 2 / January 30, 2003
12
www.semtech.com
TEST AND MEASUREMENT PRODUCTS
V
CC
OUT1*
OUT1
V
EE
OUT2*
OUT2
V
CC
V
EE
V
CC
SEL
SEL*
CLK*
CLK
EN
EN*
V
CC
V
CC
V
EE
IN0
INO*
OUT0*
OUT0
IN1
IN1*
V
CC
OUT3*
OUT3
V
EE
IN3
IN3*
IN2
IN2*
Package Information
Functional Block Diagram
Quad Buffer/Receiver
3 GHz Fmax
3.3V / 5.2V Compatible
Available in 32 lead, 5mm X5mm, TQFP
Package
The SK4410 is an extremely fast, stable and accurate
low skew quad buffer or cable driver / receiver. It can
asychronously pass four distinct signals, or it can
resynchronize them to a common clock. In addition, all
four outputs may be asynchronously enabled or
disabled. All of the D flip-flops are triggered on the
rising edge of the CLK input.
The SK4410 has 100
input termination resistors
across each of the four inputs to help reduce system
component count and increase integration.
The SK4410 uses standard open emitter ECL outputs
optimized for:
Standard, general purpose ECL applications
Multiple destinations (daisy chain).
1
0
OUT3*
OUT3
D
D*
Q
Q*
1
0
OUT2*
OUT2
D
D*
Q
Q*
1
0
OUT1*
OUT1
D
D*
Q
Q*
1
0
OUT0*
OUT0
D
D*
Q
Q*
IN0
IN0*
IN1
IN1*
IN2
IN2*
IN3
IN3*
CLK
CLK*
SEL*
SEL
EN
EN*
SK4410
Quad Buffer/Receiver
Description
Features
Pin Description
32 pin, 5 mm X 5 mm
TQFP Package
Open Emitter
100W
IN
<
0 - 3
>
IN
<
0 - 3
>
*
Output Options
Input Options
OUT
OUT*
VCC
AN1001 - EPIC Family Product Line
AN1003 - Termination Techniques for ECL / LVECL
PECL / LVPECL Devices
AN1004 - Interfacing Between LVDS and ECL /
LVECL / PECL / LVPECL
Application Notes
13
www.semtech.com
Revision 2 / January 30, 2003
TEST AND MEASUREMENT PRODUCTS
r
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SK4410
Quad Buffer/Receiver
DC Characteristics
AC Test Conditions: Outputs terminated with 50
to VCC 2V
Note 1. Guaranteed by characterization. Not production tested.
AC Characteristics
(VCC - VEE = 3.0V to 5.5V; TA = 0
o
C to 70
o
C)
(VCC - VEE = 3.0V to 5.5V; TA = 0
o
C to 70
o
C)
Revision 2 / January 30, 2003
14
www.semtech.com
TEST AND MEASUREMENT PRODUCTS
SK4411
Quad Buffer/Receiver
Quad Buffer/Receiver
3 GHz Fmax
4.2V / 5.2V Compatible
Available in 32 lead, 5mm X5mm, TQFP
Package
The SK4411 is an extremely fast, stable and accurate
low skew quad buffer or cable driver / receiver. It can
asychronously pass four distinct signals, or it can
resynchronize them to a common clock. In addition, all
four outputs may be asynchronously enabled or
disabled. All of the D flip-flops are triggered on the
rising edge of the CLK input.
The SK4411 has 100
input termination resistors
across each of the four inputs to help reduce system
component count and increase integration.
The SK4411 uses open emitter outputs with a double
amplitude swing suitable for the following applications:
TTL compatible destinations
Double termination situations that require a
full swing at the destination
Long cables
Pin Description
1
0
OUT3*
OUT3
D
D*
Q
Q*
1
0
OUT2*
OUT2
D
D*
Q
Q*
1
0
OUT1*
OUT1
D
D*
Q
Q*
1
0
OUT0*
OUT0
D
D*
Q
Q*
IN0
IN0*
IN1
IN1*
IN2
IN2*
IN3
IN3*
CLK
CLK*
SEL*
SEL
EN
EN*
Functional Block Diagram
Package Information
Description
Features
V
CC
OUT1*
OUT1
V
EE
OUT2*
OUT2
V
CC
V
EE
V
CC
SEL
SEL*
CLK*
CLK
EN
EN*
V
CC
V
CC
V
EE
IN0
INO*
OUT0*
OUT0
IN1
IN1*
V
CC
OUT3*
OUT3
V
EE
IN3
IN3*
IN2
IN2*
32 pin, 5 mm X 5 mm
TQFP Package
Open Emitter
100W
IN
<
0 - 3
>
IN
<
0 - 3
>
*
Output Options
Input Options
OUT
OUT*
VCC
Application Notes
AN1001 - EPIC Family Product Line
AN1003 - Termination Techniques for ECL / LVECL
PECL / LVPECL Devices
AN1004 - Interfacing Between LVDS and ECL /
LVECL / PECL / LVPECL
15
www.semtech.com
Revision 2 / January 30, 2003
TEST AND MEASUREMENT PRODUCTS
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DC Test Conditions: Outputs terminated with 50
to VCC 3.3V.
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C
SK4411
Quad Buffer/Receiver
AC Test Conditions: Outputs terminated with 50
to VCC 3.3V
Note 1. Guaranteed by characterization. Not production tested.
AC Characteristics
DC Characteristics
(VCC - VE E = 4.2V to 5.5V; TA = 0
o
C to 70
o
C)
(VCC - VE E = 4.2V to 5.5V; TA = 0
o
C to 70
o
C)
Revision 2 / January 30, 2003
16
www.semtech.com
TEST AND MEASUREMENT PRODUCTS
SK4414
Quad Buffer/Receiver
Description
Features
Functional Block Diagram
Quad Buffer/Receiver
3 GHz Fmax
3.3V / 5.2V Compatible
Available in 32 lead, 5mm X5mm, TQFP
Package
The SK4414 is an extremely fast, stable and accurate
low skew quad buffer or cable driver / receiver. It can
asychronously pass four distinct signals, or it can
resynchronize them to a common clock. In addition,
all four outputs may be asynchronously enabled or
disabled. All of the D flip-flops are triggered on the
rising edge of the CLK input.
The SK4414 has 100
input termination resistors
across each of the four inputs to help reduce system
component count and increase integration.
The SK4414 uses 50
outputs with sink/source
capability, and is optimized for applications that require:
Point to point, double terminated, timing
critical lines
Point to point, series terminated, timing
critical lines
1
0
OUT3*
OUT3
D
D*
Q
Q*
1
0
OUT2*
OUT2
D
D*
Q
Q*
1
0
OUT1*
OUT1
D
D*
Q
Q*
1
0
OUT0*
OUT0
D
D*
Q
Q*
IN0
IN0*
IN1
IN1*
IN2
IN2*
IN3
IN3*
CLK
CLK*
SEL*
SEL
EN
EN*
Package Information
Pin Description
V
CC
OUT1*
OUT1
V
EE
OUT2*
OUT2
V
CC
V
EE
V
CC
SEL
SEL*
CLK*
CLK
EN
EN*
V
CC
V
CC
V
EE
IN0
INO*
OUT0*
OUT0
IN1
IN1*
V
CC
OUT3*
OUT3
V
EE
IN3
IN3*
IN2
IN2*
32 pin, 5 mm X 5 mm
TQFP Package
50
Source / Sink
OUT
OUT
VEE
VEE
VCC
*
50
50
10 mA
10 mA
100W
IN
<
0 - 3
>
IN
<
0 - 3
>
*
Output Options
Input Options
Application Notes
AN1001 - EPIC Family Product Line
AN1003 - Termination Techniques for ECL / LVECL
PECL / LVPECL Devices
AN1004 - Interfacing Between LVDS and ECL /
LVECL / PECL / LVPECL
17
www.semtech.com
Revision 2 / January 30, 2003
TEST AND MEASUREMENT PRODUCTS
r
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2
A
m
DC Test Conditions: Outputs unterminated.
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C
SK4414
Quad Buffer/Receiver
AC Test Conditions: Outputs terminated with 50
to VCC 2V
Note 1. Guaranteed by characterization. Not production tested.
DC Characteristics
AC Characteristics
(VCC - VEE = 3.0V to 5.5V; TA = 0
o
C to 70
o
C)
(VCC - VEE = 3.0V to 5.5V; TA = 0
o
C to 70
o
C)
Revision 2 / January 30, 2003
18
www.semtech.com
TEST AND MEASUREMENT PRODUCTS
SK4425
Anything to PECL
Functional Block Diagram
Quad Buffer / Receiver
3 GHz Fmax
Anything to PECL Translation
Available in 32 lead, 5mm X5mm, TQFP
Package
The SK4425 is an extremely fast, stable and accurate
low skew quad buffer or cable driver / receiver. It can
asychronously pass four distinct signals, or it can
resynchronize them to a common clock. In addition, all
four outputs may be asynchronously enabled or
disabled. All of the D flip-flops are triggered on the
rising edge of the CLK input. It is also capable of
receiving inputs of any technology or voltage level.
The SK4425 uses standard open emitter ECL outputs
optimized for:
Standard, general purpose ECL
applications
Multiple destinations (daisy chain).
1
0
OUT3*
OUT3
D
D*
Q
Q*
1
0
OUT2*
OUT2
D
D*
Q
Q*
1
0
OUT1*
OUT1
D
D*
Q
Q*
1
0
OUT0*
OUT0
D
D*
Q
Q*
IN0
IN0*
IN1
IN1*
IN2
IN2*
IN3
IN3*
CLK
CLK*
SEL*
SEL
EN
EN*
Description
Package Information
Features
32 pin, 5 mm X 5 mm
TQFP Package
V
CC
OUT1*
OUT1
V
EE
OUT2*
OUT2
V
CC
V
EE
V
CC
SEL
SEL*
CLK*
CLK
EN
EN*
V
CC
V
CC
V
EE
IN0
INO*
OUT0*
OUT0
IN1
IN1*
V
CC
OUT3*
OUT3
V
EE
IN3
IN3*
IN2
IN2*
Output Options
Open Emitter
OUT
OUT*
VCC
Open
IN
<
0 - 3
>
IN
<
0 - 3
>
*
Input Options
Pin Description
Application Notes
AN1001 - EPIC Family Product Line
AN1003 - Termination Techniques for ECL / LVECL
PECL / LVPECL Devices
AN1004 - Interfacing Between LVDS and ECL /
LVECL / PECL / LVPECL
19
www.semtech.com
Revision 2 / January 30, 2003
TEST AND MEASUREMENT PRODUCTS
AC Characteristics
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5
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0
2
1
A
m
DC Test Conditions: Outputs terminated with 50
to VCC 2V.
r
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2
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4
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3
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4
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3
0
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5
0
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7
0
5
6
0
0
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p
s
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0
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e
m
i
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a
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d
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a
e
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i
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t
u
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t
u
O
1
f
T
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r
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5
2
1
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6
1
s
p
t
n
e
i
c
i
f
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e
r
u
t
a
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e
p
m
e
T
1
/
d
p
T
T
1
<
/
s
p
o
C
SK4425
Anything to PECL
AC Test Conditions: Outputs terminated with 50
to VCC 2V
Note 1. Guaranteed by characterization. Not production tested.
DC Characteristics
(VCC = 2.0V to 3.6V; VE E = -3.6 to -3.0V; TA = 0
o
C to 70
o
C)
(VCC = 2.0V to 3.6V; VE E = -3.6 to -3.0V; TA = 0
o
C to 70
o
C)
Revision 2 / January 30, 2003
20
www.semtech.com
TEST AND MEASUREMENT PRODUCTS
SK4426
Anything to ECL
Package Information
Functional Block Diagram
Quad Buffer/Receiver
3 GHz Fmax
Anything to ECL Translation
Available in 32 lead, 5mm X5mm, TQFP
Package
The SK4426 is an extremely fast, stable and accurate
low skew quad buffer or cable driver / receiver. It can
asychronously pass four distinct signals, or it can
resynchronize them to a common clock. In addition, all
four outputs may be asynchronously enabled or
disabled. All of the D flip-flops are triggered on the
rising edge of the CLK input. It is also capable of
receiving inputs of any technology or voltage level.
The SK4426 uses standard open emitter ECL outputs
optimized for:
Standard, general purpose ECL
applications
Multiple destinations (daisy chain).
1
0
OUT3*
OUT3
D
D*
Q
Q*
1
0
OUT2*
OUT2
D
D*
Q
Q*
1
0
OUT1*
OUT1
D
D*
Q
Q*
1
0
OUT0*
OUT0
D
D*
Q
Q*
IN0
IN0*
IN1
IN1*
IN2
IN2*
IN3
IN3*
CLK
CLK*
SEL*
SEL
EN
EN*
Description
Features
32 pin, 5 mm X 5 mm
TQFP Package
V
GG
OUT1*
OUT1
V
EE
OUT2*
OUT2
V
GG
V
EE
V
CC
SEL
SEL*
CLK*
CLK
EN
EN*
V
CC
V
GG
V
EE
IN0
INO*
OUT0*
OUT0
IN1
IN1*
V
GG
OUT3*
OUT3
V
EE
IN3
IN3*
IN2
IN2*
Output Options
Open Emitter
OUT
OUT*
VGG
Input Options
Open
IN
<
0 - 3
>
IN
<
0 - 3
>
*
Pin Description
AN1001 - EPIC Family Product Line
AN1003 - Termination Techniques for ECL / LVECL
PECL / LVPECL Devices
AN1004 - Interfacing Between LVDS and ECL /
PECL / LVPECL
Application Notes
21
www.semtech.com
Revision 2 / January 30, 2003
TEST AND MEASUREMENT PRODUCTS
DC Test Conditions: Outputs terminated with 50
to VGG 2V.
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SK4426
Anything to ECL
AC Test Conditions: Outputs terminated with 50
to VGG 2V
Note 1. Guaranteed by characterization. Not production tested.
DC Characteristics
AC Characteristics
(V
GG
= - 0.1V to 2.0V; V
CC
= 2.0V to 3.6V; VEE = -3.6V to -3.0V; T
A
= 0
o
C to 70
o
C)
(V
GG
= - 0.1V to 2.0V; V
CC
= 2.0V to 3.6V; VEE = -3.6V to -3.0V; T
A
= 0
o
C to 70
o
C)
Revision 2 / January 30, 2003
22
www.semtech.com
TEST AND MEASUREMENT PRODUCTS
SK4429
Anything to PECL
Quad Buffer/Receiver
3 GHz Fmax
Anything to PECL Translation
Available in 32 lead, 5mm X5mm, TQFP
Package
The SK4429 is an extremely fast, stable and accurate
low skew quad buffer or cable driver / receiver. It can
asychronously pass four distinct signals, or it can
resynchronize them to a common clock. In addition, all
four outputs may be asynchronously enabled or
disabled. All of the D flip-flops are triggered on the
rising edge of the CLK input. It is also capable of
receiving inputs of any technology or voltage level.
The SK4429 uses 50
outputs with sink/source
capability, and is optimized for applications that require:
Point to point, double terminated, timing
critical lines
Point to point, series terminated, timing
critical lines
1
0
OUT3*
OUT3
D
D*
Q
Q*
1
0
OUT2*
OUT2
D
D*
Q
Q*
1
0
OUT1*
OUT1
D
D*
Q
Q*
1
0
OUT0*
OUT0
D
D*
Q
Q*
IN0
IN0*
IN1
IN1*
IN2
IN2*
IN3
IN3*
CLK
CLK*
SEL*
SEL
EN
EN*
Functional Block Diagram
Package Information
Pin Description
Features
Description
32 pin, 5 mm X 5 mm
TQFP Package
V
CC
OUT1*
OUT1
V
EE
OUT2*
OUT2
V
CC
V
EE
V
CC
SEL
SEL*
CLK*
CLK
EN
EN*
V
CC
V
CC
V
EE
IN0
INO*
OUT0*
OUT0
IN1
IN1*
V
CC
OUT3*
OUT3
V
EE
IN3
IN3*
IN2
IN2*
Output Options
50
Source / Sink
Input Options
Open
IN
<
0 - 3
>
IN
<
0 - 3
>
*
OUT
OUT
VEE
VEE
VCC
*
50
50
10 mA
10 mA
Application Notes
AN1001 - EPIC Family Product Line
AN1003 - Termination Techniques for ECL / LVECL
PECL / LVPECL Devices
AN1004 - Interfacing Between LVDS and ECL /
LVECL / PECL / LVPECL
23
www.semtech.com
Revision 2 / January 30, 2003
TEST AND MEASUREMENT PRODUCTS
DC Test Conditions: Outputs unterminated.
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/
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p
o
C
SK4429
Anything to PECL
DC Characteristics
AC Test Conditions: Outputs terminated with 50
to VCC 2V
Note 1. Guaranteed by characterization. Not production tested.
AC Characteristics
(V
CC
= 2.0V to 3.6V; VEE = -3.6V to -3.0V; T
A
= 0
o
C to 70
o
C)
(V
CC
= 2.0V to 3.6V; VEE = -3.6V to -3.0V; T
A
= 0
o
C to 70
o
C)
Revision 2 / January 30, 2003
24
www.semtech.com
TEST AND MEASUREMENT PRODUCTS
Functional Block Diagram
Quad Buffer/Receiver
3 GHz Fmax
Anything to ECL Translation
Available in 32 lead, 5mm X5mm, TQFP
Package
The SK4430 is an extremely fast, stable and accurate
low skew quad buffer or cable driver / receiver. It can
asychronously pass four distinct signals, or it can
resynchronize them to a common clock. In addition, all
four outputs may be asynchronously enabled or
disabled. All of the D flip-flops are triggered on the
rising edge of the CLK input. It is also capable of
receiving inputs of any technology or voltage level.
The SK4430 uses 50
outputs with sink/source
capability, and is optimized for applications that require:
Point to point, double terminated, timing
critical lines
Point to point, series terminated, timing
critical lines
SK4430
Anything to ECL Receiver
Features
1
0
OUT3*
OUT3
D
D*
Q
Q*
1
0
OUT2*
OUT2
D
D*
Q
Q*
1
0
OUT1*
OUT1
D
D*
Q
Q*
1
0
OUT0*
OUT0
D
D*
Q
Q*
IN0
IN0*
IN1
IN1*
IN2
IN2*
IN3
IN3*
CLK
CLK*
SEL*
SEL
EN
EN*
Description
Pin Description
Package Information
32 pin, 5 mm X 5 mm
TQFP Package
V
GG
OUT1*
OUT1
V
EE
OUT2*
OUT2
V
GG
V
EE
V
CC
SEL
SEL*
CLK*
CLK
EN
EN*
V
CC
V
GG
V
EE
IN0
INO*
OUT0*
OUT0
IN1
IN1*
V
GG
OUT3*
OUT3
V
EE
IN3
IN3*
IN2
IN2*
Application Notes
Output Options
50
Source / Sink
Input Options
Open
IN
<
0 - 3
>
IN
<
0 - 3
>
*
OUT
OUT
VEE
VEE
VGG
*
50
50
10 mA
10 mA
AN1001 - EPIC Family Product Line
AN1003 - Termination Techniques for ECL / LVECL
PECL / LVPECL Devices
AN1004 - Interfacing Between LVDS and ECL /
LVECL / PECL / LVPECL
25
www.semtech.com
Revision 2 / January 30, 2003
TEST AND MEASUREMENT PRODUCTS
DC Test Conditions: Outputs unterminated.
r
e
t
e
m
a
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a
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<
/
s
p
o
C
SK4430
Anything to ECL
DC Characteristics
AC Test Conditions: Outputs terminated with 50
to VGG 2V
Note 1. Guaranteed by characterization. Not production tested.
AC Characteristics
(V
GG
= - 0.1V to 2.0V; V
CC
= 2.0V to 3.6V; VEE = -3.6V to -3.0V; T
A
= 0
o
C to 70
o
C)
(V
GG
= - 0.1V to 2.0V; V
CC
= 2.0V to 3.6V; VEE = -3.6V to -3.0V; T
A
= 0
o
C to 70
o
C)
Revision 2 / January 30, 2003
26
www.semtech.com
TEST AND MEASUREMENT PRODUCTS
SK4435
Anything to PECL Receiver
Package Information
Functional Block Diagram
Quad Buffer/Receiver
3 GHz Fmax
Anything to PECL Translation
Available in 32 lead, 5mm X5mm, TQFP
Package
The SK4435 is an extremely fast, stable and accurate
low skew quad buffer or cable driver / receiver. It can
asychronously pass four distinct signals, or it can
resynchronize them to a common clock. In addition, all
four outputs may be asynchronously enabled or
disabled. All of the D flip-flops are triggered on the
rising edge of the CLK input. It is also capable of
receiving inputs of any technology or voltage level.
The SK4435 has 100
input termination resistors
across each of the four inputs to help reduce system
component count and increase integration.
The SK4435 uses standard open emitter ECL outputs
optimized for:
Standard, general purpose applications
Multiple destinations (daisy chain).
Pin Description
Description
1
0
OUT3*
OUT3
D
D*
Q
Q*
1
0
OUT2*
OUT2
D
D*
Q
Q*
1
0
OUT1*
OUT1
D
D*
Q
Q*
1
0
OUT0*
OUT0
D
D*
Q
Q*
IN0
IN0*
IN1
IN1*
IN2
IN2*
IN3
IN3*
CLK
CLK*
SEL*
SEL
EN
EN*
Features
32 pin, 5 mm X 5 mm
TQFP Package
V
CC
OUT1*
OUT1
V
EE
OUT2*
OUT2
V
CC
V
EE
V
CC
SEL
SEL*
CLK*
CLK
EN
EN*
V
CC
V
CC
V
EE
IN0
INO*
OUT0*
OUT0
IN1
IN1*
V
CC
OUT3*
OUT3
V
EE
IN3
IN3*
IN2
IN2*
Output Options
Open Emitter
Input Options
OUT
OUT*
VCC
100W
IN
<
0 - 3
>
IN
<
0 - 3
>
*
Application Notes
AN1001 - EPIC Family Product Line
AN1003 - Termination Techniques for ECL / LVECL
PECL / LVPECL Devices
AN1004 - Interfacing Between LVDS and ECL /
LVECL / PECL / LVPECL
27
www.semtech.com
Revision 2 / January 30, 2003
TEST AND MEASUREMENT PRODUCTS
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SK4435
Anything to PECL Receiver
AC Test Conditions: Outputs terminated with 50
to VCC 2V
Note 1. Guaranteed by characterization. Not production tested.
DC Characteristics
AC Characteristics
(V
CC
= 2.0V to 3.6V; VEE = -3.6V to -3.0V; T
A
= 0
o
C to 70
o
C)
(V
CC
= 2.0V to 3.6V; VEE = -3.6V to -3.0V; T
A
= 0
o
C to 70
o
C)
Revision 2 / January 30, 2003
28
www.semtech.com
TEST AND MEASUREMENT PRODUCTS
SK4436
Anything to ECL Receiver
Package Information
Functional Block Diagram
Quad Buffer/Receiver
3 GHz Fmax
Anything to ECL Translation
Available in 32 lead, 5mm X5mm, TQFP
Package
The SK4436 is an extremely fast, stable and accurate
low skew quad buffer or cable driver / receiver. It can
asychronously pass four distinct signals, or it can
resynchronize them to a common clock. In addition, all
four outputs may be asynchronously enabled or
disabled. All of the D flip-flops are triggered on the
rising edge of the CLK input. It is also capable of
receiving inputs of any technology or voltage level.
The SK4436 has 100
input termination resistors
across each of the four inputs to help reduce system
component count and increase integration.
The SK4436 uses standard open emitter ECL outputs
optimized for:
Standard, general purpose applications
Multiple destinations (daisy chain).
Pin Description
1
0
OUT3*
OUT3
D
D*
Q
Q*
1
0
OUT2*
OUT2
D
D*
Q
Q*
1
0
OUT1*
OUT1
D
D*
Q
Q*
1
0
OUT0*
OUT0
D
D*
Q
Q*
IN0
IN0*
IN1
IN1*
IN2
IN2*
IN3
IN3*
CLK
CLK*
SEL*
SEL
EN
EN*
32 pin, 5 mm X 5 mm
TQFP Package
V
GG
OUT1*
OUT1
V
EE
OUT2*
OUT2
V
GG
V
EE
V
CC
SEL
SEL*
CLK*
CLK
EN
EN*
V
CC
V
GG
V
EE
IN0
INO*
OUT0*
OUT0
IN1
IN1*
V
GG
OUT3*
OUT3
V
EE
IN3
IN3*
IN2
IN2*
Description
Features
Output Options
Open Emitter
Input Options
100W
IN
<
0 - 3
>
IN
<
0 - 3
>
*
OUT
OUT*
VGG
Application Notes
AN1001 - EPIC Family Product Line
AN1003 - Termination Techniques for ECL / LVECL
PECL / LVPECL Devices
AN1004 - Interfacing Between LVDS and ECL /
LVECL / PECL / LVPECL
29
www.semtech.com
Revision 2 / January 30, 2003
TEST AND MEASUREMENT PRODUCTS
DC Test Conditions: Outputs terminated with 50
to VGG 2V.
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p
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1
/
d
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1
<
/
s
p
o
C
SK4436
Anything to ECL Receiver
AC Test Conditions: Outputs terminated with 50
to VGG 2V
Note 1. Guaranteed by characterization. Not production tested.
DC Characteristics
AC Characteristics
(V
GG
= - 0.1V to 2.0V; V
CC
= 2.0V to 3.6V; VEE = -3.6V to -3.0V; T
A
= 0
o
C to 70
o
C)
(V
GG
= - 0.1V to 2.0V; V
CC
= 2.0V to 3.6V; VEE = -3.6V to -3.0V; T
A
= 0
o
C to 70
o
C)
Revision 2 / January 30, 2003
30
www.semtech.com
TEST AND MEASUREMENT PRODUCTS
SK4439
Anything to PECL Receiver
Description
Features
Package Information
Functional Block Diagram
Quad Buffer/Receiver
3 GHz Fmax
Anything to PECL Translation
Available in 32 lead, 5mm X5mm, TQFP
Package
The SK4439 is an extremely fast, stable and accurate
low skew quad buffer or cable driver / receiver. It can
asychronously pass four distinct signals, or it can
resynchronize them to a common clock. In addition, all
four outputs may be asynchronously enabled or
disabled. All of the D flip-flops are triggered on the
rising edge of the CLK input. It is also capable of
receiving inputs of any technology or voltage level.
The SK4439 has 100
input termination resistors
across each of the four inputs to help reduce system
component count and increase integration.
The SK4439 uses 50
outputs with sink/source
capability, and is optimized for applications that require:
Point to point, double terminated, timing
critical lines
Point to point, series terminated, timing
critical lines
Pin Description
1
0
OUT3*
OUT3
D
D*
Q
Q*
1
0
OUT2*
OUT2
D
D*
Q
Q*
1
0
OUT1*
OUT1
D
D*
Q
Q*
1
0
OUT0*
OUT0
D
D*
Q
Q*
IN0
IN0*
IN1
IN1*
IN2
IN2*
IN3
IN3*
CLK
CLK*
SEL*
SEL
EN
EN*
32 pin, 5 mm X 5 mm
TQFP Package
V
CC
OUT1*
OUT1
V
EE
OUT2*
OUT2
V
CC
V
EE
V
CC
SEL
SEL*
CLK*
CLK
EN
EN*
V
CC
V
CC
V
EE
IN0
INO*
OUT0*
OUT0
IN1
IN1*
V
CC
OUT3*
OUT3
V
EE
IN3
IN3*
IN2
IN2*
Output Options
50
Source / Sink
Input Options
OUT
OUT
VEE
VEE
VCC
*
50
50
10 mA
10 mA
100W
IN
<
0 - 3
>
IN
<
0 - 3
>
*
Application Notes
AN1001 - EPIC Family Product Line
AN1003 - Termination Techniques for ECL / LVECL
PECL / LVPECL Devices
AN1004 - Interfacing Between LVDS and ECL /
LVECL / PECL / LVPECL
31
www.semtech.com
Revision 2 / January 30, 2003
TEST AND MEASUREMENT PRODUCTS
DC Test Conditions: Outputs unterminated.
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SK4439
Anything to PECL
DC Characteristics
AC Test Conditions: Outputs terminated with 50
to VCC 2V
Note 1. Guaranteed by characterization. Not production tested.
AC Characteristics
(V
CC
= 2.0V to 3.6V; VEE = -3.6V to -3.0V; T
A
= 0
o
C to 70
o
C)
(V
CC
= 2.0V to 3.6V; VEE = -3.6V to -3.0V; T
A
= 0
o
C to 70
o
C)
Revision 2 / January 30, 2003
32
www.semtech.com
TEST AND MEASUREMENT PRODUCTS
SK4440
Anything to ECL
Functional Block Diagram
Quad Buffer/Receiver
3 GHz Fmax
Available in 32 lead, 5mm X5mm, TQFP
Package
The SK4440 is an extremely fast, stable and accurate
low skew quad buffer or cable driver / receiver. It can
asychronously pass four distinct signals, or it can
resynchronize them to a common clock. In addition, all
four outputs may be asynchronously enabled or
disabled. All of the D flip-flops are triggered on the
rising edge of the CLK input. It is also capable of
receiving inputs of any technology or voltage level.
The SK4440 has 100
input termination resistors
across each of the four inputs to help reduce system
component count and increase integration.
The SK4440 uses 50
outputs with sink/source
capability, and is optimized for applications that require:
Point to point, double terminated, timing
critical lines
Point to point, series terminated, timing
critical lines
1
0
OUT3*
OUT3
D
D*
Q
Q*
1
0
OUT2*
OUT2
D
D*
Q
Q*
1
0
OUT1*
OUT1
D
D*
Q
Q*
1
0
OUT0*
OUT0
D
D*
Q
Q*
IN0
IN0*
IN1
IN1*
IN2
IN2*
IN3
IN3*
CLK
CLK*
SEL*
SEL
EN
EN*
Features
Pin Description
Description
Package Information
32 pin, 5 mm X 5 mm
TQFP Package
V
GG
OUT1*
OUT1
V
EE
OUT2*
OUT2
V
GG
V
EE
V
CC
SEL
SEL*
CLK*
CLK
EN
EN*
V
CC
V
GG
V
EE
IN0
INO*
OUT0*
OUT0
IN1
IN1*
V
GG
OUT3*
OUT3
V
EE
IN3
IN3*
IN2
IN2*
Output Options
50
Source / Sink
Input Options
OUT
OUT
VEE
VEE
VGG
*
50
50
10 mA
10 mA
100W
IN
<
0 - 3
>
IN
<
0 - 3
>
*
AN1001 - EPIC Family Product Line
AN1003 - Termination Techniques for ECL / LVECL
PECL / LVPECL Devices
AN1004 - Interfacing Between LVDS and ECL /
LVECL / ECL / LVPECL
AN1008 - Interfacing with CML
Application Notes
r ECL / LVECL
and ECL /
33
www.semtech.com
Revision 2 / January 30, 2003
TEST AND MEASUREMENT PRODUCTS
DC Test Conditions: Outputs unterminated.
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1
/
d
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1
<
/
s
p
o
C
SK4440
Anything to ECL Receiver
AC Test Conditions: Outputs terminated with 50
to VGG 2V
Note 1. Guaranteed by characterization. Not production tested.
DC Characteristics
AC Characteristics
(V
GG
= - 0.1V to 2.0V; V
CC
= 2.0V to 3.6V; VEE = -3.6V to -3.0V; T
A
= 0
o
C to 70
o
C)
(V
GG
= - 0.1V to 2.0V; V
CC
= 2.0V to 3.6V; VEE = -3.6V to -3.0V; T
A
= 0
o
C to 70
o
C)
Revision 2 / January 30, 2003
34
www.semtech.com
TEST AND MEASUREMENT PRODUCTS
SK44XX Family
Quad Buffer/Receiver
e
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o
C
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Notes:
1.
For tape and reel, add the letter T at the
end of ordering code.
2.
For tape and reel information, see TMD Part
Ordering Information Data Sheet.
Contact Information
Ordering Information
Semtech Corporation
Test and Measurement Division
10021 Willow Creek Rd., San Diego, CA 92131
Phone: (858) 695-1808 FAX: (858) 695-2633
PDF 
ZIP