Cool Solutions for Wireless Connectivity
XEMICS SA
e-mail: info@xemics.com
web: www.xemics.com
Datasheet XE88LC01/01A
Sensing Machine
Data Acquisition with ZoomingADC
XE88LC01/01A
Sensing Machine
Data Acquisition with 16+10 bit ZoomingADCTM
General Description
The XE88LC01A is a data acquisition ultra low-
power low-voltage system on a chip (SoC) with a
high efficiency embedded microcontroller unit
(MCU), allowing for 1 MIPS at 300uA and 2.4 V,
and multiplying in one clock cycle.
The XE88LC01A includes a high resolution
acquisition path with16+10 bits.
The XE88LC01A is available with on chip ROM or
Multiple-Time-Programmable (MTP) program
memory.
Applications
Portable, battery operated instruments
Current loop powered instruments
Wheatstone bridge interfaces
Pressure and chemical sensors
HVAC
control
Metering
Sports watches, wrist instruments
Key product Features
Low-power, high resolution ZoomingADC
0.5 to 1000 gain with offset cancellation
up to 16 bits analog to digital converter
up to 13 inputs multiplexer
Low-voltage
low-power
controller operation
2 MIPS with 2.4 V to 5.5 V operation
300 A at 1 MIPS over voltage range
22 kByte (8 kInstruction) MTP
520 Byte RAM data memory
RC and crystal oscillators
5 reset, 22 interrupt, 8 event sources
100 years MTP Flash retention at 55C
Ordering Information
Product Temperature
range
Memory
type
Package
XE88LC01MI027*
-40C to 85 C
MTP
LQFP44
XE88LC01AMI000
-40C to 85 C
MTP
Die
XE88LC01AMI027
-40C to 85 C
MTP
LQFP44
XE88LC01ARE000
-40C to 125 C
ROM
Die
XE88LC01ARE027
-40C to 125 C
ROM
LQFP44
*Not for new designs
D0304-60
Datasheet XE88LC01/01A
Sensing Machine
Data Acquisition with ZoomingADC
TABLE OF CONTENTS
Chapter 1
XE88LC01/01A Overview
Chapter 2
XE88LC01/01A Performance
Chapter 3
XE88LC01/01A CPU
Chapter 4
XE88LC01/01A Memory
Chapter 5
System Block
Chapter 6
Reset generator
Chapter 7
Clock generation
Chapter 8
Interrupt handler
Chapter 9
Event handler
Chapter 10
Low power RAM
Chapter 11
Port A
Chapter 12
Port B
Chapter 13
Port C
Chapter 14
Universal Asynchronous Receiver/Transmitter (UART)
Chapter 15
Universal Synchronous Receiver/Transmitter (USRT)
Chapter 16
Acquisition Chain
Chapter 17
Voltage multiplier
Chapter 18
Counters/Timers/PWM
Chapter 19
The Voltage Level Detector
Chapter 20
XE88LC01/01A Dimensions
1-2
D0304-60
Datasheet
XE88LC01/01A
1.1 Top schematic
1.1.1 General description
The top level block schematic of the circuit is shown in Figure 1-1. The heart of the circuit consists of
the Coolrisc816 CPU core. This core includes an 8x8 multiplier and 16 internal registers.
The bus controller generates all control signals for access to all data registers other than the CPU
internal registers.
The reset block generates the adequate reset signals for the rest of the circuit as a function of the set-
up contained in its control registers. Possible reset sources are the power-on-reset (POR), the
external pin RESET, the watchdog (WD), a bus error detected by the bus controller or a
programmable pattern on Port A. Different low power modes are implemented.
The clock generation and power management block sets up the clock signals and generates internal
supplies for different blocks. The clock can be generated from the RC oscillator (this is the start-up
condition), the crystal oscillator (XTAL) or an external clock source (given on the OSCIN pin).
The test controller generates all set-up signals for different test modes. In normal operation, it is used
as a set of 8 low power data registers. If power consumption is important for the application, the
variables that need to be accessed very often should be stored in these registers rather than in the
RAM.
The IRQ handler routes the interrupt signals of the different peripherals to the IRQ inputs of the CPU
core. It allows masking of the interrupt sources and it flags which interrupt source is active.
Events are generally used to restart the processor after a HALT period without jumping to a specified
address, i.e. the program execution resumes with the instruction following the HALT instruction. The
EVN handler routes the event signals of the different peripherals to the EVN inputs of the CPU core. It
allows masking of the interrupt sources and it flags which interrupt source is active.
The Port B is an 8 bit parallel IO port with analog capabilities. The URST, UART, and PWM block also
make use of this port.
The instruction memory is a 22-bit wide flash or ROM memory depending on the circuit version. Flash
and ROM versions have both 8k instruction memory.
The data memory on this product is a 512 byte SRAM.
The Acquisition Chain is a high resolution acquisition path with the 16+10 bits ZoomingADC
. The
VMULT (voltage multiplier) powers a part of the Acquisition Chain.
Port A is an 8 bit parallel input port. It can also generate interrupts, events or a reset. It can be used to
input external clocks for the timer/counter/PWM block.
Port C is a general purpose 8 bit parallel I/O port.
The USRT (universal synchronous receiver/transmitter) contains some simple hardware functions in
order to simplify the software implementation of a synchronous serial link.
The UART (universal asynchronous receiver/transmitter) contains a full hardware implementation of
the asynchronous serial link.
The counters/timers/PWM can take its clocks from internal or external sources (on Port A) and can
generate interrupts or events. The PWM is output on Port B.
1-3
D0304-60
Datasheet
XE88LC01/01A
The VLD (voltage level detector) detects the battery end of life with respect to a programmable
threshold.
INSTRUCTION MEMORY
B
U
S
C
O
N
T
R
O
L
L
E
R
TEST
CONTROLLER
RESET
BLOCK
WD
CLOCK
GENERATION/
POWER
MANAGEMENT
VREG
XTAL
RC
CPU
COOLRISC816
8
X
8
MULTIPLIER
16
CPU
REGISTERS
IRQ HANDLING
EVN HANDLING
PORT B
8 DATA REGISTERS
PORT A
USRT
PORT C
address
control
datain
dataout
reset
control
clocks
test
control
irq
evn
VPP/TEST
VBAT
VSS
RESET
OSCIN
OSCOUT
VREG
PB(7:0)
PA(7:0)
PC(7:0)
AC_R(3:0)
AC_A(7:0)
VMULT
DATA
MEMORY
UART
COUNTERS
TIMERS
PWM
VLD
PB
(5
:
4
)
P
B
(7
:
6
)
PA
(3:
0
)
PB
(1
:
0
)
POR
ACQUISITION
CHAIN
ZoomingADC
VMULT
Figure 1-1. Block schematic of the XE88LC01/01A circuit.
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