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1
DESCRIPTION
The LH168M is a 384-output TFT-LCD source
driver IC which can simultaneously display 262 144
colors in 64 gray scales.
FEATURES
Number of LCD drive outputs : 384
Built-in 6-bit digital input DAC
Dot-inversion drive : Outputs the inverted gray
scale voltages between LCD drive pins next to
each other
RSDS
TM*
(R
_educed S
_wing D
_ifferential S
_ignaling)
input interface (Data and CK) : Possible to reduce
E
_lectro-M
_ agnetic I_nterference (EMI)
Possible to display 262 144 colors in 64 gray scales
with reference voltage input of 18 gray scales : This
reference voltage input corresponds to < correction
and intermediate reference voltage input can be
abbreviated
Cascade connection
Sampling sequence :
Output shift direction can be selected
XO
1
, YO
1
, ZO
1
/XO
128
, YO
128
, ZO
128
or
ZO
128
, YO
128
, XO
128
/ZO
1
, YO
1
, XO
1
Shift clock frequency : 68 MHz (MAX.)
Supply voltages
V
CC
(for logic system) : +3.0 to +3.6 V
V
LS
(for LCD drive system) : +12 V (MAX.)
Package : 434-pin TCP (Tape Carrier Package)
* RSDS is a trademark of National Semiconductor Corporation.
SHARP recommends FPD87310 of National Semiconductor
Corporation as a timing controller for RSDS
TM
.
PIN CONNECTIONS
LH168M
LH168M
384-output TFT-LCD Source Driver IC
XO
128
YO
128
ZO
128
382
383
384
XO
1
YO
1
ZO
1
1
2
3
CHIP SURFACE
SPOI
X
0
P
X
0
N
X
1
P
X
1
N
X
2
P
X
2
N
POL
REV
LS
CKP
CKN
GND
GND
VH
0
VH
8
VH
16
VH
24
VH
32
VH
40
VH
48
VH
56
VH
64
GND
V
LS
VL
64
VL
56
VL
48
VL
40
VL
32
VL
24
VL
16
VL
8
VL
0
LBR
V
CC
V
CC
Y
0
P
Y
0
N
Y
1
P
Y
1
N
Y
2
P
Y
2
N
Z
0
P
Z
0
N
Z
1
P
Z
1
N
Z
2
P
Z
2
N
SPIO
434
433
432
431
430
429
428
427
426
425
424
423
422
421
420
419
418
417
416
415
414
413
412
411
410
409
408
407
406
405
404
403
402
401
400
399
398
397
396
395
394
393
392
391
390
389
388
387
386
385
434-PIN TCP
TOP VIEW
NOTE :
Doesn't prescribe TCP outline.
LH168M
2
PIN DESCRIPTION
PIN NO.
SYMBOL
I/O
DESCRIPTION
1 to 384
XO
1
-ZO
128
O
LCD drive output pins
385
SPIO
I/O
Start pulse input/cascade output pin
386 to 391
Z
2
N-Z
0
P
I
Data input pins
392 to 397
Y
2
N-Y
0
P
I
Data input pins
398, 399
V
CC
Power supply pins for digital circuit
400
LBR
I
Shift direction selection input pin
401 to 409
VL
0
-VL
64
I
Reference voltage input pins
410
V
LS
Power supply pin for analog circuit
411, 421, 422
GND
Ground pins
412 to 420
VH
64
-VH
0
I
Reference voltage input pins
423, 424
CKN, CKP
I
Shift clock input pins
425
LS
I
Latch input pin
426
REV
I
LCD drive output polarity exchange input pin
427
POL
I
Input data polarity exchange input pin
428 to 433
X
2
N-X
0
P
I
Data input pins
434
SPOI
I/O
Start pulse input/cascade output pin
LH168M
4
FUNCTIONAL OPERATIONS OF EACH BLOCK
INPUT/OUTPUT CIRCUITS
I
V
CC
GND
To Internal Circuit
Fig. 1 Input Circuit (1)
Applicable pins
LBR, LS, REV
I
V
CC
GND
GND
To Internal Circuit
Fig. 2 Input Circuit (2)
Applicable pin
POL
BLOCK FUNCTION
Shift Register
Used as a bi-directional shift register which performs the shifting operation by CK and
selects bits for data sampling.
Data Latch
Used to temporary latch the input data which is sent to the sampling memory.
Comparator
Convert low voltage input signal into internal [CMOS level] voltage input signal.
Sampling Memory
Used to sample the data to be entered by time sharing.
Hold Memory
Used for latch processing of data in the sampling memory by LS input.
Level Shifter
Used to shift the data in the hold memory to the power supply level of the analog circuit
unit and sends the shifted data to DA converter.
Reference Voltage
Generation Circuit
Used to generate a gamma-connected 64 x 2-level voltage by the resistor dividing circuit.
DA Converter
Used to generate an analog signal according to the display data and sends the signal to
the output circuit.
Output Circuit
Used as a voltage follower, configured with an operational amplifier and an output buffer,
which outputs analog signals of 64 x 2 gray scales to LCD drive output pin.
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