LH28F320S3TD-L10

32 M-bit (2 MB x 8/1 MB x 16 x 2-Bank)

Smart 3 Dual Work Flash Memory

DESCRIPTION

The LH28F320S3TD-L10 Dual Work flash memory
with Smart 3 technology is a high-density, low-cost,
nonvolatile, read/write storage solution for a wide
range of applications, having high programming
performance is achieved through highly-optimized
page buffer operations. Its symmetrically-blocked
architecture, flexible voltage and enhanced cycling
capability provide for highly flexible component
suitable for resident flash arrays, SIMMs and
memory cards. Its enhanced suspend capabilities
provide for an ideal solution for code + data storage
applications. For secure code storage applications,
such as networking, where code is either directly
executed out of flash or downloaded to DRAM, the
LH28F320S3TD-L10 offers three levels of
protection : absolute protection with V

at GND,

selective hardware block locking, or flexible
software block locking. These alternatives give
designers ultimate control of their code security
needs. LH28F320S3TD-L10 is conformed to the
flash Scalable Command Set (SCS) and the
Common Flash Interface (CFI) specification which
enable universal and upgradable interface, enable
the highest system/device data transfer rates and
minimize device and system-level implementation
costs.

FEATURES

· Smart 3 Dual Work technology

2.7 V or 3.3 V V

2.7 V, 3.3 V or 5 V V

Capable of performing erase, write and read

for each bank independently (Impossible to
perform read from both banks at a time).

· High-speed write performance

Two 32-byte page buffers/bank
2.7 µs/byte write transfer rate

· Common Flash Interface (CFI)

Universal & upgradable interface

· Scalable Command Set (SCS)
· High performance read access time

100 ns (3.3±0.3 V)/120 ns (2.7 to 3.6 V)

· Enhanced automated suspend options

Write suspend to read
Block erase suspend to write
Block erase suspend to read

· Enhanced data protection features

Absolute protection with V

= GND

Flexible block locking
Erase/write lockout during power transitions

· SRAM-compatible write interface
· User-configurable x8 or x16 operation
· High-density symmetrically-blocked architecture

Sixty-four 64 k-byte erasable blocks

· Enhanced cycling capability

100 000 block erase cycles
3.2 million block erase cycles/bank

· Low power management

Deep power-down mode
Automatic power saving mode decreases Icc

in static mode

· Automated write and erase

Command user interface
Status register

· ETOX

V nonvolatile flash technology

· Package

56-pin TSOP Type I (TSOP056-P-1420)

Normal bend

ETOX is a trademark of Intel Corporation.

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In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books,
etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.

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LH28F320S3TD-L10

SYMBOL

TYPE

NAME AND FUNCTION

ADDRESS INPUTS : Inputs for addresses during read and write operations. Addresses
are internally latched during a write cycle.
A

: Byte Select Address. Not used in x16 mode (can be floated).

-A

: Column Address. Selects 1 of 16-bit lines.

-A

: Row Address. Selects 1 of 2 048-word lines.

-A

: Block Address.

DATA INPUT/OUTPUTS :
DQ

-DQ

: Inputs data and commands during CUI write cycles; outputs data during

memory array, status register, query, and identifier code read cycles. Data pins float to
high-impedance when the chip is deselected or outputs are disabled. Data is internally
latched during a write cycle.
DQ

-DQ

: Inputs data during CUI write cycles in x16 mode; outputs data during

memory array read cycles in x16 mode; not used for status register, query and identifier
code read mode. Data pins float to high-impedance when the chip is deselected, outputs
are disabled, or in x8 mode (BYTE# = V

). Data is internally latched during a write cycle.

BANK ENABLE : Activates the device's control logic, input buffers, decoders, and sense
amplifiers. When BE

# and BE

# "low", bank0 is in active. When BE

# and BE

# are

"low", bank1 is in active. BE

# and BE

#, BE

# must not be low at the same time.

RP#

INPUT

RESET/DEEP POWER-DOWN : Puts the device in deep power-down mode and resets
internal automation. RP# V

enables normal operation. When driven V

, RP# inhibits

write operations which provide data protection during power transitions. Exit from deep
power-down sets the device to read array mode.

OE#

INPUT

OUTPUT ENABLE : Gates the device's outputs during a read cycle.

WE#

INPUT

WRITE ENABLE : Controls writes to the CUI and array blocks. Addresses and data are
latched on the rising edge of the WE# pulse.
STS (RY/BY#) : Indicates the status of the internal WSM. When configured in level
mode (default mode) , it acts as a RY/BY# pin. When low, the WSM is performing an
internal operation (block erase, bank erase, (multi) word/byte write or block lock-bit
configuration). STS High Z indicates that the WSM is ready for new commands, block
ease is suspended, and (multi) word/byte write is inactive, (multi) word/byte write is
suspended or the device is in deep power-down mode. For alternate configurations of
the STATUS pin, see the Configuration command (Table 3 and Section 4.14).

WP#

INPUT

WRITE PROTECT : Master control for block locking. When V

, locked blocks can not

be erased and programmed, and block lock-bits can not be set and reset.

BYTE#

INPUT

BYTE ENABLE : BYTE# V

places device in x8 mode. All data are then input or output

on DQ

0-7

, and DQ

8-15

float. BYTE# V

places the device in x16 mode, and turns off the

input buffer.

BLOCK ERASE, BANK ERASE, (MULTI) WORD/BYTE WRITE, BLOCK LOCK-BIT
CONFIGURATION POWER SUPPLY : For erasing array blocks, writing bytes or
configuring block lock-bits. With V

PPLK

, memory contents cannot be altered. Block

erase, bank erase, word/byte write, and block lock-bit configuration with an invalid V

(see Section 6.2.3 "DC CHARACTERISTICS") produce spurious results and should
not be attempted.
DEVICE POWER SUPPLY : Internal detection configures the device for 2.7 V or 3.3 V
operation. To switch from one voltage to another, ramp V

down to GND and then ramp

to the new voltage. Do not float any power pins. With V

LKO

, all write attempts

to the flash memory are inhibited. Device operations at invalid V

voltage (see Section

6.2.3 "DC CHARACTERISTICS") produce spurious results and should not be attempted.

GND

SUPPLY

GROUND : Do not float any ground pins.

NO CONNECT : Lead is not internal connected; recommend to be floated.

-DQ

INPUT/

OUTPUT

OPEN

STS

DRAIN

OUTPUT

-A

INPUT

SUPPLY

PIN DESCRIPTION

INPUT

#, BE

LH28F320S3TD-L10

1 INTRODUCTION

This datasheet contains LH28F320S3TD-L10
specifications. Section 1 provides a flash memory
overview. Sections 2, 3, 4, and 5 describe the memory
organization and functionality. Section 6 covers
electrical specifications. The LH28F320S3TD-L10
flash memory documentation also includes ordering
information which is referenced in Section 7.

1.1

Product Overview

The LH28F320S3TD-L10 is a high-performance
32 M-bit Smart 3 Dual Work flash memory
organized as 2 MB x8/1 MB x 16 x 2-Bank. The
4 MB of data is arranged in sixty-four 64 k-byte
blocks which are individually erasable, lockable,
and unlockable in-system. The memory map is
shown in Fig. 1.

Smart 3 technology provides a choice of V

and

combinations, as shown in Table 1, to meet

system performance and power expectations. V

at 2.7 V, 3.3 V and 5 V eliminates the need for a
separate 12 V converter. In addition to flexible
erase and program voltages, the dedicated V

gives complete data protection when V

PPLK

Table 1 V

and V

Voltage Combinations

Offered by Smart 3 Technology

Internal V

and V

detection circuitry auto-

matically configures the device for optimized read
and write operations.

A Command User Interface (CUI) serves as the
interface between the system processor and internal
operation of the device. A valid command sequence
written to the CUI initiates device automation. An
internal Write State Machine (WSM) automatically
executes the algorithms and timings necessary for
block erase, bank erase, (multi) word/byte write and
block lock-bit configuration operations.

A block erase operation erases one of the device's
64 k-byte blocks typically within 0.41 second (3.3 V
V

, 5 V V

) independent of other blocks. Each

block can be independently erased 100 000 times
(3.2 million block erases per bank). Block erase
suspend mode allows system software to suspend
block erase to read data from, or write data to any
other block.

A word/byte write is performed in byte increments
typically within 12.95 µs (3.3 V V

, 5 V V

). A

multi word/byte write has high speed write
performance of 2.7 µs/byte (3.3 V V

, 5 V V

(Multi) word/byte write suspend mode enables the
system to read data from, or write data to any other
flash memory array location.

Individual block locking uses a combination of bits
and WP#, sixty-four block lock-bits per bank, to lock
and unlock blocks. Block lock-bits gate block erase,
bank erase and (multi) word/byte write operations.
Block lock-bit configuration operations (Set Block
Lock-Bit and Clear Block Lock-Bits commands) set
and cleared block lock-bits.

The status register indicates when the WSM's block
erase, bank erase, (multi) word/byte write or block
lock-bit configuration operation is finished.

The STS output gives an additional indicator of
WSM activity by providing both a hardware signal
of status (versus software polling) and status
masking (interrupt masking for background block
erase, for example). Status polling using STS
minimizes both CPU overhead and system power
consumption. STS pin can be configured to
different states using the Configuration command.
The STS pin defaults to RY/BY# operation. When
low, STS indicates that the WSM is performing a
block erase, bank erase, (multi) word/byte write or
block lock-bit configuration. STS High Z indicates
that the WSM is ready for a new command, block
erase is suspended and (multi) word/byte write are

VOLTAGE

2.7 V

2.7 V, 3.3 V, 5 V

3.3 V

3.3 V, 5 V

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