P
RODUCT
S
PECIFICATION
Integrated Circuits Group
LH28F800BGHB-TTLZK
Flash Memory
8Mbit (512Kbitx16)
(Model Number: LHF80BZK)
Spec. Issue Date: July 28, 2004
Spec No: EL167189
LHF80BZK
Rev. 1.1
Handle this document carefully for it contains material protected by international copyright law.
Any reproduction, full or in part, of this material is prohibited without the express written
permission of the company.
When using the products covered herein, please observe the conditions written herein and the
precautions outlined in the following paragraphs. In no event shall the company be liable for any
damages resulting from failure to strictly adhere to these conditions and precautions.
(1) The products covered herein are designed and manufactured for the following application
areas. When using the products covered herein for the equipment listed in Paragraph (2),
even for the following application areas, be sure to observe the precautions given in
Paragraph (2). Never use the products for the equipment listed in Paragraph (3).
Office electronics
Instrumentation and measuring equipment
Machine tools
Audiovisual equipment
Home appliance
Communication equipment other than for trunk lines
(2) Those contemplating using the products covered herein for the following equipment which
demands high reliability, should first contact a sales representative of the company and then
accept responsibility for incorporating into the design fail-safe operation, redundancy, and
other appropriate measures for ensuring reliability and safety of the equipment and the
overall system.
Control and safety devices for airplanes, trains, automobiles, and other
transportation equipment
Mainframe computers
Traffic control systems
Gas leak detectors and automatic cutoff devices
Rescue and security equipment
Other safety devices and safety equipment, etc.
(3) Do not use the products covered herein for the following equipment which demands
extremely high performance in terms of functionality, reliability, or accuracy.
Aerospace equipment
Communications equipment for trunk lines
Control equipment for the nuclear power industry
Medical equipment related to life support, etc.
(4) Please direct all queries and comments regarding the interpretation of the above three
Paragraphs to a sales representative of the company.
Please direct all queries regarding the products covered herein to a sales representative of the
company.
LHF80BZK
1
Rev. 1.1
CONTENTS
PAGE
1 INTRODUCTION.............................................................. 3
1.1 Features ........................................................................ 3
1.2 Product Overview......................................................... 3
2 PRINCIPLES OF OPERATION........................................ 6
2.1 Data Protection ............................................................. 7
3 BUS OPERATION ............................................................ 7
3.1 Read.............................................................................. 7
3.2 Output Disable.............................................................. 7
3.3 Standby......................................................................... 7
3.4 Deep Power-Down ....................................................... 7
3.5 Read Identifier Codes Operation .................................. 8
3.6 Write............................................................................. 8
4 COMMAND DEFINITIONS............................................. 8
4.1 Read Array Command................................................ 11
4.2 Read Identifier Codes Command ............................... 11
4.3 Read Status Register Command ................................. 11
4.4 Clear Status Register Command................................. 11
4.5 Block Erase Command ............................................... 11
4.6 Word Write Command ............................................... 12
4.7 Block Erase Suspend Command ................................ 12
4.8 Word Write Suspend Command................................. 13
4.9 Considerations of Suspend ......................................... 13
4.10 Block Locking .......................................................... 13
4.10.1 V
PP
=V
IL
for Complete Protection ...................... 13
4.10.2 WP#=V
IL
for Block Locking.............................. 13
4.10.3 WP#=V
IH
for Block Unlocking.......................... 13
PAGE
5 DESIGN CONSIDERATIONS ...................................... 19
5.1 Three-Line Output Control ....................................... 19
5.2 Power Supply Decoupling ........................................ 19
5.3 V
PP
Trace on Printed Circuit Boards ........................ 19
5.4 V
CC
, V
PP
, RP# Transitions ....................................... 19
5.5 Power-Up/Down Protection...................................... 20
5.6 Power Dissipation ..................................................... 20
6 ELECTRICAL SPECIFICATIONS ............................... 21
6.1 Absolute Maximum Ratings ..................................... 21
6.2 Operating Conditions ................................................ 21
6.2.1 Capacitance ......................................................... 21
6.2.2 AC Input/Output Test Conditions ....................... 22
6.2.3 DC Characteristics .............................................. 23
6.2.4 AC Characteristics - Read-Only Operations ....... 25
6.2.5 AC Characteristics - Write Operations ............... 27
6.2.6 Alternative CE#-Controlled Writes..................... 29
6.2.7 Reset Operations ................................................. 31
6.2.8 Block Erase and Word Write Performance ......... 32
7 PACKAGE AND PACKING SPECIFICATIONS......... 33
LHF80BZK
2
Rev. 1.1
LH28F800BGHB-TTLZK
8M-BIT (512Kbit 16)
Smart3 Flash MEMORY
Smart3 Technology
2.7V-3.6V V
CC
2.7V-3.6V or 11.4V-12.6V V
PP
16bit I/O Interface
High-Performance Access Time
90ns(2.7V-3.6V)
Operating Temperature
-40C to +85C
Optimized Array Blocking Architecture
Two 4K-word Boot Blocks
Six 4K-word Parameter Blocks
Fifteen 32K-word Main Blocks
Top Boot Location
Extended Cycling Capability
100,000 Block Erase Cycles
Enhanced Automated Suspend Options
Word Write Suspend to Read
Block Erase Suspend to Word Write
Block Erase Suspend to Read
Enhanced Data Protection Features
Absolute Protection with V
PP
=GND
Block Erase and Word Write Lockout
during Power Transitions
Boot Blocks Protection with WP#=V
IL
Automated Word Write and Block Erase
Command User Interface
Status Register
Low Power Management
Deep Power-Down Mode
Automatic Power Savings Mode Decreases
I
CC
in Static Mode
SRAM-Compatible Write Interface
Chip Size Packaging
0.75mm pitch 48-Ball CSP
ETOX
TM*
Nonvolatile Flash Technology
CMOS Process (P-type silicon substrate)
Not designed or rated as radiation hardened
SHARP's LH28F800BGHB-TTLZK Flash memory with Smart3 technology is a high-density, low-cost, nonvolatile,
read/write storage solution for a wide range of applications. LH28F800BGHB-TTLZK can operate at V
CC
=2.7V-3.6V and
V
PP
=2.7V-3.6V. Its low voltage operation capability realize battery life and suits for cellular phone application.
Its Boot, Parameter and Main-blocked architecture, flexible voltage and extended cycling provide for highly flexible
component suitable for portable terminals and personal computers. Its enhanced suspend capabilities provide for an ideal
solution for code + data storage applications. For secure code storage applications, such as networking, where code is either
directly executed out of flash or downloaded to DRAM, the LH28F800BGHB-TTLZK offers two levels of protection:
absolute protection with V
PP
at GND, selective hardware boot block locking. These alternatives give designers ultimate
control of their code security needs.
The LH28F800BGHB-TTLZK is manufactured on SHARP's 0.35m ETOX
TM*
process technology. It come in chip size
package: the 0.75mm pitch
48-ball CSP ideal for board constrained applications.
*ETOX is a trademark of Intel Corporation.
LHF80BZK
3
Rev. 1.1
1 INTRODUCTION
This datasheet contains LH28F800BGHB-TTLZK
specifications. Section 1 provides a flash memory
overview. Sections 2, 3, 4 and 5 describe the memory
organization and functionality. Section 6 covers electrical
specifications.
1.1 Features
Key enhancements of LH28F800BGHB-TTLZK Smart3
Flash memory are:
Smart3 Technology
Enhanced Suspend Capabilities
Boot Block Architecture
Please note following important differences:
V
PPLK
has been lowered to 1.5V to support 2.7V-3.6V
block erase and word write operations. The V
PP
voltage transitions to GND is recommended for
designs that switch V
PP
off during read operation.
To take advantage of Smart3 technology, allow V
CC
and V
PP
connection to 2.7V-3.6V.
1.2 Product Overview
The LH28F800BGHB-TTLZK is a high-performance 8M-
bit Smart3 Flash memory organized as 512K-word of 16
bits. The 512K-word of data is arranged in two 4K-word
boot blocks, six 4K-word parameter blocks and fifteen
32K-word main blocks which are individually erasable in-
system. The memory map is shown in Figure 3.
Smart3 technology provides a choice of V
CC
and V
PP
combinations, as shown in Table 1, to meet system
performance and power expectations. V
PP
at 2.7V-3.6V
eliminates the need for a separate 12V converter, while
V
PP
=12V maximizes block erase and word write
performance. In addition to flexible erase and program
voltages, the dedicated V
PP
pin gives complete data
protection when V
PP
V
PPLK
.
Table 1. V
CC
and V
PP
Voltage Combinations Offered by
Smart3 Technology
V
CC
Voltage
V
PP
Voltage
2.7V-3.6V
2.7V-3.6V, 11.4V-12.6V
Internal V
CC
and V
PP
detection Circuitry automatically
configures the device for optimized read and write
operations.
A Command User Interface (CUI) serves as the interface
between the system processor and internal operation of the
device. A valid command sequence written to the CUI
initiates device automation. An internal Write State
Machine (WSM) automatically executes the algorithms
and timings necessary for block erase and word write
operations.
A block erase operation erases one of the device's 32K-
word blocks typically within 0.51s (2.7V-3.6V V
CC
,
11.4V-12.6V V
PP
), 4K-word blocks typically within 0.31s
(2.7V-3.6V V
CC
, 11.4V-12.6V V
PP
) independent of other
blocks. Each block can be independently erased 100,000
times. Block erase suspend mode allows system software
to suspend block erase to read or write data from any other
block.
Writing memory data is performed in word increments of
the device's 32K-word blocks typically within 12.6s
(2.7V-3.6V V
CC
, 11.4V-12.6V V
PP
), 4K-word blocks
typically within 24.5s (2.7V-3.6V V
CC
, 11.4V-12.6V
V
PP
). Word write suspend mode enables the system to
read data or execute code from any other flash memory
array location.
The boot blocks can be locked for the WP# pin. Block
erase or word write for boot block must not be carried out
by WP# to Low and RP# to V
IH
.
The status register indicates when the WSM's block erase
or word write operation is finished.
The access time is 90ns (t
AVQV
) over the extended
temperature range (-40C to +85C) and V
CC
supply
voltage range of 2.7V-3.6V.
The Automatic Power Savings (APS) feature substantially
reduces active current when the device is in static mode
(addresses not switching). In APS mode, the typical I
CCR
current is 3mA at 2.7V V
CC
.
When CE# and RP# pins are at V
CC
, the I
CC
CMOS
standby mode is enabled. When the RP# pin is at GND,
deep power-down mode is enabled which minimizes
power consumption and provides write protection during
reset. A reset time (t
PHQV
) is required from RP# switching
high until outputs are valid. Likewise, the device has a
wake time (t
PHEL
) from RP#-high until writes to the CUI
are recognized. With RP# at GND, the WSM is reset and
the status register is cleared.
The device is available in 0.75mm pitch 48-ball CSP
(Chip Size Package). Pinout is shown in Figure 2.
Input
Buffer
Buffer
Output
Multiplexer
I/O
Command
User
V
CC
CE#
RP#
OE#
Identifier
Register
Status
Register
Data
Register
Data
Comparator
Y-Gating
Y
Decoder
Decoder
X
Address
Latch
Address
Counter
Write
Machine
Program/Erase
Voltage
V
PP
V
CC
GND
A
0
-A
18
DQ
0
-DQ
15
Input
Buffer
Logic
State
Boot Block 0
Boot Block 1
Parameter Block 0
Parameter Block 5
Parameter Block 4
Parameter Block 3
Parameter Block 2
Parameter Block 1
Main Block 0
Main Block 1
Main Block 13
Main Block 14
15
32K-Word
WP#
WE#
Output
Interface
Switch
Main blocks
0.75mm pitch
48-BALL CSP
PINOUT
8mm x 8mm
TOP VIEW
8
7
6
5
4
3
2
1
F
E
D
C
B
A
A
5
A
8
A
11
V
PP
A
12
A
15
A
18
A
6
A
9
RP#
NC
CE#
A
14
A
17
A
4
A
7
A
10
NC
A
13
A
16
A
3
A
0
DQ
2
DQ
6
A
1
DQ
1
GND
NC
DQ
4
DQ
7
OE#
A
2
DQ
0
DQ
3
GND
V
CC
DQ
5
WE#
WP#
DQ
8
DQ
9
DQ
10
DQ
11
DQ
12
DQ
13
DQ
14
DQ
15
NC
LHF80BZK
4
Rev. 1.1
Figure 1. Block Diagram
Figure 2. 0.75mm pitch CSP 48-Ball Pinout
NOTE: NC balls at C4 and C5 are internally connected.
LHF80BZK
5
Rev. 1.1
Table 2. Pin Descriptions
Symbol
Type
Name and Function
A
0
-A
18
INPUT
ADDRESS INPUTS: Addresses are internally latched during a write cycle.
A
0
-A
10
: Row Address. Selects 1 of 2048 word lines.
A
11
-A
14
: Column Address. Selects 1 of 16 bit lines.
A
15
-A
18
: Main Block Address. (Boot and Parameter block Addresses are A
12
-A
18
.)
DQ
0
-DQ
15
INPUT/
OUTPUT
DATA INPUT/OUTPUTS: Inputs data and commands during CUI write cycles; outputs data
during memory array, status register and identifier code read cycles. Data pins float to high-
impedance when the chip is deselected or outputs are disabled. Data is internally latched during a
write cycle.
CE#
INPUT
CHIP ENABLE: Activates the device's control logic, input buffers, decoders and sense amplifiers.
CE#-high deselects the device and reduces power consumption to standby levels.
RP#
INPUT
RESET/DEEP POWER-DOWN: Puts the device in deep power-down mode and resets internal
automation. RP#-high enables normal operation. When driven low, RP# inhibits write operations
which provides data protection during power transitions. Exit from deep power-down sets the
device to read array mode. With RP#=V
HH
, block erase or word write can operate to all blocks
without WP# state. Block erase or word write with V
IH
<RP#<V
HH
produce spurious results and
should not be attempted.
OE#
INPUT
OUTPUT ENABLE: Gates the device's outputs during a read cycle.
WE#
INPUT
WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are latched on
the rising edge of the WE# pulse.
WP#
INPUT
WRITE PROTECT: Master control for boot blocks locking. When V
IL
, locked boot blocks cannot
be erased and programmed.
V
PP
SUPPLY
BLOCK ERASE AND WORD WRITE POWER SUPPLY: For erasing array blocks or writing
words. With V
PP
V
PPLK
, memory contents cannot be altered. Block erase and word write with an
invalid V
PP
(see DC Characteristics) produce spurious results and should not be attempted.
V
CC
SUPPLY
DEVICE POWER SUPPLY: Do not float any power pins. With V
CC
V
LKO
, all write attempts to
the flash memory are inhibited. Device operations at invalid V
CC
voltage (see DC Characteristics)
produce spurious results and should not be attempted.
GND
SUPPLY
GROUND: Do not float any ground pins.
NC
NO CONNECT: Lead is not internally connected to die; it may be driven or floated.
7FFFF
7F000
7EFFF
7E000
7DFFF
7D000
7CFFF
7C000
7BFFF
7B000
7AFFF
7A000
79FFF
79000
78FFF
78000
77FFF
70000
6FFFF
68000
67FFF
60000
5FFFF
58000
57FFF
50000
4FFFF
48000
47FFF
40000
4K-word Parameter Block 3
4K-word Parameter Block 2
4K-word Parameter Block 1
4K-word Parameter Block 0
32K-word Main Block 0
32K-word Main Block 1
32K-word Main Block 2
32K-word Main Block 3
32K-word Main Block 5
32K-word Main Block 6
4K-word Parameter Block 5
4K-word Parameter Block 4
Top Boot
4K-word Boot Block 0
4K-word Boot Block 1
32K-word Main Block 4
37FFF
30000
2FFFF
28000
27FFF
20000
1FFFF
18000
17FFF
10000
0FFFF
08000
07FFF
00000
32K-word Main Block 8
32K-word Main Block 9
32K-word Main Block 10
32K-word Main Block 11
32K-word Main Block 13
32K-word Main Block 14
32K-word Main Block 12
3FFFF
38000
32K-word Main Block 7
[
A
18
-A
0
]
LHF80BZK
6
Rev. 1.1
2 PRINCIPLES OF OPERATION
The LH28F800BGHB-TTLZK Smart3 Flash memory
includes an on-chip WSM to manage block erase and word
write functions. It allows for: 100% TTL-level control
inputs, fixed power supplies during block erasure and
word write, and minimal processor overhead with RAM-
like interface timings.
After initial device power-up or return from deep power-
down mode (see Bus Operations), the device defaults to
read array mode. Manipulation of external memory control
pins allow array read, standby and output disable
operations.
Status register and identifier codes can be accessed
through the CUI independent of the V
PP
voltage. High
voltage on V
PP
enables successful block erasure and word
writing. All functions associated with altering memory
contents-block erase, word write, status and identifier
codes-are accessed via the CUI and verified through the
status register.
Commands are written using standard microprocessor
write timings. The CUI contents serve as input to the
WSM, which controls the block erase and word write. The
internal algorithms are regulated by the WSM, including
pulse repetition, internal verification and margining of
data. Addresses and data are internally latch during write
cycles. Writing the appropriate command outputs array
data, accesses the identifier codes or outputs status register
data.
Interface software that initiates and polls progress of block
erase and word write can be stored in any block. This code
is copied to and executed from system RAM during flash
memory updates. After successful completion, reads are
again possible via the Read Array command. Block erase
suspend allows system software to suspend a block erase
to read/write data from/to blocks other than that which is
suspend. Word write suspend allows system software to
suspend a word write to read data from any other flash
memory array location.
Figure 3. Memory Map
LHF80BZK
7
Rev. 1.1
2.1 Data Protection
Depending on the application, the system designer may
choose to make the V
PP
power supply switchable
(available only when memory block erases or word writes
are required) or hardwired to V
PPH1/2
. The device
accommodates either design practice and encourages
optimization of the processor-memory interface.
When V
PP
V
PPLK
, memory contents cannot be altered.
The CUI, with two-step block erase or word write
command sequences, provides protection from unwanted
operations even when high voltage is applied to V
PP
. All
write functions are disabled when V
CC
is below the write
lockout voltage V
LKO
or when RP# is at V
IL
. The device's
boot blocks locking capability for WP# provides
additional protection from inadvertent code or data
alteration by block erase and word write operations. Refer
to Table 6 for write protection alternatives.
3 BUS OPERATION
The local CPU reads and writes flash memory in-system.
All bus cycles to or from the flash memory conform to
standard microprocessor bus cycles.
3.1 Read
Information can be read from any block, identifier codes
or status register independent of the V
PP
voltage. RP# can
be at either V
IH
or V
HH
.
The first task is to write the appropriate read mode
command (Read Array, Read Identifier Codes or Read
Status Register) to the CUI. Upon initial device power-up
or after exit from deep power-down mode, the device
automatically resets to read array mode. Five control pins
dictate the data flow in and out of the component: CE#,
OE#, WE#, RP# and WP#. CE# and OE# must be driven
active to obtain data at the outputs. CE# is the device
selection control, and when active enables the selected
memory device. OE# is the data output (DQ
0
-DQ
15
)
control and when active drives the selected memory data
onto the I/O bus. WE# must be at V
IH
and RP# must be at
V
IH
or V
HH
. Figure 11 illustrates read cycle.
3.2 Output Disable
With OE# at a logic-high level (V
IH
), the device outputs
are disabled. Output pins (DQ
0
-DQ
15
) are placed in a
high-impedance state.
3.3 Standby
CE# at a logic-high level (V
IH
) places the device in
standby mode which substantially reduces device power
consumption. DQ
0
-DQ
15
outputs are placed in a high-
impedance state independent of OE#. If deselected during
block erase or word write, the device continues
functioning, and consuming active power until the
operation completes.
3.4 Deep Power-Down
RP# at V
IL
initiates the deep power-down mode.
In read modes, RP#-low deselects the memory, places
output drivers in a high-impedance state and turns off all
internal circuits. RP# must be held low for a minimum of
100ns. Time t
PHQV
is required after return from power-
down until initial memory access outputs are valid. After
this wake-up interval, normal operation is restored. The
CUI is reset to read array mode and status register is set to
80H.
During block erase or word write modes, RP#-low will
abort the operation. Memory contents being altered are no
longer valid; the data may be partially erased or written.
Time t
PHWL
is required after RP# goes to logic-high (V
IH
)
before another command can be written.
As with any automated device, it is important to assert
RP# during system reset. When the system comes out of
reset, it expects to read from the flash memory. Automated
flash memories provide status information when accessed
during block erase or word write modes. If a CPU reset
occurs with no flash memory reset, proper CPU
initialization may not occur because the flash memory
may be providing status information instead of array data.
SHARP's flash memories allow proper CPU initialization
following a system reset through the use of the RP# input.
In this application, RP# is controlled by the same RESET#
signal that resets the system CPU.
Device Code
Manufacturer Code
7FFFF
00001
00000
Reserved for Future Implementation
00002
[A
18
-A
0
]
LHF80BZK
8
Rev. 1.1
3.5 Read Identifier Codes Operation
The read identifier codes operation outputs the
manufacturer code and device code (see Figure 4). Using
the manufacturer and device codes, the system CPU can
automatically match the device with its proper algorithms.
Figure 4. Device Identifier Code Memory Map
3.6 Write
Writing commands to the CUI enable reading of device
data and identifier codes. They also control inspection and
clearing of the status register. When V
CC
=2.7V-3.6V and
V
PP
=V
PPH1/2
, the CUI additionally controls block erasure
and word write.
The Block Erase command requires appropriate command
data and an address within the block to be erased. The
Word Write command requires the command and address
of the location to be written.
The CUI does not occupy an addressable memory
location. It is written when WE# and CE# are active. The
address and data needed to execute a command are latched
on the rising edge of WE# or CE# (whichever goes high
first). Standard microprocessor write timings are used.
Figures 12 and 13 illustrate WE# and CE# controlled write
operations.
4 COMMAND DEFINITIONS
When the V
PP
voltage
V
PPLK
, Read operations from the
status register, identifier codes, or blocks are enabled.
Placing V
PPH1/2
on V
PP
enables successful block erase
and word write operations.
Device operations are selected by writing specific
commands into the CUI. Table 4 defines these commands.
LHF80BZK
9
Rev. 1.1
Table 3. Bus Operations
(1,2)
Mode
Notes
RP#
CE#
OE#
WE#
Address
V
PP
DQ
0-15
Read
7
V
IH
or
V
HH
V
IL
V
IL
V
IH
X
X
D
OUT
Output Disable
V
IH
or
V
HH
V
IL
V
IH
V
IH
X
X
High Z
Standby
8
V
IH
or
V
HH
V
IH
X
X
X
X
High Z
Deep Power-Down
3,8
V
IL
X
X
X
X
X
High Z
Read Identifier Codes
7
V
IH
or
V
HH
V
IL
V
IL
V
IH
See
Figure 4
X
Note 4
Write
5,6,7
V
IH
or
V
HH
V
IL
V
IH
V
IL
X
X
D
IN
NOTES:
1. Refer to DC Characteristics. When V
PP
V
PPLK
, memory contents can be read, but not altered.
2. X can be V
IL
or V
IH
for control pins and addresses, and V
PPLK
or V
PPH1/2
for V
PP
. See DC Characteristics for V
PPLK
and
V
PPH1/2
voltages.
3. RP# at GND0.2V ensures the lowest deep power-down current.
4. See Section 4.2 for read identifier code data.
5. Command writes involving block erase or word write are reliably executed when V
PP
=V
PPH1/2
and V
CC
=2.7V-3.6V.
Block erase or word write with V
IH
<RP#<V
HH
produce spurious results and should not be attempted.
6. Refer to Table 4 for valid D
IN
during a write operation.
7. Never hold OE# low and WE# low at the same timing.
8. WP# set to V
IL
or V
IH
.
LHF80BZK
10
Rev. 1.1
Table 4. Command Definitions
(7)
Bus Cycles
First Bus Cycle
Second Bus Cycle
Command
Req'd.
Notes
Oper
(1)
Addr
(2)
Data
(3)
Oper
(1)
Addr
(2)
Data
(3)
Read Array/Reset
1
Write
X
FFH
Read Identifier Codes
2
4
Write
X
90H
Read
IA
ID
Read Status Register
2
Write
X
70H
Read
X
SRD
Clear Status Register
1
Write
X
50H
Block Erase
2
5
Write
BA
20H
Write
BA
D0H
Word Write
2
5,6
Write
WA
40H or
10H
Write
WA
WD
Block Erase and Word Write
Suspend
1
5
Write
X
B0H
Block Erase and Word Write
Resume
1
5
Write
X
D0H
NOTES:
1. BUS operations are defined in Table 3
2. X=Any valid address within the device.
IA=Identifier Code Address: see Figure 4.
BA=Address within the block being erased. The each block can select by the address pin A
18
through A
12
combination.
WA=Address of memory location to be written.
3. SRD=Data read from status register. See Table 7 for a description of the status register bits.
WD=Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high first).
ID=Data read from identifier codes.
4. Following the Read Identifier Codes command, read operations access manufacturer and device codes. See Section 4.2 for
read identifier code data.
5. If the block is boot block, WP# must be at V
IH
or RP# must be at V
HH
to enable block erase or word write operations.
Attempts to issue a block erase or word write to a boot block while WP# is V
IH
or RP# is V
IH
.
6. Either 40H or 10H are recognized by the WSM as the word write setup.
7. Commands other than those shown above are reserved by SHARP for future device implementations and should not be
used.
LHF80BZK
11
Rev. 1.1
4.1 Read Array Command
Upon initial device power-up and after exit from deep
power-down mode, the device defaults to read array mode.
This operation is also initiated by writing the Read Array
command. The device remains enabled for reads until
another command is written. Once the internal WSM has
started a block erase or word write, the device will not
recognize the Read Array command until the WSM
completes its operation unless the WSM is suspended via
an Erase Suspend or Word Write Suspend command. The
Read Array command functions independently of the V
PP
voltage and RP# can be V
IH
or V
HH
.
4.2 Read Identifier Codes Command
The identifier code operation is initiated by writing the
Read Identifier Codes command. Following the command
write, read cycles from addresses shown in Figure 4
retrieve the manufacturer and device codes (see Table 5
for identifier code values). To terminate the operation,
write another valid command. Like the Read Array
command, the Read Identifier Codes command functions
independently of the V
PP
voltage and RP# can be V
IH
or
V
HH
. Following the Read Identifier Codes command, the
following information can be read:
Table 5. Identifier Codes
Code
Address
[A
18
-A
0
]
Data
[DQ
15
-DQ
0
]
Manufacture Code
00000H
00B0H
Device Code
00001H
0060H
4.3 Read Status Register Command
The status register may be read to determine when a block
erase or word write is complete and whether the operation
completed successfully. It may be read at any time by
writing the Read Status Register command. After writing
this command, all subsequent read operations output data
from the status register until another valid command is
written. The status register contents are latched on the
falling edge of OE# or CE#, whichever occurs. OE# or
CE# must toggle to V
IH
before further reads to update the
status register latch. The Read Status Register command
functions independently of the V
PP
voltage. RP# can be
V
IH
or V
HH
.
4.4 Clear Status Register Command
Status register bits SR.5, SR.4, SR.3 or SR.1 are set to
"1"s by the WSM and can only be reset by the Clear Status
Register command. These bits indicate various failure
conditions (see Table 7). By allowing system software to
reset these bits, several operations (such as cumulatively
erasing multiple blocks or writing several words in
sequence) may be performed. The status register may be
polled to determine if an error occurred during the
sequence.
To clear the status register, the Clear Status Register
command (50H) is written. It functions independently of
the applied V
PP
Voltage. RP# can be V
IH
or V
HH
. This
command is not functional during block erase or word
write suspend modes.
4.5 Block Erase Command
Erase is executed one block at a time and initiated by a
two-cycle command. A block erase setup is first written,
followed by an block erase confirm. This command
sequence requires appropriate sequencing and an address
within the block to be erased (erase changes all block data
to FFFFH). Block preconditioning, erase, and verify are
handled internally by the WSM (invisible to the system).
After the two-cycle block erase sequence is written, the
device automatically outputs status register data when read
(see Figure 5). The CPU can detect block erase completion
by analyzing the status register bit SR.7.
When the block erase is complete, status register bit SR.5
should be checked. If a block erase error is detected, the
status register should be cleared before system software
attempts corrective actions. The CUI remains in read
status register mode until a new command is issued.
This two-step command sequence of set-up followed by
execution ensures that block contents are not accidentally
erased. An invalid Block Erase command sequence will
result in both status register bits SR.4 and SR.5 being set
to "1". Also, reliable block erasure can only occur when
V
CC
=2.7V-3.6V and V
PP
=V
PPH1/2
. In the absence of this
high voltage, block contents are protected against erasure.
If block erase is attempted while V
PP
V
PPLK
, SR.3 and
SR.5 will be set to "1". Successful block erase for boot
blocks requires that the corresponding if set, that
WP#=V
IH
or RP#=V
HH
. If block erase is attempted to
boot block when the corresponding WP#=V
IL
or
RP#=V
IH
, SR.1 and SR.5 will be set to "1". Block erase
operations with V
IH
<RP#<V
HH
produce spurious results
and should not be attempted.
LHF80BZK
12
Rev. 1.1
4.6 Word Write Command
Word write is executed by a two-cycle command
sequence. Word write setup (standard 40H or alternate
10H) is written, followed by a second write that specifies
the address and data (latched on the rising edge of WE#).
The WSM then takes over, controlling the word write and
write verify algorithms internally. After the word write
sequence is written, the device automatically outputs
status register data when read (see Figure 6). The CPU can
detect the completion of the word write event by analyzing
the status register bit SR.7.
When word write is complete, status register bit SR.4
should be checked. If word write error is detected, the
status register should be cleared. The internal WSM verify
only detects errors for "1"s that do not successfully write
to "0"s. The CUI remains in read status register mode until
it receives another command.
Reliable word writes can only occur when
V
CC
=2.7V-3.6V and V
PP
=V
PPH1/2
. In the absence of this
high voltage, memory contents are protected against word
writes. If word write is attempted while V
PP
V
PPLK
,
status register bits SR.3 and SR.4 will be set to "1".
Successful word write for boot blocks requires that the
corresponding if set, that WP#=V
IH
or RP#=V
HH
. If word
write is attempted to boot block when the corresponding
WP#=V
IL
or RP#=V
IH
, SR.1 and SR.4 will be set to "1".
Word write operations with V
IH
<RP#<V
HH
produce
spurious results and should not be attempted.
4.7 Block Erase Suspend Command
The Block Erase Suspend command allows block-erase
interruption to read or word write data in another block of
memory. Once the block-erase process starts, writing the
Block Erase Suspend command requests that the WSM
suspend the block erase sequence at a predetermined point
in the algorithm. The device outputs status register data
when read after the Block Erase Suspend command is
written. Polling status register bits SR.7 and SR.6 can
determine when the block erase operation has been
suspended (both will be set to "1"). Specification section
6.2.8 defines the block erase suspend latency.
At this point, a Read Array command can be written to
read data from blocks other than that which is suspended.
A Word Write command sequence can also be issued
during erase suspend to program data in other blocks.
Using the Word Write Suspend command (see Section
4.8), a word write operation can also be suspended. During
a word write operation with block erase suspended, status
register bit SR.7 will return to "0". However, SR.6 will
remain "1" to indicate block erase suspend status.
The only other valid commands while block erase is
suspended are Read Status Register and Block Erase
Resume. After a Block Erase Resume command is written
to the flash memory, the WSM will continue the block
erase process. Status register bits SR.6 and SR.7 will
automatically clear. After the Erase Resume command is
written, the device automatically outputs status register
data when read (see Figure 7). V
PP
must remain at
V
PPH1/2
(the same V
PP
level used for block erase) while
block erase is suspended. RP# must also remain at V
IH
or
V
HH
(the same RP# level used for block erase). WP# must
also remain at V
IL
or V
IH
(the same WP# level used for
block erase). Block erase cannot resume until word write
operations initiated during block erase suspend have
completed.
LHF80BZK
13
Rev. 1.1
4.8 Word Write Suspend Command
The Word Write Suspend command allows word write
interruption to read data in other flash memory locations.
Once the word write process starts, writing the Word
Write Suspend command requests that the WSM suspend
the word write sequence at a predetermined point in the
algorithm. The device continues to output status register
data when read after the Word Write Suspend command is
written. Polling status register bits SR.7 and SR.2 can
determine when the word write operation has been
suspended (both will be set to "1"). Specification section
6.2.8 defines the word write suspend latency.
At this point, a Read Array command can be written to
read data from locations other than that which is
suspended. The only other valid commands while word
write is suspended are Read Status Register and Word
Write Resume. After Word Write Resume command is
written to the flash memory, the WSM will continue the
word write process. Status register bits SR.2 and SR.7 will
automatically clear. After the Word Write Resume
command is written, the device automatically outputs
status register data when read (see Figure 8). V
PP
must
remain at V
PPH1/2
(the same V
PP
level used for word
write) while in word write suspend mode. RP# must also
remain at V
IH
or V
HH
(the same RP# level used for word
write). WP# must also remain at V
IL
or V
IH
(the same
WP# level used for word write).
4.9 Considerations of Suspend
After the suspend command write to the CUI, read status
register command has to write to CUI, then status register
bit SR.6 or SR.2 should be checked for places the device
in suspend mode.
4.10 Block Locking
This Boot Block Flash memory architecture features two
hardware-lockable boot blocks so that the kernel code for
the system can be kept secure while other blocks are
programmed or erased as necessary.
4.10.1 V
PP
=V
IL
for Complete Protection
The V
PP
programming voltage can be held low for
complete write protection of all blocks in the flash device.
4.10.2 WP#=V
IL
for Block Locking
The lockable blocks are locked when WP#=V
IL
; any
program or erase operation to a locked block will result in
an error, which will be reflected in the status register. For
top configuration, the top two boot blocks are lockable.
For the bottom configuration, the bottom two boot blocks
are lockable. Unlocked blocks can be programmed or
erased normally (Unless V
PP
is below V
PPLK
).
4.10.3 WP#=V
IH
for Block Unlocking
WP#=V
IH
unlocks all lockable blocks.
These blocks can now be programmed or erased.
WP# controls 2 boot blocks locking and V
PP
provides
protection against spurious writes. Table 6 defines the
write protection methods.
Table 6. Write Protection Alternatives
Operation
V
PP
RP#
WP#
Effect
V
IL
X
X
All Blocks Locked.
Block Erase
V
IL
X
All Blocks Locked.
or
>V
PPLK
V
HH
X
All Blocks Unlocked.
Word Write
V
IH
V
IL
2 Boot Blocks Locked.
V
IH
All Blocks Unlocked.
LHF80BZK
14
Rev. 1.1
Table 7. Status Register Definition
WSMS
ESS
ES
WWS
VPPS
WWSS
DPS
R
7
6
5
4
3
2
1
0
SR.7 = WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
SR.6 = ERASE SUSPEND STATUS (ESS)
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
SR.5 = ERASE STATUS (ES)
1 = Error in Block Erasure
0 = Successful Block Erase
SR.4 = WORD WRITE STATUS (WWS)
1 = Error in Word Write
0 = Successful Word Write
SR.3 = V
PP
STATUS (VPPS)
1 = V
PP
Low Detect, Operation Abort
0 = V
PP
OK
SR.2 = WORD WRITE SUSPEND STATUS (WWSS)
1 = Word Write Suspended
0 = Word Write in Progress/Completed
SR.1 = DEVICE PROTECT STATUS (DPS)
1 = WP# or RP# Lock Detected, Operation Abort
0 = Unlock
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
NOTES:
Check SR.7 to determine block erase or word write
completion. SR.6-0 are invalid while SR.7="0".
If both SR.5 and SR.4 are "1"s after a block erase attempt,
an improper command sequence was entered.
SR.3 does not provide a continuous indication of V
PP
level.
The WSM interrogates and indicates the V
PP
level only after
Block Erase or Word Write command sequences. SR.3 is not
guaranteed to reports accurate feedback only when
V
PP
V
PPH1/2
.
The WSM interrogates the WP# and RP# only after Block
Erase or Word Write command sequences. It informs the
system, depending on the attempted operation, if the WP# is
not V
IH,
RP# is not V
HH
.
SR.0 is reserved for future use and should be masked out
when polling the status register.
Bus
Operation
Command
Comments
Write
Write
Read
Standby
Erase Setup
Erase
Confirm
Data=20H
Addr=Within Block to be Erased
Data=D0H
Addr=Within Block to be Erased
Status Register Data
Check SR.7
1=WSM Ready
0=WSM Busy
Repeat for subsequent block erasures.
Full status check can be done after each block erase or after a sequence of
block erasures.
Write FFH after the last operation to place device in read array mode.
Bus
Operation
Command
Comments
Standby
1=V
PP
Error Detect
1=Device Protect Detect
Check SR.4,5
SR.5,SR.4,SR.3 and SR.1 are only cleared by the Clear Status
Register Command in cases where multiple blocks are erased
before full status is checked.
If error is detected, clear the Status Register before attempting
retry or other error recovery.
Check SR.5
1=Block Erase Error
Standby
Standby
Standby
Check SR.3
Check SR.1
Both 1=Command Sequence Error
Start
Write 20H,
Block Address
Write D0H,
Block Address
Read Status
Register
SR.7=
0
1
Suspend
Block Erase
No
Yes
Suspend Block
Erase Loop
Full Status
Check if Desired
Block Erase
Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data(See Above)
SR.3=
1
0
V
PP
Range Error
Device Protect Error
Command Sequence
Error
Block Erase Error
SR.1=
1
0
SR.4,5=
SR.5=
1
1
0
0
Block Erase Successful
LHF80BZK
15
Rev. 1.1
Figure 5. Automated Block Erase Flowchart
Bus
Operation
Command
Comments
Write
Write
Read
Standby
Setup Word Write
Word Write
Data=40H or 10H
Addr=Location to Be Written
Data=Data to Be Written
Addr=Location to Be Written
Status Register Data
Check SR.7
1=WSM Ready
0=WSM Busy
Repeat for subsequent word writes.
SR full status check can be done after each Word write, or after a sequence of
Word writes.
Write FFH after the last Word write operation to place device in
read array mode.
Bus
Operation
Command
Comments
1=V
PP
Error Detect
1=Device Protect Detect
SR.4,SR.3 and SR.1 are only cleared by the Clear Status Register
command in cases where multiple locations are written before
full status is checked.
If error is detected, clear the Status Register before attempting
retry or other error recovery.
Check SR.4
1=Data Write Error
Standby
Standby
Standby
Check SR.3
Check SR.1
Start
Write 40H or 10H,
Address
Write Word
Data and Address
Read
Status Register
SR.7=
0
1
Suspend
Word Write
No
Yes
Suspend Word
Write Loop
Full Status
Check if Desired
Word Write
Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data(See Above)
SR.3=
1
0
V
PP
Range Error
Device Protect Error
Word Write Error
SR.1=
1
0
SR.4=
1
0
Word Write
Successful
LHF80BZK
16
Rev. 1.1
Figure 6. Automated Word Write Flowchart
Start
Write B0H
Word Write Loop
Read
Status Register
SR.7=
0
1
No
Bus
Operation
Command
Comments
Write
Read
Standby
Data=B0H
Addr=X
Data=D0H
Status Register Data
Check SR.7
1=WSM Ready
0=WSM Busy
Yes
SR.6=
0
1
Read Array Data
Done?
Block Erase Resumed
Read Array Data
Block Erase Completed
Write FFH
Write D0H
Standby
Write
Erase
Suspend
Erase
Resume
Addr=X
Addr=X
Check SR.6
1=Block Erase Suspended
0=Block Erase Completed
Read
Word Write
Read or
Word
Write?
LHF80BZK
17
Rev. 1.1
Figure 7. Block Erase Suspend/Resume Flowchart
Start
Write B0H
Write FFH
Read
Status Register
SR.7=
0
1
No
Bus
Operation
Command
Comments
Write
Read
Standby
Data=B0H
Addr=X
Data=D0H
Status Register Data
Check SR.7
1=WSM Ready
0=WSM Busy
Yes
SR.2=
0
1
Read Array Data
Done
Reading
Word Write
Resumed
Read Array Data
Write FFH
Write D0H
Standby
Write
Write
Read
Word Write
Suspend
Read Array
Word Write
Resume
Addr=X
Addr=X
Data=FFH
Addr=X
Check SR.2
1=Word Write Suspended
0=Word Write Completed
Read Array locations other
than that being written.
Word Write
Completed
LHF80BZK
18
Rev. 1.1
Figure 8. Word Write Suspend/Resume Flowchart
LHF80BZK
19
Rev. 1.1
5 DESIGN CONSIDERATIONS
5.1 Three-Line Output Control
The device will often be used in large memory arrays.
SHARP provides three control inputs to accommodate
multiple memory connections. Three-line control provides
for:
a. Lowest possible memory power dissipation.
b. Complete assurance that data bus contention will not
occur.
To use these control inputs efficiently, an address decoder
should enable CE# while OE# should be connected to all
memory devices and the system's READ# control line.
This assures that only selected memory devices have
active outputs while deselected memory devices are in
standby mode. RP# should be connected to the system
POWERGOOD signal to prevent unintended writes during
system power transitions. POWERGOOD should also
toggle during system reset.
5.2 Power Supply Decoupling
Flash memory power switching characteristics require
careful device decoupling. System designers are interested
in three supply current issues; standby current levels,
active current levels and transient peaks produced by
falling and rising edges of CE# and OE#. Transient current
magnitudes depend on the device outputs' capacitive and
inductive loading. Two-line control and proper decoupling
capacitor selection will suppress transient voltage peaks.
Each device should have a 0.1F ceramic capacitor
connected between its V
CC
and GND and between its V
PP
and GND. These high-frequency, low inductance
capacitors should be placed as close as possible to package
leads. Additionally, for every eight devices, a 4.7F
electrolytic capacitor should be placed at the array's power
supply connection between V
CC
and GND. The bulk
capacitor will overcome voltage slumps caused by PC
board trace inductance.
5.3 V
PP
Trace on Printed Circuit Boards
Updating flash memories that reside in the target system
requires that the printed circuit board designer pay
attention to the V
PP
Power supply trace. The V
PP
pin
supplies the memory cell current for word writing and
block erasing. Use similar trace widths and layout
considerations given to the V
CC
power bus. Adequate V
PP
supply traces and decoupling will decrease V
PP
voltage
spikes and overshoots.
5.4 V
CC
, V
PP
, RP# Transitions
Block erase and word write are not guaranteed if V
PP
falls
outside of a valid V
PPH1/2
range, V
CC
falls outside of a
valid 2.7V-3.6V range, or RP#
V
IH
or V
HH
. If V
PP
error
is detected, status register bit SR.3 is set to "1" along with
SR.4 or SR.5, depending on the attempted operation. If
RP# transitions to V
IL
during block erase or word write,
the reset operation will execute. Then, the operation will
abort and the device will enter deep power-down. The
aborted operation may leave data partially altered.
Therefore, the command sequence must be repeated after
normal operation is restored. Device power-off or RP#
transitions to V
IL
clear the status register.
The CUI latches commands issued by system software and
is not altered by V
PP
or CE# transitions or WSM actions.
Its state is read array mode upon power-up, after exit from
deep power-down or after V
CC
transitions below V
LKO
.
After block erase or word write, even after V
PP
transitions
down to V
PPLK
, the CUI must be placed in read array
mode via the Read Array command if subsequent access
to the memory array is desired.
LHF80BZK
20
Rev. 1.1
5.5 Power-Up/Down Protection
The device is designed to offer protection against
accidental block erasure or word writing during power
transitions. Upon power-up, the device is indifferent as to
which power supply (V
PP
or V
CC
) powers-up first.
Internal circuitry resets the CUI to read array mode at
power-up.
A system designer must guard against spurious writes for
V
CC
voltages above V
LKO
when V
PP
is active. Since both
WE# and CE# must be low for a command write, driving
either to V
IH
will inhibit writes. The CUI's two-step
command sequence architecture provides added level of
protection against data alteration.
WP# provide additional protection from inadvertent code
or data alteration. The device is disabled while RP#=V
IL
regardless of its control inputs state.
5.6 Power Dissipation
When designing portable systems, designers must consider
battery power consumption not only during device
operation, but also for data retention during system idle
time. Flash memory's nonvolatility increases usable
battery life because data is retained when system power is
removed.
In addition, deep power-down mode ensures extremely
low power consumption even when system power is
applied. For example, portable computing products and
other power sensitive applications that use an array of
devices for solid-state storage can consume negligible
power by lowering RP# to V
IL
standby or sleep modes. If
access is again needed, the devices can be read following
the t
PHQV
and t
PHWL
wake-up cycles required after RP# is
first raised to V
IH
. See AC Characteristics- Read Only
and Write Operations and Figures 11, 12 and 13 for more
information.
LHF80BZK
21
Rev. 1.1
6 ELECTRICAL SPECIFICATIONS
6.1 Absolute Maximum Ratings*
Operating Temperature
During Read, Block Erase and
Word Write ......................................-40C to +85C
(1)
Temperature under Bias ...................... -40C to +85C
Storage Temperature ................................ -65C to +125C
Voltage On Any Pin
(except V
CC
, V
PP
, and RP#) ............ -0.5V to +7.0V
(2)
V
CC
Supply Voltage................................ -0.2V to +7.0V
(2)
V
PP
Update Voltage during Block
Erase and Word Write.................. -0.2V to +14.0V
(2,3)
RP# Voltage ........................................ -0.5V to +14.0V
(2,3)
Output Short Circuit Current................................100mA
(4)
*WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage. These
are stress ratings only. Operation beyond the "Operating
Conditions" is not recommended and extended exposure
beyond the "Operating Conditions" may affect device
reliability.
NOTES:
1. Operating temperature is for extended temperature
product defined by this specification.
2. All specified voltages are with respect to GND.
Minimum DC voltage is -0.5V on input/output pins
and -0.2V on V
CC
and V
PP
pins. During transitions,
this level may undershoot to -2.0V for periods <20ns.
Maximum DC voltage on input/output pins and V
CC
is
V
CC
+0.5V which, during transitions, may overshoot to
V
CC
+2.0V for periods <20ns.
3. Maximum DC voltage on V
PP
and RP# may overshoot
to +14.0V for periods <20ns.
4. Output shorted for no more than one second. No more
than one output shorted at a time.
6.2 Operating Conditions
Temperature and V
CC
Operating Conditions
Symbol
Parameter
Min.
Max.
Unit
Test Condition
T
A
Operating Temperature
-40
+85
C
Ambient Temperature
V
CC
V
CC
Supply Voltage (2.7V-3.6V)
2.7
3.6
V
6.2.1 CAPACITANCE
(1)
T
A
=+25C, f=1MHz
Symbol
Parameter
Typ.
Max.
Unit
Condition
C
IN
Input Capacitance
7
10
pF
V
IN
=0.0V
C
OUT
Output Capacitance
9
12
pF
V
OUT
=0.0V
NOTE:
1. Sampled, not 100% tested.
AC test inputs are driven at 2.7V for a Logic "1" and 0.0V for a Logic "0." Input timing begins, and output timing ends, at 1.35V.
Input rise and fall times (10% to 90%) <10 ns.
2.7
0.0
INPUT
TEST POINTS
OUTPUT
1.35
1.35
1.3V
1N914
DEVICE
UNDER
TEST
C
L
OUT
C
L
Includes Jig
R
L
=3.3k
Capacitance
LHF80BZK
22
Rev. 1.1
6.2.2 AC INPUT/OUTPUT TEST CONDITIONS
Figure 9. Transient Input/Output Reference Waveform for V
CC
=2.7V-3.6V
Test Configuration Capacitance Loading Value
Test Configuration
C
L
(pF)
V
CC
=2.7V-3.6V
30
Figure 10. Transient Equivalent Testing Load
Circuit
LHF80BZK
23
Rev. 1.1
6.2.3 DC CHARACTERISTICS
DC Characteristics
V
CC
=2.7V-3.6V
Test
Sym.
Parameter
Notes
Typ.
Max.
Unit
Conditions
I
LI
Input Load Current
1
0.5
A
V
CC
=V
CC
Max.
V
IN
=V
CC
or GND
I
LO
Output Leakage Current
1
0.5
A
V
CC
=V
CC
Max.
V
OUT
=V
CC
or GND
I
CCS
V
CC
Standby Current
1,5,9
25
50
A
CMOS Inputs
V
CC
=V
CC
Max.
CE#=RP#=V
CC
0.2V
1,5
0.2
2
mA
TTL Inputs
V
CC
=V
CC
Max.
CE#=RP#=V
IH
I
CCD
V
CC
Deep Power-Down Current
1,9
5
20
A
RP#=GND0.2V
I
CCR
V
CC
Read Current
1,4,5
15
25
mA
CMOS Inputs
V
CC
=V
CC
Max., CE#=GND
f=5MHz, I
OUT
=0mA
30
mA
TTL Inputs
V
CC
=V
CC
Max., CE#=GND
f=5MHz, I
OUT
=0mA
I
CCW
V
CC
Word Write Current
1,6
5
17
mA
V
PP
=2.7V-3.6V
5
12
mA
V
PP
=11.4V-12.6V
I
CCE
V
CC
Block Erase Current
1,6
4
17
mA
V
PP
=2.7V-3.6V
4
12
mA
V
PP
=11.4V-12.6V
I
CCWS
I
CCES
V
CC
Word Write or Block Erase
Suspend Current
1,2
1
6
mA
CE#=V
IH
I
PPS
V
PP
Standby or Read Current
1
2
15
A
V
PP
V
CC
I
PPR
10
200
A
V
PP
>V
CC
I
PPD
V
PP
Deep Power-Down Current
1
0.1
5
A
RP#=GND0.2V
I
PPW
V
PP
Word Write Current
1,6
12
40
mA
V
PP
=2.7V-3.6V
30
mA
V
PP
=11.4V-12.6V
I
PPE
V
PP
Block Erase Current
1,6
8
25
mA
V
PP
=2.7V-3.6V
20
mA
V
PP
=11.4V-12.6V
I
PPWS
I
PPES
V
PP
Word Write or Block Erase
Suspend Current
1
10
200
A
V
PP
=V
PPH1/2
LHF80BZK
24
Rev. 1.1
DC Characteristics (Continued)
V
CC
=2.7V-3.6V
Sym.
Parameter
Notes
Min.
Max.
Unit
Test Conditions
V
IL
Input Low Voltage
6
-0.5
0.8
V
V
IH
Input High Voltage
6
2.0
V
CC
+0.5
V
V
OL
Output Low Voltage
6
0.4
V
V
CC
=V
CC
Min.
I
OL
=2.0mA
V
OH1
Output High Voltage
(TTL)
6
2.4
V
V
CC
=V
CC
Min.
I
OH
=-1.5mA
V
OH2
Output High Voltage
(CMOS)
6
0.85
V
CC
V
V
CC
=V
CC
Min.
I
OH
=-2.0mA
V
CC
-0.4
V
V
CC
=V
CC
Min.
I
OH
=-100A
V
PPLK
V
PP
Lockout Voltage during Normal
Operations
3,6
1.5
V
V
PPH1
V
PP
Voltage during Word Write or
Block Erase Operations
2.7
3.6
V
V
PPH2
V
PP
Voltage during Word Write or
Block Erase Operations
11.4
12.6
V
V
LKO
V
CC
Lockout Voltage
2.0
V
V
HH
RP# Unlock Voltage
7,8
11.4
12.6
V
Unavailable WP#
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at nominal V
CC
voltage and T
A
=+25C.
2. I
CCWS
and I
CCES
are specified with the device de-selected. If read or word written while in erase suspend mode, the
device's current draw is the sum of I
CCWS
or I
CCES
and I
CCR
or I
CCW
, respectively.
3. Block erases and word writes are inhibited when V
PP
V
PPLK
, and not guaranteed in the range between V
PPLK
(max.) and
V
PPH1
(min.), between V
PPH1
(max.) and V
PPH2
(min.) and above V
PPH2
(max.).
4. Automatic Power Savings (APS) reduces typical I
CCR
to 3mA at 2.7V V
CC
in static operation.
5. CMOS inputs are either V
CC
0.2V or GND0.2V. TTL inputs are either V
IL
or V
IH
.
6. Sampled, not 100% tested.
7. Boot block erases and word writes are inhibited when the corresponding RP#=V
IH
and WP#=V
IL
. Block erase and word
write operations are not guaranteed with V
IH
<RP#<V
HH
and should not be attempted.
8. RP# connection to a V
HH
supply is allowed for a maximum cumulative period of 80 hours.
9. WP# input level is V
CC
0.2V or GND0.2V.
LHF80BZK
25
Rev. 1.1
6.2.4 AC CHARACTERISTICS - READ-ONLY OPERATIONS
(1)
V
CC
=2.7V-3.6V, T
A
=-40C to +85C
Sym.
Parameter
Notes
Min.
Max.
Unit
t
AVAV
Read Cycle Time
90
ns
t
AVQV
Address to Output Delay
90
ns
t
ELQV
CE# to Output Delay
2
90
ns
t
PHQV
RP# High to Output Delay
600
ns
t
GLQV
OE# to Output Delay
2
50
ns
t
ELQX
CE# to Output in Low Z
3
0
ns
t
EHQZ
CE# High to Output in High Z
3
55
ns
t
GLQX
OE# to Output in Low Z
3
0
ns
t
GHQZ
OE# High to Output in High Z
3
20
ns
t
OH
Output Hold from Address, CE# or OE# Change, Whichever
Occurs First
3
0
ns
NOTES:
1. See AC Input/Output Reference Waveform for maximum allowable input slew rate.
2. OE# may be delayed up to t
ELQV
-t
GLQV
after the falling edge of CE# without impact on t
ELQV
.
3. Sampled, not 100% tested.
ADDRESSES(A)
CE#(E)
OE#(G)
WE#(W)
DATA(D/Q)
RP#(P)
V
CC
Standby
Device
Address Selection
Data Valid
Address Stable
t
AVAV
t
EHQZ
t
GHQZ
HIGH Z
Valid Output
t
GLQV
t
ELQV
t
GLQX
t
ELQX
t
AVQV
t
PHQV
HIGH Z
t
OH
V
IL
V
OH
V
OL
V
IH
V
IH
V
IH
V
IH
V
IH
V
IL
V
IL
V
IL
V
IL
(DQ
0
-DQ
15
)
LHF80BZK
26
Rev. 1.1
Figure 11. AC Waveform for Read Operations
LHF80BZK
27
Rev. 1.1
6.2.5 AC CHARACTERISTICS - WRITE OPERATIONS
(1)
V
CC
=2.7V-3.6V, T
A
=-40C to +85C
Sym.
Parameter
Notes
Min.
Max.
Unit
t
AVAV
Write Cycle Time
90
ns
t
PHWL
RP# High Recovery to WE# Going Low
2
1
s
t
ELWL
CE# Setup to WE# Going Low
10
ns
t
WLWH
WE# Pulse Width
50
ns
t
PHHWH
RP# V
HH
Setup to WE# Going High
2
100
ns
t
SHWH
WP# V
IH
Setup to WE# Going High
2
100
ns
t
VPWH
V
PP
Setup to WE# Going High
2
100
ns
t
AVWH
Address Setup to WE# Going High
3
50
ns
t
DVWH
Data Setup to WE# Going High
3
50
ns
t
WHDX
Data Hold from WE# High
0
ns
t
WHAX
Address Hold from WE# High
0
ns
t
WHEH
CE# Hold from WE# High
0
ns
t
WHWL
WE# Pulse Width High
20
ns
t
WHGL
Write Recovery before Read
0
ns
t
QVVL
V
PP
Hold from Valid SRD
2,4
0
ns
t
QVPH
RP# V
HH
Hold from Valid SRD
2,4
0
ns
t
QVSL
WP# V
IH
Hold from Valid SRD
2,4
0
ns
NOTES:
1. Read timing characteristics during block erase and word write operations are the same as during read-only operations.
Refer to AC Characteristics for read-only operations.
2. Sampled, not 100% tested.
3. Refer to Table 4 for valid A
IN
and D
IN
for block erase or word write.
4. V
PP
should be held at V
PPH1/2
(and if necessary RP# should be held at V
HH
) until determination of block erase or word
write success (SR.1/3/4/5=0).
V
IL
V
IH
V
IH
V
IH
V
IH
V
IL
V
IL
V
IL
V
IL
V
IH
V
HH
V
IL
V
PPLK
V
PPH2,1
V
IH
V
IL
NOTES:
1. V
CC
power-up and standby.
2. Write block erase or word write setup.
3. Write block erase confirm or valid address and data.
4. Automated erase or program delay.
5. Read status register data.
6. Write Read Array command.
ADDRESSES(A)
CE#(E)
OE#(G)
WE#(W)
DATA(D/Q)
RP#(P)
V
PP
(V)
}
}
}
}
}
}
1
2
3
4
5
6
A
IN
A
IN
t
AVAV
t
AVWH
t
WHAX
t
ELWL
t
WHEH
t
WHGL
t
WHWL
t
WHQV1,2
t
WLWH
t
DVWH
t
WHDX
Valid
SRD
t
PHWL
t
VPWH
t
QVVL
D
IN
D
IN
High Z
D
IN
WP#(S)
V
IH
V
IL
t
PHHWH
t
QVPH
t
SHWH
t
QVSL
LHF80BZK
28
Rev. 1.1
Figure 12. AC Waveform for WE#-Controlled Write Operations
LHF80BZK
29
Rev. 1.1
6.2.6 ALTERNATIVE CE#-CONTROLLED WRITES
(1)
V
CC
=2.7V-3.6V, T
A
=-40C to +85C
Sym.
Parameter
Notes
Min.
Max.
Unit
t
AVAV
Write Cycle Time
90
ns
t
PHEL
RP# High Recovery to CE# Going Low
2
1
s
t
WLEL
WE# Setup to CE# Going Low
0
ns
t
ELEH
CE# Pulse Width
50
ns
t
PHHEH
RP# V
HH
Setup to CE# Going High
2
100
ns
t
SHEH
WP# V
IH
Setup to CE# Going High
2
100
ns
t
VPEH
V
PP
Setup to CE# Going High
2
100
ns
t
AVEH
Address Setup to CE# Going High
3
50
ns
t
DVEH
Data Setup to CE# Going High
3
50
ns
t
EHDX
Data Hold from CE# High
0
ns
t
EHAX
Address Hold from CE# High
0
ns
t
EHWH
WE# Hold from CE# High
0
ns
t
EHEL
CE# Pulse Width High
20
ns
t
EHGL
Write Recovery before Read
0
ns
t
QVVL
V
PP
Hold from Valid SRD
2,4
0
ns
t
QVPH
RP# V
HH
Hold from Valid SRD
2,4
0
ns
t
QVSL
WP# V
IH
Hold from Valid SRD
2,4
0
ns
NOTES:
1. In systems where CE# defines the write pulse width (within a longer WE# timing waveform), all setup, hold, and inactive
WE# times should be measured relative to the CE# waveform.
2. Sampled, not 100% tested.
3. Refer to Table 4 for valid A
IN
and D
IN
for block erase or word write.
4. V
PP
should be held at V
PPH1/2
(and if necessary RP# should be held at V
HH
) until determination of block erase or word
write success (SR.1/3/4/5=0).
V
IL
V
IH
V
IH
V
IL
V
IL
V
IH
V
HH
V
IL
V
PPLK
V
PPH2,1
V
IH
V
IL
NOTES:
1. V
CC
power-up and standby.
2. Write block erase or word write setup.
3. Write block erase confirm or valid address and data.
4. Automated erase or program delay.
5. Read status register data.
6. Write Read Array command.
ADDRESSES(A)
OE#(G)
DATA(D/Q)
RP#(P)
V
PP
(V)
A
IN
A
IN
t
AVAV
t
AVEH
t
EHAX
t
EHGL
t
EHDX
Valid
SRD
t
PHEL
t
VPEH
t
QVVL
D
IN
D
IN
High Z
D
IN
}
}
}
}
}
}
1
2
3
4
5
6
V
IH
V
IL
WP#(S)
t
PHHEH
t
QVPH
t
SHEH
t
QVSL
V
IH
V
IL
WE#(W)
t
WLEL
t
EHWH
t
EHQV1,2
t
DVEH
V
IH
V
IL
CE#(E)
t
EHEL
t
ELEH
LHF80BZK
30
Rev. 1.1
Figure 13. AC Waveform for CE#-Controlled Write Operations
V
IL
t
PLPH
V
IH
RP#(P)
V
IL
t
2VPH
(B)RP# rising Timing
V
IH
2.7V
V
IL
RP#(P)
V
CC
(A)Reset Timing
Device
State
Device Busy
(Reset Operation)
Device
Busy
Device
Ready
Reset Operating Time
LHF80BZK
31
Rev. 1.1
6.2.7 RESET OPERATIONS
Figure 14. AC Waveform for Reset Operation
Reset AC Specifications
V
CC
=2.7V-3.6V
Sym.
Parameter
Notes
Min.
Max.
Unit
t
PLPH
RP# Pulse Low Time
(If RP# is tied to V
CC
, this specification is not applicable)
100
ns
Reset Operating Time
(During block erase or word write operation is executing)
1,2
22
s
t
2VPH
V
CC
2.7V to RP# High
3
100
ns
NOTES:
1. If RP# is asserted while a block erase or word write operation is not executing, the reset will complete within 100ns.
2. A reset time, t
PHQV
, is required from the later of reset operation is finished or RP# going high until outputs are valid.
3. When the device power-up, holding RP# low minimum 100ns is required after V
CC
has been in predefined range and also
has been in stable there.
LHF80BZK
32
Rev. 1.1
6.2.8 BLOCK ERASE AND WORD WRITE PERFORMANCE
(3)
V
CC
=2.7V-3.6V, T
A
=-40C to +85C
V
PP
=2.7V-3.6V
V
PP
=11.4V-12.6V
Sym.
Parameter
Notes
Typ.
(1)
Max.
Typ.
(1)
Max.
Unit
t
WHQV1
Word Write Time
32K word Block
2
44.6
12.6
s
t
EHQV1
4K word Block
2
45.9
24.5
s
Block Write Time
32K word Block
2
1.46
0.42
s
4K word Block
2
0.19
0.11
s
t
WHQV2
Block Erase Time
32K word Block
2
1.14
0.51
s
t
EHQV2
4K word Block
2
0.38
0.31
s
Word Write Suspend Latency Time to Read
7
8
6
7
s
Erase Suspend Latency Time to Read
18
22
11
14
s
NOTES:
1. Typical values measured at T
A
=+25C and nominal voltages. Subject to change based on device characterization.
2. Excludes system-level overhead.
3. Sampled but not 100% tested.
Rev. 1.10
i
A-1 RECOMMENDED OPERATING CONDITIONS
A-1.1 At Device Power-Up
AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up.
If the timing in the figure is ignored, the device may not operate correctly.
Figure A-1. AC Timing at Device Power-Up
For the AC specifications t
VR
, t
R
, t
F
in the figure, refer to the next page. See the "ELECTRICAL SPECIFICATIONS"
described in specifications for the supply voltage range, the operating temperature and the AC specifications not shown in
the next page.
t
2VPH
*1
V
CC
GND
V
CC
(min)
RP#
V
IL
V
IH
(P)
t
PHQV
V
CCW
*2
GND
V
CCWH1/2
(V)
CE#
V
IL
V
IH
(E)
WE#
V
IL
V
IH
(W)
OE#
V
IL
V
IH
(G)
WP#
V
IL
V
IH
(S)
V
OH
V
OL
(D/Q)
DATA
High Z
Valid
Output
t
VR
t
F
t
R
t
ELQV
t
F
t
GLQV
(A)
ADDRESS
Valid
(RST#)
(V
PP
)
t
R
or
t
F
Address
V
IL
V
IH
t
AVQV
*1 t
5VPH
for the device in 5V operations.
t
R
or
t
F
t
R
t
R
*2 To prevent the unwanted writes, system designers should consider the V
CCW
(V
PP
) switch, which connects V
CCW
(V
PP
)
to GND during read operations and V
CCWH1/2
(V
PPH1/2
) during write or erase operations.
(V
PPH1/2
)
See the application note AP-007-SW-E for details.
Rev. 1.10
ii
A-1.1.1 Rise and Fall Time
NOTES:
1. Sampled, not 100% tested.
2. This specification is applied for not only the device power-up but also the normal operations.
t
R
(Max.) and t
F
(Max.) for RP# (RST#) are 100
s/V.
Symbol
Parameter
Notes
Min.
Max.
Unit
t
VR
V
CC
Rise Time
1
0.5
30000
s/V
t
R
Input Signal Rise Time
1, 2
1
s/V
t
F
Input Signal Fall Time
1, 2
1
s/V
Rev. 1.10
iii
A-1.2 Glitch Noises
Do not input the glitch noises which are below V
IH
(Min.) or above V
IL
(Max.) on address, data, reset, and control signals,
as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a).
Figure A-2. Waveform for Glitch Noises
See the "DC CHARACTERISTICS" described in specifications for V
IH
(Min.) and V
IL
(Max.).
(a) Acceptable Glitch Noises
Input Signal
V
IH
(Min.)
Input Signal
V
IH
(Min.)
Input Signal
V
IL
(Max.)
Input Signal
V
IL
(Max.)
(b)
NOT
Acceptable Glitch Noises
Rev. 1.10
iv
A-2 RELATED DOCUMENT INFORMATION
(1)
NOTE:
1. International customers should contact their local SHARP or distribution sales office.
Document No.
Document Name
AP-001-SD-E
Flash Memory Family Software Drivers
AP-006-PT-E
Data Protection Method of SHARP Flash Memory
AP-007-SW-E
RP#, V
PP
Electric Potential Switching Circuit
SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
Suggested applications (if any) are for standard use; See Important Restrictions for limitations on special applications. See Limited
Warranty for SHARP's product warranty. The Limited Warranty is in lieu, and exclusive of, all other warranties, express or implied.
ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND
FITNESS FOR A PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED. In no event will SHARP be liable, or in any way responsible,
for any incidental or consequential economic or property damage.
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Phone: (1) 360-834-2500
Fax: (1) 360-834-8903
Fast Info: (1) 800-833-9437
www.sharpsma.com
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Division of Sharp Electronics (Europe) GmbH
Sonninstrasse 3
20097 Hamburg, Germany
Phone: (49) 40-2376-2286
Fax: (49) 40-2376-2232
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Electronic Components & Devices
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Osaka 545-8522, Japan
Phone: (81) 6-6621-1221
Fax: (81) 6117-725300/6117-725301
www.sharp-world.com
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SINGAPORE
KOREA
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(Taiwan) Corporation
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Taipei, Taiwan, Republic of China
Phone: (886) 2-2577-7341
Fax: (886) 2-2577-7326/2-2577-7328
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438A, Alexandra Road, #05-01/02
Alexandra Technopark,
Singapore 119967
Phone: (65) 271-3566
Fax: (65) 271-3855
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(Korea) Corporation
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Phone: (82) 2-711-5813 ~ 8
Fax: (82) 2-711-5819
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