LH5164AZ8
CMOS 64K (8K
8) Static RAM
FEATURES
8,192
8 bit organization
Access time:
200 ns (V
CC
= 3.0 V MAX.)
Power consumption:
Operating:
60 mW (MAX.) @ 3 V
Standby (to 60
C):
3
W (MAX.) @ 3 V
Data hold
0.6
A (V
CC
= 3 V, T
A
= 60
C)
Operating voltage range:
3.0 V to 3.6 V
Wide operating temperature range:
-30 to 60
C
Fully-static operation
TTL compatible I/O
Three-state outputs
Package: 28-pin, 450-mil SOP
DESCRIPTION
The LH5164AZ8 is a static RAM organized as
8,192
8 bits. It is fabricated using silicon-gate CMOS
process technology.
PIN CONNECTIONS
2
3
4
5
6
9
10
7
8
A
12
11
1
28
27
26
25
22
21
24
23
20
19
V
CC
28-PIN SOP
12
13
14
17
16
18
15
NC
A
6
A
7
A
1
CE
1
I/O
8
CE
2
WE
A
9
A
8
GND
A
11
OE
I/O
7
5164AZ8-1
A
0
TOP VIEW
A
5
A
3
A
4
A
2
I/O
1
I/O
2
I/O
3
A
10
I/O
6
I/O
5
I/O
4
Figure 1. Pin Connections for SOP Package
1
I/O
8
A
5
A
4
A
3
5164AZ8-2
MEMORY
ARRAY
(256 x 256)
A
6
WE
A
7
A
12
A
8
ROW SELECT
COLUMN I/O
CIRCUITS
COLUMN SELECT
V
CC
GND
OE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
I/O
2
I/O
1
A
2
A
1
A
0
A
11
A
9
CE
1
CE
2
INPUT
DATA
CONTROL
A
10
8
23
9
10
21
22
20
26
27
11
15
18
13
17
12
16
19
5
6
7
4
3
2
25
24
28
14
ROW ADDRESS
BUFFERS
COLUMN ADDRESS
BUFFERS
Figure 2. LH5164AZ8 Block Diagram
PIN DESCRIPTION
SIGNAL
PIN NAME
A
0
- A
12
Address inputs
CE
1
- CE
2
Chip Enable input
WE
Write Enable input
OE
Output Enable input
SIGNAL
PIN NAME
I/O
1
- I/O
8
Data inputs and outputs
V
CC
Power supply
GND
Ground
NC
Non connection
LH5164AZ8
CMOS 64K (8K
8) Static RAM
2
TRUTH TABLE
CE
1
CE
2
WE
OE
MODE
I/O
1
- I/O
8
SUPPLY CURRENT
NOTE
H
X
X
X
Standby
High-Z
Standby (I
SB
)
1
X
L
X
X
Standby
High-Z
Standby (I
SB
)
1
L
H
L
X
Write
D
IN
Operating (I
CC
)
1
L
H
H
L
Read
D
OUT
Operating (I
CC
)
L
H
H
H
Output deselect
High-Z
Operating (I
CC
)
NOTE:
1.
X = H or L
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
UNIT
NOTE
Supply voltage
V
CC
-0.3 to +7.0
V
1
Input voltage
V
IN
-0.3 to V
CC
+ 0.3
V
1
Operating temperature
Topr
-30 to +60
C
Storage temperature
Tstg
-65 to +150
C
NOTE:
1.
The maximum applicable voltage on any pin with respect to GND.
RECOMMENDED OPERATING CONDITIONS (T
A
= -30 to +60
C)
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
Supply voltage
V
CC
3.0
3.6
V
Input voltage
(V
CC
= 3.0 to 3.6 V)
V
IH
V
CC
- 0.5
V
CC
+ 0.3
V
V
IL
-0.3
0.2
V
DC CHARACTERISTICS (T
A
= -30 to +60
C, V
CC
= 3.0 to 3.6 V)
ADD TABLE
NOTE:
1.
CE
2
should be
V
CC
- 0.2 V or
0.2 V.
CMOS 64K (8K
8) Static RAM
LH5164AZ8
3
AC CHARACTERISTICS
(1) READ CYCLE (T
A
= -30 to +60
C, V
CC
= 3.0 to 3.6 V)
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
Read cycle
t
RC
200
ns
Address access time
t
AA
200
ns
Chip enable
access time
(CE
1
)
t
ACE1
200
ns
(CE
2
)
t
ACE2
200
ns
Output enable access time
t
OE
150
ns
Output hold time
t
OH
10
ns
Chip enable to
output in Low-Z
(CE
1
)
t
LZ1
20
ns
(CE
2
)
t
LZ2
20
ns
Output enable to output in Low-Z
t
OLZ
10
ns
Chip enable to
output in High-Z
(CE
1
)
t
HZ1
0
60
ns
(CE
2
)
t
HZ2
0
60
ns
Output disable to output in High-Z
t
OHZ
0
40
ns
(2) WRITE CYCLE (T
A
= -30 to +60
C, V
CC
= 3.0 to 3.6 V)
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
Write cycle time
t
WC
200
ns
Chip enable to end of write
t
CW
180
ns
Address valid to end of write
t
AW
180
ns
Address setup time
t
AS
0
ns
Write pulse width
t
WP
150
ns
Write recovery time
t
WR
0
ns
Data valid to end of write
t
DW
100
ns
Data hold time
t
DH
0
ns
Output active from end of write
t
OW
20
ns
WE to output in High-Z
t
WZ
0
60
ns
OE to output in High-Z
t
OHZ
0
40
ns
AC TEST CONDITIONS
PARAMETER
MODE
Input voltage amplitude
0 to V
CC
Input rise/fall time
10 ns
Timing reference level
1.5 V
Output load conditions
No load
CAPACITANCE (T
A
= 25
C, f = 1 MHz)
PARAMETER
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Input capacitance
C
IN
V
IN
= 0 V
7
pF
Input/output capacitance
C
I/O
V
I/O
= 0 V
10
pF
NOTE:
This parameter is sampled and not production tested.
LH5164AZ8
CMOS 64K (8K
8) Static RAM
4
DATA RETENTION CHARACTERISTICS (T
A
= -30 to +60
C)
PARAMETER
SYMBOL
CONDITIONS
MIN.
MAX.
UNIT
NOTE
Data retention supply voltage
V
CCDR
CE
2
0.2 V or
CE
1
V
CCDR
0.2 V
2.0
5.5
V
1
Data retention supply current
I
CCDR
V
CCDR
= 3.0 V,
CE
2
0.2 V or
CE
1
V
CCDR
0.2 V
T
A
= 25
C
0.2
A
T
A
= 60
C
0.6
1
Chip disable to data retention
t
CDR
0
ns
Recovery time
t
R
t
RC
ns
2
NOTES:
1.
CE
2
should be
V
CCDR
- 0.2 V or
0.2 V.
2.
t
RC
= Read cycle time
t
LZ1
t
ACE1
t
OHZ
D
OUT
DATA VALID
OE
t
RC
5164AZ8-3
t
OLZ
NOTE: WE is "HIGH" level during the read cycle.
t
ACE2
t
AA
t
LZ2
CE
1
CE
2
t
HZ1
t
OE
t
OH
t
HZ2
ADDRESS
Figure 3. Read Cycle
CMOS 64K (8K
8) Static RAM
LH5164AZ8
5
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