LH52D1000
CMOS 1M (128K
8) Static Ram
FEATURES
Access time: 85 ns (MAX.),
100 ns (MAX.)
Current consumption:
Operating: 40 mA (MAX.)
6 mA (MAX.) (t
RC
, t
WC
= 1
s)
Standby: 45
A (MAX.)
Data Retention:
1.0
A (MAX. V
CCDR
= 3 V, t
A
= 25
C)
Single power supply: 2.7 V to 3.6 V
Operating temperature: -40
C to +85
C
Fully-static operation
Three-state output
Not designed or rated as radiation
hardened
Packages:
32-pin 8
20 mm
2
TSOP
32-pin 8
13.4 mm
2
STSOP
N-type bulk silicon
DESCRIPTION
The LH52D1000 is a static RAM organized as
131,072
8 bits which provides low-power standby
mode. It is fabricated using silicon-gate CMOS process
technology.
PIN CONNECTIONS
2
3
4
5
6
9
10
7
8
11
1
32
31
30
29
26
25
28
27
24
23
OE
A
10
32-PIN TSOP
32-PIN STSOP
12
15
13
14
21
20
22
19
18
A
8
CE
2
A
15
I/O
3
I/O
2
A
1
I/O
8
CE
1
I/O
6
I/O
7
I/O
5
I/O
4
A
0
A
2
52D1000S-1
V
CC
A
16
A
12
A
7
A
6
A
5
16
17
A
4
WE
NC
A
3
GND
TOP VIEW
A
9
A
11
A
13
A
14
I/O
1
Figure 1. Pin Connections for TSOP
and STSOP Packages
1
A
7
A
8
A
9
52D1000S-2
MEMORY
CELL ARRAY
(1024 x 128 x 8)
A
6
15
A
5
A
4
A
3
COLUMN GATE
V
CC
GND
I/O BUFFER
23
27
25 26
8
24
14
13
3
16
17
18
22
21
I/O
1
A
2
A
1
19
20
CE
CONTROL
LOGIC
ADDRESS
BUFFER
OE, WE
CONTROL
LOGIC
WE 5
OE 32
ROW
DECODER
COLUMN
DECODER
A
12
A
13
A
14
A
11
31
A
10
1
12
2
10
1024
4
A
0
7
128
128 x 8
8
29
28
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
I/O
8
11
7
A
15
A
16
CE
1
30
CE
2
6
10
Figure 2. LH52D1000 Block Diagram
PIN DESCRIPTION
SIGNAL
PIN NAME
A
0
A
16
Address inputs
CE
1
Chip enable 1
CE
2
Chip enable 2
WE
Write enable
OE
Output enable
SIGNAL
PIN NAME
I/O
1
I/O
8
Data inputs and outputs
V
CC
Power supply
GND
Ground
NC
No connection
LH52D1000
CMOS 1M (128K
8) Static RAM
2
TRUTH TABLE
CE
1
CE
2
WE
OE
MODE
I/O
1
I/O
8
SUPPLY CURRENT
NOTE
H
Standby
High
impedance
Standby (I
SB
)
1
L
L
H
L
Write
Data input
Active (I
CC
)
1
L
H
H
L
Read
Data output
Active (I
CC
)
L
H
H
H
Output disable
High
impedance
Active (I
CC
)
NOTE:
1.
= Don't care
L = Low
H = High
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
UNIT
NOTE
Supply voltage
V
CC
- 0 . 3 t o + 4 . 6
V
1
Input voltage
V
IN
- 0.3 to V
CC
+ 0.3
V
1, 2
Operating temperature
T
OPR
-40 to +85
C
Storage temperature
T
STG
-55 to +1 50
C
NOTE:
1.
The maximum applicable voltage on any pin with respect to GND.
2.
Undershoot of -3.0 V is allowed width of pulse below 50 ns.
RECOMMENDED DC OPERATING CONDITIONS (T
A
= -40
C to +85
C)
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTE
Supply voltage
V
CC
2.7
3.0
3.6
V
Input voltage
V
IH
2.0
V
CC
+ 0.3
V
V
IL
0.3
0.6
V
1
NOTE:
1.
Undershoot of 3.0 V is allowed width of pulse below 50 ns.
DC ELECTRICAL CHARACTERISTICS (T
A
= -25
C to +85
C, V
CC
= 2.7 V to 3.6 V)
PARAMETER
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Input
leakage
current
I
LI
VIN = 0 to V
CC
1.0
1.0
A
Output
leakage
current
I
LO
CE
1
= V
IH
or CE
2
= V
IL
or
OE = V
IH
or WE = V
IL
V
I/O
= 0 V to V
CC
1.0
1.0
A
Operating
supply
current
I
CC
V
IN
= V
IL
or V
IH,
CE
1
= V
IL
, WE = V
IH
CE
2
= V
IH
, I
I/O
= 0 mA
t
CYCLE
= Min
40
mA
I
CC1
CE
1
= 0.2 V, V
IN
= 0.2 V or V
CC
- 0.2 V
CE
2
, WE = V
CC
- 0.2 V, I
I/O
= 0 mA
t
CYCLE
= 1.0
s
6
Standby
current
I
SB
CE
1
= V
CC
0.2 V or
CE
2
= 0.2 V
45
A
I
SB1
CE
1
= V
IH
or CE
2
= V
IL
2.0
mA
Output
voltage
V
OL
I
OL
= 2.1 mA
0.4
V
V
OH
I
OH
= 0.5 mA
V
CC
- 0.5
V
CMOS 1M (128K
8) Static RAM
LH52D1000
3
AC ELECTRICAL CHARACTERISTICS
AC Test Conditions
PARAMETER
MODE
NOTE
Input pulse level
0.4 V to 2.4 V
Input rise and fall time
5 ns
Input and output timing Ref. level
1.5 V
Output load
100 pF + 1TTL
1
NOTE:
1.
Including scope and jig capacitance.
READ CYCLE (T
A
= -40
C to +85
C, V
CC
= 2.7 V to 3.6 V)
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
NOTE
Read cycle time
t
RC
85
ns
Address access time
t
AA
85
ns
CE
1
access time
t
ACE1
85
ns
CE
2
access time
t
ACE2
85
ns
Output enable to output valid
t
OE
45
ns
Output hold from address change
t
OH
10
ns
CE
1
Low to output active
t
LZ1
5
ns
1
CE
2
High to output active
t
LZ2
5
ns
1
OE Low to output active
t
OLZ
0
ns
1
CE
1
High to output in High impedance
t
HZ1
0
35
ns
1
CE
2
Low to output in High impedance
t
HZ2
0
35
ns
1
OE High to output in High impedance
t
OHZ
0
35
ns
1
NOTE:
1.
Active output to High impedance and High impedance to output active tests specified for a
200 mV transition
from steady state levels into the test load.
WRITE CYCLE (T
A
= -40
C to +85
C, V
CC
= 2.7 V to 3.6 V)
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
NOTE
Write cycle time
t
WC
85
ns
CE
1
Low to end of write
t
CW1
75
ns
CE
2
High to end of write
t
CW2
75
ns
Address setup time
t
AS
0
ns
Write pulse width
t
WP
60
ns
Write recovery time
t
WR
0
ns
Input data setup time
t
DW
35
ns
Input data hold time
t
DH
0
ns
WE High to output active
t
OW
0
ns
1
WE Low to output in High impedance
t
WZ
0
ns
1
OE High to output in High impedance
t
OHZ
0
35
ns
1
NOTE:
1.
Active output to High impedance and High impedance to output active tests specified for a
200 mV transition
from steady state levels into the test load.
LH52D1000
CMOS 1M (128K
8) Static RAM
4
DATA RETENTION CHARACTERISTICS (T
A
= -40
C to +85
C)
PARAMETER
SYMBOL
CONDITIONS
MIN.
TYP
MAX.
UNIT
NOTE
Data retention
supply voltage
V
CCDR
CE
2
0.2 V or
CE
1
V
CCDR
0.2 V
2.0
3.6
V
1
Data retention
supply current
I
CCDR
V
CCDR
= 3.0 V
CE
2
0.2 V or
CE
1
V
CCDR
0.2 V
T
A
= 25
C
1.0
A
1
T
A
= 40
C
3.0
35
Chip enable
setup time
t
CDR
0
ms
Chip enable
hold time
t
R
5
ms
NOTE:
1.
CE
2
V
CCDR
0.2 V or CE
2
0.2 V
2.
Typical values at T
A
= 25
C
PIN CAPACITANCE (T
A
= 25
C, f = 1 MHz)
PARAMETER
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNIT
NOTE
Input capacitance
C
IN
V
IN
= 0 V
10
pF
1
I/O capacitance
C
I/O
V
I/O
= 0 V
10
pF
1
NOTE:
1.
This parameter is sampled and not production tested.
CMOS 1M (128K
8) Static RAM
LH52D1000
5
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