LH538700A
CMOS 8M (1M
8) MROM
FEATURES
1,048,576 words
8 bit organization
Access time: 100 ns (MAX.)
Power consumption:
Operating: 550 mW (MAX.)
Standby: 550
W (MAX.)
Static operation
TTL compatible I/O
Three-state outputs
Single +5 V power supply
Packages:
32-pin, 600-mil DIP
32-pin, 525-mil SOP
32-pin, 400-mil TSOP (Type II)
DESCRIPTION
The LH538700A is an 8M-bit mask-programmable
ROM organized as 1,048,576
8 bits. It is fabricated
using silicon-gate CMOS process technology.
PIN CONNECTIONS
538700A-1
TOP VIEW
1
2
3
4
5
6
9
10
A
2
A
5
V
CC
28
27
26
25
24
23
20
17
A
7
A
6
7
8
A
3
A
4
22
21
A
15
A
12
GND
A
13
A
8
A
11
A
10
CE
D
7
D
6
D
3
11
12
13
32
31
30
29
A
14
A
1
14
15
16
19
D
5
18
D
4
D
1
D
2
A
0
D
0
A
9
A
16
OE
32-PIN DIP
32-PIN SOP
A
19
A
18
A
17
Figure 1. Pin Connections for DIP and
SOP Packages
538700A-2
TOP VIEW
2
3
4
5
8
9
A
4
A
7
29
28
27
26
25
24
21
18
A
15
A
12
6
7
23
22
A
14
D
4
10
11
12
31
30
A
2
13
20
19
A
3
32-PIN TSOP (Type II)
14
15
16
17
D
3
32
1
A
16
CE
A
18
A
13
A
9
A
11
OE
A
10
A
8
D
7
D
6
D
5
A
19
A
1
A
0
D
0
D
1
D
2
GND
NOTE: Reverse bend available on request.
A
6
A
5
V
CC
A
17
Figure 2. Pin Connections for TSOP Package
PRELIMINARY
1
538700A-3
A
3
A
2
A
1
A
12
A
11
A
10
A
9
A
8
32
4
25
23
26
6
9
10
11
A
7
A
6
V
CC
A
4
18
19
20
13
21
D
0
MEMORY
MATRIX
(1,048,576 x 8)
SENSE AMPLIFIER
OUTPUT BUFFER
16
5
GND
D
1
D
2
D
3
D
4
D
5
D
6
D
7
17
14
15
8
27
A
5
7
A
13
28
ADDRESS BUFFER
CE
A
0
12
ADDRESS DECODER
COLUMN SELECTOR
CE
BUFFER
OE
BUFFER
A
14
29
A
15
3
22
TIMING
GENERATOR
A
16
2
24
OE
A
17
30
A
18
31
A
19
1
Figure 3. LH538700A Block Diagram
PIN DESCRIPTION
SIGNAL
PIN NAME
A
0
A
19
Address input
D
0
D
7
Data output
CE
Chip enable input
SIGNAL
PIN NAME
OE
Output enable input
V
CC
Power supply (+5 V)
GND
Ground
LH538700A
PRELIMINARY
CMOS 8M MROM
2
TRUTH TABLE
CE
OE
DATA OUTPUT
SUPPLY CURRENT
H
X
High-Z
Standby
L
H
High-Z
Operating
L
L
Output
Operating
NOTE:
X = H or L.
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
UNIT
Supply voltage
V
CC
0.3 to +7.0
V
Input voltage
V
IN
0.3 to V
CC
+0.3
V
Output voltage
V
OUT
0.3 to V
CC
+0.3
V
Operating temperature
Topr
0 to +70
C
Storage temperature
Tstg
65 to +150
C
RECOMMENDED OPERATING CONDI-
TIONS (T
A
= 0
C to +70
C)
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
Supply voltage
V
CC
4.5
5.0
5.5
V
DC CHARACTERISTICS (V
CC
= 5 V
10%, T
A
= 0
C to +70
C)
PARAMETER
SYMBOL
CONDITIONS
MIN.
MAX.
UNIT
NOTE
Input `Low' voltage
V
IL
0.3
0.8
V
Input `High' voltage
V
IH
2.2
V
CC
+ 0.3
V
Output `Low' voltage
V
OL
I
OL
= 2.0 mA
0.4
V
Output `High' voltage
V
OH
I
OH
= 400
A
2.4
V
Input leakage current
| I
LI
|
V
IN
= 0 V to V
CC
10
A
Output leakage current
| I
LO
|
V
OUT
= 0 V to V
CC
10
A
1
Operating current
I
CC1
t
RC
= 100 ns
100
mA
2
I
CC2
t
RC
= 1
s
90
mA
2
Standby current
I
SB1
CE = V
IH
3
mA
I
SB2
CE = V
CC
0.2 V
100
A
Input capacitance
C
IN
f = 1 MHz
T
A
= 25
C
10
pF
Output capacitance
C
OUT
10
pF
NOTES:
1.
CE/OE = V
IH
2.
V
IN
= V
IH
or V
IL
, CE = V
IL
, outputs open
CMOS 8M MROM
PRELIMINARY
LH538700A
3
AC CHARACTERISTICS (V
CC
= 5 V
10%, T
A
= 0
C to +70
C)
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
NOTE
Read cycle time
t
RC
100
ns
Address access time
t
AA
100
ns
Chip enable access time
t
ACE
100
ns
Output enable delay time
t
OE
50
ns
Output hold time
t
OH
5
ns
CE to output in High-Z
t
CHZ
40
ns
1
OE to output in High-Z
t
OHZ
40
ns
1
NOTE:
1.
This is the time required for the output to become high-impedance.
AC TEST CONDITIONS
PARAMETER
RATING
Input voltage amplitude
0.4 V to 2.6 V
Input rise/fall time
10 ns
Input/output reference level
1.5 V
Output load condition
1TTL + 100 pF
CAUTION
To stabilize the power supply, it is recommended that
a high-frequency bypass capacitor be connected be-
tween the V
CC
pin and the GND pin.
t
AA
A
0
- A
19
t
OHZ
t
CHZ
D
0
- D
7
538700A-4
t
RC
t
ACE
CE
t
OH
DATA VALID
(NOTE)
(NOTE)
t
OE
(NOTE)
OE
NOTE: The output data becomes valid when the last
intervals, t
AA
, t
ACE
, or t
OE
,
have concluded.
Figure 4. Timing Diagram
LH538700A
PRELIMINARY
CMOS 8M MROM
4
PACKAGE DIAGRAMS
13.45 [0.530]
12.95 [0.510]
0.51 [0.020] MIN.
5.20 [0.205]
5.00 [0.197]
3.50 [0.138]
3.00 [0.118]
2.54 [0.100]
TYP.
0.60 [0.024]
0.40 [0.016]
0.30 [0.012]
0.20 [0.008]
DETAIL
DIMENSIONS IN MM [INCHES]
41.30 [1.626]
40.70 [1.602]
0
TO 15
MAXIMUM LIMIT
MINIMUM LIMIT
4.50 [0.177]
4.00 [0.157]
15.24 [0.600]
TYP.
32DIP (DIP032-P-0600)
1
16
17
32
32DIP
32-pin, 600-mil DIP
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT
MINIMUM LIMIT
32SOP (SOP032-P-0525)
14.50 [0.571]
13.70 [0.539]
11.50 [0.453]
11.10 [0.437]
12.50 [0.492]
20.80 [0.819]
20.40 [0.803]
0.15 [0.006]
1.275 [0.050]
0.20 [0.008]
0.00 [0.000]
1.275 [0.050]
2.90 [0.114]
2.50 [0.098]
0.20 [0.008]
0.10 [0.004]
0.50 [0.020]
0.30 [0.012]
1.27 [0.050]
TYP.
32
17
16
1
1.40 [0.055]
1.40 [0.055]
32SOP
32-pin, 525-mil SOP
CMOS 8M MROM
PRELIMINARY
LH538700A
5
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT
MINIMUM LIMIT
32TSOP (Type II) (TSOP032-P-0400)
12.30 [0.484]
11.30 [0.445]
10.40 [0.409]
10.00 [0.394]
11.00 [0.433]
10.60 [0.417]
21.20 [0.835]
20.80 [0.819]
0.15 [0.006]
0.20 [0.008]
0.00 [0.000]
1.20 [0.047] MAX.
0.20 [0.008]
0.10 [0.004]
0.50 [0.020]
0.30 [0.012]
1.27 [0.050]
TYP.
32
1
32TSOP400
16
1.10 [0.043]
0.90 [0.035]
17
0.4375 [0.017]
32-pin, 400-mil TSOP (Type II)
D 32-pin, 600-mil DIP (DIP032-P-0600)
N 32-pin, 525-mil SOP (SOP032-P-0525)
S 32-pin, 400-mil
TSOP (Type II) (TSOP032-P-0400)
SR 32-pin, 400-mil
TSOP (Type II) Reverse bend (TSOP032-P-0400)
LH538700A
Device Type
X
Package
538700A-5
Example: LH538700AD (CMOS 8M (1M x 8) Mask-Programmable ROM, 32-pin, 600-mil DIP)
CMOS 8M (1M x 8) Mask-Programmable ROM
ORDERING INFORMATION
LH538700A
PRELIMINARY
CMOS 8M MROM
6
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