LH53B16R00
CMOS 16M (1M
16/512K
32) MROM
FEATURES
1,048,576
16 bit organization
(Word mode: W = V
IL
)
524,288
32 bit organization
(Double Word mode: W = V
IH
)
Access time: 120 ns (MAX.)
Access time in page mode: 50 ns (MAX.)
Supply current:
Operating: 180 mA (MAX.)
Standby: 300
A (MAX.)
TTL compatible I/O
Three-state outputs
Single +5 V power supply
Static operation
Package:
70-pin, 500-mil SSOP
Others:
Non programmable
Not designed or rated as radiation
hardened
CMOS process (P type silicon
substrate)
DESCRIPTION
The LH53B16R00 is a 16M-bit CMOS mask ROM
(mask-programmable-read-only memory) organized as
1,048,576
16 bits (Word mode) or 524,288
32 bits
(Double Word mode). It is fabricated using silicon-gate
CMOS process technology.
PIN CONNECTIONS
53B16R00-1
TOP VIEW
2
3
4
5
8
9
D
0
A
4
67
66
65
64
63
62
59
56
A
2
A
3
6
7
V
CC
V
CC
A
5
61
60
W
OE
GND
D
15
D
13
10
11
12
69
68
NC
D
16
13
58
D
29
V
CC
GND
57
GND
D
1
CE
70-PIN SSOP
14
15
16
17
18
19
20
21
53
50
55
54
52
51
D
12
D
27
D
11
D
26
D
20
D
5
D
4
D
3
D
18
D
19
D
2
D
21
GND
GND
D
31
/A
-1
(NOTE)
D
30
D
28
NC
70
1
A
1
A
0
22
49
D
10
D
17
D
14
NC
46
43
48
47
V
CC
23
24
25
26
45
D
8
D
24
D
9
44
V
CC
27
28
29
30
31
32
33
34
40
37
42
41
39
38
A
18
A
17
A
16
A
15
A
9
A
10
A
8
A
6
A
7
GND
A
11
A
12
V
CC
NC
35
36
A
14
A
13
D
6
D
7
D
23
D
22
D
25
NOTE: D
31
/A
-1
pin becomes LSB address input (A
-1
) when the
W pin is set to be LOW in word mode, and data output
(D
31
) when set to be HIGH in double word mode.
Figure 1. Pin Connections
1
53B16R00-2
A
3
A
2
A
12
A
11
A
10
A
9
A
8
35
34
33
32
29
4
3
A
7
A
6
A
4
MEMORY
MATRIX
(1,048,576 x 16)
(524,288 x 32)
SENSE AMPLIFIER
30
67
5
31
A
5
6
A
13
36
ADDRESS BUFFER
CE
ADDRESS DECODER
COLUMN SELECTOR
CE
BUFFER
OE
BUFFER
A
14
37
A
15
38
65
TIMING
GENERATOR
A
16
39
W
A
17
40
A
18
41
ADDRESS
BUFFER
WORD/DOUBLE
WORD SWITCHOVER
CIRCUIT
66
OE
ADDRESS
BUFFER
DATA SELECTOR/OUTPUT BUFFER
D
3
D
2
D
1
D
7
D
6
D
4
D
5
D
0
20
14
10
8
59
16
26
D
8
44
D
9
46
18
24
D
13
D
12
D
11
D
17
D
16
D
14
D
15
D
10
62
54
52
50
56
11
D
18
15
D
19
17
60
9
D
23
D
22
D
21
D
27
D
26
D
24
D
25
D
20
47
25
21
19
27
53
D
28
55
D
29
57
D
30
61
D
31
63
45
51
63
A
-1
A
0
1
A
1
2
V
CC
GND
48
64
49
28
22
12
58
23 43
7 13
Figure 2. LH53B16R00 Block Diagram
LH53B16R00
CMOS 16M (1M x 16/512K x 32) MROM
2
TRUTH TABLE
CE
OE
W
A
-1
(D
31
)
DATA OUTPUT
ADDRESS INPUT
SUPPLY
CURRENT
D
0
- D
15
D
16
- D
31
LSB
MSB
H
X
X
X
High-Z
High-Z
Standby (I
SB
)
L
H
X
X
High-Z
High-Z
Operating
L
L
H
D
0
- D
15
D
16
- D
31
A
0
A
18
Operating
L
L
L
L
D
0
- D
15
High-Z
A
-1
A
18
Operating
L
L
L
H
D
16
- D
31
High-Z
A
-1
A
18
Operating
NOTE:
X = Don't care; High-Z = High-impedance
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
UNIT
Supply voltage
V
CC
-0.3 to +7.0
V
Input voltage
V
IN
-0.3 to V
CC
+ 0.3
V
Output voltage
V
OUT
-0.3 to V
CC
+ 0.3
V
Operating temperature
T
OPR
0 to +70
C
Storage temperature
T
STG
-65 to +150
C
RECOMMENDED OPERATING CONDITIONS (T
A
= 0 to +70
C)
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
Supply voltage
V
CC
4.5
5.0
5.5
V
PIN DESCRIPTION
SIGNAL
PIN NAME
A
-1
- A
1
Address input
(page mode operation)
A
2
- A
18
Address input
D
0
- D
31
Data output
W
16 bit /
32 bit
(word/double word)
mode select input
SIGNAL
PIN NAME
CE
Chip enable input
OE
Output enable input
V
CC
Power pin (+5 V)
GND
Ground
NC
No connection
CMOS 16M (1M x 16/512K x 32) MROM
LH53B16R00
3
DC ELECTRICAL CHARACTERISTICS (V
CC
= 5 V
10%, T
A
= 0 to +70
C)
PARAMETER
SYMBOL
CONDITIONS
MIN.
MAX.
UNIT
NOTE
Input `High' voltage
V
IH
2.2
V
CC
+0.3
V
Input `Low' voltage
V
IL
-0.3
0.8
V
Output `High' voltage
V
OH
I
OH
= -400
A
2.4
V
Output `Low' voltage
V
OL
I
OL
= 2.0 mA
0.4
V
Input leakage current
| I
LI
|
V
IN
= 0 V to V
CC
10
A
Output leakage current
| I
LO
|
V
OUT
= 0 V to V
CC
10
A
1
Operating current
I
CC1
t
RC
= 120 ns
180
mA
2
Standby current
I
SB1
CE = V
IH
2
mA
I
SB2
CE = V
CC
- 0.2 V
300
A
Input capacitance
C
IN
f = 1 MHz, t
A
= 25
C
10
pF
Output capacitance
C
OUT
10
pF
NOTES:
1.
CE = V
IH
, OE = V
IH
, output is open
2.
V
IN
= V
IH
, V
IL
, CE = V
IL
, output is open
AC ELECTRICAL CHARACTERISTICS (V
CC
= 5 V
10%, T
A
= 0 to +70
C)
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
NOTE
Read cycle time
t
RC
120
ns
Address access time
t
AA
120
ns
Chip enable access time
t
ACE
120
ns
Page address access time
t
APA
50
ns
Output enable delay time
t
OE
50
ns
Output hold time
t
OH
5
ns
Output floating time
t
CHZ
40
ns
1
t
OHZ
40
ns
NOTE:
1.
Determined by the time for the output to be opened. (Irrespective of output voltage)
AC TEST CONDITIONS
PARAMETER
RATING
Input voltage amplitude
0.4 V to 2.6 V
Input signal rise time
10 ns
Input signal fall time
10 ns
Input/output reference level
1.5 V
Output load condition
1TTL + 100 pF
LH53B16R00
CMOS 16M (1M x 16/512K x 32) MROM
4
t
AA
A
2
- A
18
53B16R00-4
t
ACE
CE
(NOTE)
(NOTE)
OE
t
OE
(NOTE)
A
-1
- A
1
t
APA
(NOTE)
DATA
VALID
t
APA
(NOTE)
t
CHZ
t
OHZ
t
OH
t
OH
t
OH
t
OH
DATA
VALID
DATA
VALID
DATA
VALID
(A
0
- A
1
)
D
0
- D
15
(D
0
- D
31
)
NOTE: The output data becomes valid when the
last intervals, t
AA
, t
ACE
, t
APA
, or t
OE
,
have concluded.
Figure 4. Page Mode Read Cycle
t
AA
A
-1
- A
18
t
OHZ
t
CHZ
D
0
- D
15
53B16R00-3
t
RC
t
ACE
CE
DATA VALID
(NOTE)
(NOTE)
OE
t
OE
(NOTE)
(A
0
- A
18
)
(D
0
- D
31
)
t
OH
NOTE: The output data becomes valid when the
last intervals, t
AA
, t
ACE
, t
APA
, or t
OE
,
have concluded.
Figure 3. Read Cycle
CMOS 16M (1M x 16/512K x 32) MROM
LH53B16R00
5
PDF 
ZIP