LH5P864
CMOS 512K (64K
8) Pseudo-Static RAM
FEATURES
65,536
8 bit organization
Access time: 80 ns (MAX.)
Cycle time: 140 ns (MIN.)
Single +5 V power supply
Power consumption:
Operating: 440 mW (MAX.)
Standby (TTL level): 22 mW (MAX.)
Standby (CMOS level): 2.75 mW (MAX.)
Operating temperature: 0 to 70
C
TTL compatible I/O
512 refresh cycles/8 ms (MAX.)
Available for auto-refresh and
self-refresh modes
Package: 32-pin, 525-mil SOP
DESCRIPTION
The LH5P864 is a 512K-bit Pseudo-Static RAM or-
ganized as 65,536
8 bits. It is fabricated using sili-
con-gate CMOS process technology. With its built-in
oscillator, it is easy to refresh memories without an
external clock.
PIN CONNECTIONS
5P864-1
TOP VIEW
5
6
7
8
11
12
A
0
A
3
26
25
24
23
22
21
18
A
5
A
4
9
10
A
1
A
2
20
19
A
6
A
9
A
11
A
10
13
14
15
28
27
I/O
0
A
13
16
17
I/O
2
OE/RFSH
CE
1
A
7
GND
I/O
4
I/O
3
I/O
5
A
8
32-PIN SOP
3
4
A
12
30
29
CE
2
A
14
R/W
1
2
NC
32
31
V
CC
TEST
NC
I/O
1
I/O
6
I/O
7
Figure 1. Pin Connections for SOP Package
1
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
UNIT
NOTE
Applied voltage on any pin
V
T
-1.0 to +7.0
V
1
Output short circuit current
I
O
50
mA
Power dissipation
P
D
600
mW
Operating temperature
Topr
0 to +70
C
Storage temperature
Tstg
-65 to +150
C
NOTE:
1.
The maximum applicable voltage on any pin with respect to GND.
RECOMMENDED OPERATING CONDITIONS (T
A
= 0 to +70
C)
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
Supply voltage
V
CC
4.5
5.0
5.5
V
Input voltage
V
IH
2.4
V
CC
+ 0.3
V
V
IL
-1.0
0.8
V
CAPACITANCE (T
A
= 0 to +70
C, f = 1MHz, V
CC
= 5.0 V
10%)
PARAMETER
CONDITIONS
SYMBOL
MIN.
MAX.
UNIT
Input capacitance
A
0
- A
14
C
IN1
8
pF
R/W, OE/RFSH
C
IN2
8
pF
CE
1
, CE
2
C
IN3
8
pF
TEST
1
C
IN4
10
pF
Input/Output capacitance
I/O
0
- I/O
7
C
OUT1
10
pF
DC CHARACTERISTICS (T
A
= 0 to +70
C, V
CC
= 5.0 V
10%)
PARAMETER
SYMBOL
CONDITIONS
MIN.
MAX.
UNIT
NOTE
Operating current
I
CC1
t
RC
= t
RC
(MIN.)
80
mA
1, 2
Standby current
I
CC2
TTL input
4.0
mA
1, 3, 5
CMOS input
0.5
mA
1, 3, 6
Self refresh average current
I
CC3
TTL input
4.0
mA
1, 4, 5
CMOS input
0.5
mA
1, 4, 6
Input leakage current
I
LI
0 V
V
IN
6.5 V,
0 V except on test pins
-10
10
A
Output leakage current
I
LO
0 V
V
OUT
V
CC
+ 0.3 V,
Outputs in High-Z state
-10
10
A
Output HIGH voltage
V
OH
I
OUT
= -1.0 mA
2.4
V
Output LOW voltage
V
OL
I
OUT
= 4.0 mA
0.4
V
NOTES:
1.
Specified values are with outputs open.
2.
I
CC1
depends on the cycle time.
3.
CE
1
= CE
2
= V
IH
, OE/RFSH = V
IH
4.
CE
1
= CE
2
= V
IH
, OE/RFSH = V
IL
5.
CE
1
= CE
2
= V
CC
0.2 V, OE/RFSH = V
CC
0.2 V
6.
CE
1
= CE
2
= V
CC
0.2 V, OE/RFSH = 0.2 V
CMOS 512K (64K
8) Pseudo-Static RAM
LH5P864
3
AC CHARACTERISTICS
1,2,3
(T
A
= 0 to +70
C, V
CC
= 5.0 V
10%)
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
NOTE
Random read, write cycle time
t
RC
140
ns
Read modify write cycle time
t
RMW
205
ns
CE pulse width
t
CE
80
10,000
ns
CE precharge time
t
P
50
ns
Address setup time
t
AS
0
ns
4
Address hold time
t
AH
20
ns
4
Read command setup time
t
RCS
0
ns
Read command hold time
t
RCH
0
ns
CE access time
t
CEA
80
ns
5
OE access time
t
OEA
30
ns
5
CE to output in Low-Z
t
CLZ
20
ns
OE to output in Low-Z
t
OLZ
0
ns
R/W to output in Low-Z
t
WLZ
0
ns
Chip disable to output in High-Z
t
CHZ
25
ns
Output disable to output in High-Z
t
OHZ
25
ns
Write enable to output in High-Z
t
WHZ
25
ns
OE setup time
t
OES
10
ns
OE hold time
t
OEH
10
ns
OE lead time
t
OEL
10
ns
Write command pulse width
t
WCP
30
ns
Write command setup time
t
WCS
30
ns
Write command hold time
t
WCH
50
ns
Data setup time from write
t
DSW
30
ns
6
Data setup time from CE
t
DSC
30
ns
6
Data hold time from write
t
DHW
0
ns
6
Data hold time from CE
t
DHC
0
ns
6
Transition time (rise and fall)
t
T
3
35
ns
Refresh time interval
t
REF
8
ms
Auto refresh cycle time
t
FC
130
ns
Refresh delay time from CE
t
RFD
50
ns
Refresh pulse width (Auto refresh)
t
FAP
30
8,000
ns
Refresh precharge time (Auto refresh)
t
FP
30
ns
CE delay time from refresh precharge (Auto
refresh)
t
FCE
160
ns
Refresh pulse width (Self refresh)
t
FAS
8,000
ns
CE delay time from refresh precharge (Self refresh)
t
FRS
160
ns
NOTES:
1.
In order to initialize the circuit, CE
1
, CE
2
and OE/RFSH should
be kept in V
IH
for 100
s after power-up and followed by at least
8 dummy cycles.
2.
AC characteristics are measured at t
T
= 5 ns.
3.
AC characteristics are measured at the following condition (see
figure at right).
4.
Address is latched at the negative edge of CE
1
or CE
2
.
5.
Measured with a load equivalent to 2TTL + 100 pF.
6.
Data is latched at the positive edge of R/W or at the positive edge
of CE
1
or CE
2
.
2.4 V
0.8 V
2.6 V
0.6 V
2.2 V
0.8 V
OUTPUT
INPUT
5P864-3
Figure 3. AC Characteristics
LH5P864
CMOS 512K (64K
8) Pseudo-Static RAM
4
PDF 
ZIP
