LHF32K10

Rev. 1.55

Handle this document carefully for it contains material protected by international copyright

law. Any reproduction, full or in part, of this material is prohibited without the express
written permission of the company.

When using the products covered herein, please observe the conditions written herein

and the precautions outlined in the following paragraphs. In no event shall the company
be liable for any damages resulting from failure to strictly adhere to these conditions and
precautions.

(1) The products covered herein are designed and manufactured for the following

application areas. When using the products covered herein for the equipment listed
in Paragraph (2), even for the following application areas, be sure to observe the
precautions given in Paragraph (2). Never use the products for the equipment listed
in Paragraph (3).

·Office electronics
·Instrumentation and measuring equipment
·Machine tools
·Audiovisual equipment
·Home appliance
·Communication equipment other than for trunk lines

(2) Those contemplating using the products covered herein for the following equipment

which demands high reliability, should first contact a sales representative of the
company and then accept responsibility for incorporating into the design fail-safe
operation, redundancy, and other appropriate measures for ensuring reliability and
safety of the equipment and the overall system.

·Control and safety devices for airplanes, trains, automobiles, and other

transportation equipment

·Mainframe computers
·Traffic control systems
·Gas leak detectors and automatic cutoff devices
·Rescue and security equipment
·Other safety devices and safety equipment, etc.

(3) Do not use the products covered herein for the following equipment which demands

extremely high performance in terms of functionality, reliability, or accuracy.

·Aerospace equipment
·Communications equipment for trunk lines
·Control equipment for the nuclear power industry
·Medical equipment related to life support, etc.

(4) Please direct all queries and comments regarding the interpretation of the above

three Paragraphs to a sales representative of the company.

Please direct all queries regarding the products covered herein to a sales representative

of the company.

sharp

LHF32K10

Rev. 1.55

CONTENTS

PAGE

1 INTRODUCTION ...................................................... 3

1.1 Product Overview ................................................ 3

2 PRINCIPLES OF OPERATION ................................ 6

2.1 Data Protection ................................................... 6

3 BUS OPERATION.................................................... 8

3.1 Read ................................................................... 8

3.2 Output Disable .................................................... 8

3.3 Standby ............................................................... 8

3.4 Deep Power-Down .............................................. 8

3.5 Read Identifier Codes Operation ......................... 9

3.6 Query Operation.................................................. 9

3.7 Write.................................................................... 9

4 COMMAND DEFINITIONS ....................................... 9

4.1 Read Array Command....................................... 12

4.2 Read Identifier Codes Command ...................... 12

4.3 Read Status Register Command....................... 12

4.4 Clear Status Register Command....................... 12

4.5 Query Command ............................................... 13

4.5.1 Block Status Register .................................. 13

4.5.2 CFI Query Identification String..................... 14

4.5.3 System Interface Information ....................... 14

4.5.4 Device Geometry Definition ......................... 15

4.5.5 SCS OEM Specific Extended Query Table .. 15

4.6 Block Erase Command...................................... 16

4.7 Full Chip Erase Command ................................ 16

4.8 Word/Byte Write Command............................... 17

4.9 Multi Word/Byte Write Command ...................... 17

4.10 Block Erase Suspend Command..................... 18

4.11 (Multi) Word/Byte Write Suspend Command... 18

4.12 Set Block Lock-Bit Command.......................... 19

4.13 Clear Block Lock-Bits Command..................... 19

4.14 STS Configuration Command ......................... 20

PAGE

5 DESIGN CONSIDERATIONS .................................31

5.1 Three-Line Output Control .................................31

5.2 STS and Block Erase, Full Chip Erase, (Multi)

Word/Byte Write and Block Lock-Bit Configuration

Polling................................................................31

5.3 Power Supply Decoupling ..................................31

5.4 V

Trace on Printed Circuit Boards ..................31

5.5 V

, V

, RP# Transitions.................................32

5.6 Power-Up/Down Protection................................32

5.7 Power Dissipation ..............................................32

6 ELECTRICAL SPECIFICATIONS...........................33

6.1 Absolute Maximum Ratings ...............................33

6.2 Operating Conditions .........................................33

6.2.1 Capacitance .................................................33

6.2.2 AC Input/Output Test Conditions ..................34

6.2.3 DC Characteristics........................................35

6.2.4 AC Characteristics - Read-Only Operations .37

6.2.5 AC Characteristics - Write Operations ..........40

6.2.6 Alternative CE#-Controlled Writes ................42

6.2.7 Reset Operations .........................................44

6.2.8 Block Erase, Full Chip Erase, (Multi)

Word/Byte Write and Block Lock-Bit

Configuration Performance...........................45

7 ADDITIONAL INFORMATION ................................46

7.1 Ordering Information ..........................................46

8 PACKAGE AND PACKING SPECIFICATION........47

sharp

LHF32K10

Rev. 1.55

LH28F320S5NS-L90

32-MBIT (4MBx8/2MBx16)

Smart 5 Flash MEMORY

Smart 5 Technology

5V V

Common Flash Interface (CFI)

Universal & Upgradable Interface

Scalable Command Set (SCS)

High Speed Write Performance

32 Bytes x 2 plane Page Buffer
2µs/Byte Write Transfer Rate

High Speed Read Performance

90ns(5V±0.25V), 100ns(5V±0.5V)

Operating Temperature

0°C to +70°C

High-Density Symmetrically-Blocked

Architecture

Sixty-four 64-Kbyte Erasable Blocks

Extended Cycling Capability

100,000 Block Erase Cycles
6.4 Million Block Erase Cycles/Chip

Automated Write and Erase

Command User Interface
Status Register

Enhanced Automated Suspend Options

Write Suspend to Read
Block Erase Suspend to Write
Block Erase Suspend to Read

Enhanced Data Protection Features

Absolute Protection with V

=GND

Flexible Block Locking
Erase/Write Lockout during Power
Transitions

Low Power Management

Deep Power-Down Mode
Automatic Power Savings Mode
Decreases I

in Static Mode

User-Configurable x8 or x16 Operation

SRAM-Compatible Write Interface

Industry-Standard Packaging

56-Lead SSOP

ETOX

TM*

V Nonvolatile Flash

Technology

CMOS Process

(P-type silicon substrate)

Not designed or rated as radiation

hardened

SHARP's LH28F320S5NS-L90 Flash memory with Smart 5 technology is a high-density, low-cost, nonvolatile,
read/write storage solution for a wide range of applications. Its symmetrically-blocked architecture, flexible voltage
and extended cycling provide for highly flexible component suitable for resident flash arrays, SIMMs and memory
cards. Its enhanced suspend capabilities provide for an ideal solution for code + data storage applications. For
secure code storage applications, such as networking, where code is either directly executed out of flash or
downloaded to DRAM, the LH28F320S5NS-L90 offers three levels of protection: absolute protection with V

GND, selective hardware block locking, or flexible software block locking. These alternatives give designers
ultimate control of their code security needs.

The LH28F320S5NS-L90 is conformed to the flash Scalable Command Set (SCS) and the Common Flash Interface
(CFI) specification which enable universal and upgradable interface, enable the highest system/device data transfer
rates and minimize device and system-level implementation costs.

The LH28F320S5NS-L90 is manufactured on SHARP's 0.4µm ETOX

* V process technology. It come in industry-

standard package: the 56-Lead SSOP, ideal for board constrained applications.

*ETOX is a trademark of Intel Corporation.

sharp

LHF32K10

Rev. 1.55

1 INTRODUCTION

This datasheet contains LH28F320S5NS-L90
specifications. Section 1 provides a flash memory
overview. Sections 2, 3, 4, and 5 describe the
memory organization and functionality. Section 6
covers electrical specifications.

1.1 Product Overview

The LH28F320S5NS-L90 is a high-performance 32-
Mbit Smart 5 Flash memory organized as
4MBx8/2MBx16. The 4MB of data is arranged in
sixty-four 64-Kbyte blocks which are individually
erasable, lockable, and unlockable in-system. The
memory map is shown in Figure 3.

Smart 5 technology provides a choice of V

and

combinations, as shown in Table 1, to meet

system performance and power expectations. 5V V

provides the highest read performance. V

at 5V

eliminates the need for a separate 12V converter,
while V

=5V maximizes erase and write

performance. In addition to flexible erase and
program voltages, the dedicated V

pin gives

complete data protection when V

PPLK

Table 1. V

and V

Voltage Combinations

Offered by Smart 5 Technology

Voltage

Internal V

and V

detection Circuitry

automatically configures the device for optimized
read and write operations.

A Command User Interface (CUI) serves as the
interface between the system processor and internal
operation of the device. A valid command sequence
written to the CUI initiates device automation. An
internal Write State Machine (WSM) automatically
executes the algorithms and timings necessary for
block erase, full chip erase, (multi) word/byte write
and block lock-bit configuration operations.

A block erase operation erases one of the device's
64-Kbyte blocks typically within 0.34s (5V V

, 5V

) independent of other blocks. Each block can be

independently erased 100,000 times (6.4 million
block erases per device). Block erase suspend mode
allows system software to suspend block erase to
read or write data from any other block.

A word/byte write is performed in byte increments
typically within 9.24µs (5V V

, 5V V

). A multi

word/byte write has high speed write performance of
2µs/byte (5V V

, 5V V

). (Multi) Word/byte write

suspend mode enables the system to read data or

execute code from any other flash memory array
location.

Individual block locking uses a combination of bits
and WP#, Sixty-four block lock-bits, to lock and
unlock blocks. Block lock-bits gate block erase, full
chip erase and (multi) word/byte write operations.
Block lock-bit configuration operations (Set Block
Lock-Bit and Clear Block Lock-Bits commands) set
and cleared block lock-bits.

The status register indicates when the WSM's block
erase, full chip erase, (multi) word/byte write or block
lock-bit configuration operation is finished.

The STS output gives an additional indicator of WSM
activity by providing both a hardware signal of status
(versus software polling) and status masking
(interrupt masking for background block erase, for
example). Status polling using STS minimizes both
CPU overhead and system power consumption. STS
pin can be configured to different states using the
Configuration command. The STS pin defaults to
RY/BY# operation. When low, STS indicates that the
WSM is performing a block erase, full chip erase,
(multi) word/byte write or block lock-bit configuration.
STS-High Z indicates that the WSM is ready for a
new command, block erase is suspended and (multi)
word/byte write are inactive, (multi) word/byte write
are suspended, or the device is in deep power-down
mode. The other 3 alternate configurations are all
pulse mode for use as a system interrupt.

The access time is 90ns (t

AVQV

) over the commercial

temperature range (0°C to +70°C) and V

supply

voltage range of 4.75V-5.25V. At lower V

voltage,

the access time is 100ns (4.5V-5.5V).

The Automatic Power Savings (APS) feature
substantially reduces active current when the device
is in static mode (addresses not switching). In APS
mode, the typical I

CCR

current is 1 mA at 5V V

When either CE

# or CE

#, and RP# pins are at V

the I

CMOS standby mode is enabled. When the

RP# pin is at GND, deep power-down mode is
enabled which minimizes power consumption and
provides write protection during reset. A reset time
(t

PHQV

) is required from RP# switching high until

outputs are valid. Likewise, the device has a wake
time (t

PHEL

) from RP#-high until writes to the CUI are

recognized. With RP# at GND, the WSM is reset and
the status register is cleared.

The device is available in 56-Lead SSOP (Shrink
Small Outline Package). Pinout is shown in Figure 2.

sharp

Output

Input

Buffer

Output

Multiplexer

I/O Logic

Command

CE#

WE#

RP#

OE#

Idenrifier

Status

Data

Comparator

Y Gating

Decoder

64KByte

Blocks

Input

Buffer

Address

Latch

Address

Counter

Write State

Machine

Program/Erase

Voltage Switch

STS

GND

-A

-DQ

Query

ROM

Data

Buffer

Page

WP#

BYTE#

Multiplexer

56 LEAD SSOP

STANDARD PINOUT

1.8mm x 16mm x 23.7mm

TOP VIEW

2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17

21
22
23
24
25
26
27
28

WE#

OE#

STS

WP#

GND

NC
NC

BYTE#

RP#

LHF32K10

Rev. 1.55

Figure 1. Block Diagram

Figure 2. SSOP 56-Lead Pinout

sharp

LHF32K10

Rev. 1.55

Table 2. Pin Descriptions

Symbol

Type

Name and Function

-A

INPUT

ADDRESS INPUTS: Inputs for addresses during read and write operations. Addresses are
internally latched during a write cycle.
A

: Byte Select Address. Not used in x16 mode(can be floated).

-A

: Column Address. Selects 1 of 16 bit lines.

-A

: Row Address. Selects 1 of 2048 word lines.

-A

: Block Address.

-DQ

INPUT/

OUTPUT

DATA INPUT/OUTPUTS:
DQ

-DQ

:Inputs data and commands during CUI write cycles; outputs data during memory

array, status register, query, and identifier code read cycles. Data pins float to high-
impedance when the chip is deselected or outputs are disabled. Data is internally latched
during a write cycle.
DQ

-DQ

:Inputs data during CUI write cycles in x16 mode; outputs data during memory

array read cycles in x16 mode; not used for status register, query and identifier code read
mode. Data pins float to high-impedance when the chip is deselected, outputs are
disabled, or in x8 mode(Byte#=V

). Data is internally latched during a write cycle.

INPUT

CHIP ENABLE: Activates the device's control logic, input buffers decoders, and sense
amplifiers. Either CE

# or CE

# V

deselects the device and reduces power consumption

to standby levels. Both CE

# and CE

# must be V

to select the devices.

RP#

INPUT

RESET/DEEP POWER-DOWN: Puts the device in deep power-down mode and resets
internal automation. RP# V

enables normal operation. When driven V

, RP# inhibits

write operations which provides data protection during power transitions. Exit from deep
power-down sets the device to read array mode.

OE#

INPUT

OUTPUT ENABLE: Gates the device's outputs during a read cycle.

WE#

INPUT

WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are
latched on the rising edge of the WE# pulse.

STS

OPEN

DRAIN

OUTPUT

STS (RY/BY#): Indicates the status of the internal WSM. When configured in level mode
(default mode), it acts as a RY/BY# pin. When low, the WSM is performing an internal
operation (block erase, full chip erase, (multi) word/byte write or block lock-bit
configuration). STS High Z indicates that the WSM is ready for new commands, block
erase is suspended, and (multi) word/byte write is inactive, (multi) word/byte write is
suspended or the device is in deep power-down mode. For alternate configurations of the
STATUS pin, see the Configuration command.

WP#

INPUT

WRITE PROTECT: Master control for block locking. When V

IL,

Locked blocks can not be

erased and programmed, and block lock-bits can not be set and reset.

BYTE#

INPUT

BYTE ENABLE: BYTE# V

places device in x8 mode. All data is then input or output on

0-7

, and DQ

8-15

float. BYTE# V

places the device in x16 mode , and turns off the A

input buffer.

SUPPLY

BLOCK ERASE, FULL CHIP ERASE, (MULTI) WORD/BYTE WRITE, BLOCK LOCK-
BIT CONFIGURATION POWER SUPPLY: For erasing array blocks, writing bytes or
configuring block lock-bits. With V

PPLK

, memory contents cannot be altered. Block

erase, full chip erase, (multi) word/byte write and block lock-bit configuration with an invalid
V

(see DC Characteristics) produce spurious results and should not be attempted.

SUPPLY

DEVICE POWER SUPPLY: Internal detection configures the device for 5V operation. Do
not float any power pins. With V

LKO

, all write attempts to the flash memory are

inhibited. Device operations at invalid V

voltage (see DC Characteristics) produce

spurious results and should not be attempted.

GND

SUPPLY GROUND: Do not float any ground pins.

NO CONNECT: Lead is not internal connected; it may be driven or floated.

sharp

LHF32K10

Rev. 1.55

2 PRINCIPLES OF OPERATION

The LH28F320S5NS-L90 Flash memory includes an
on-chip WSM to manage block erase, full chip erase,
(multi) word/byte write and block lock-bit
configuration functions. It allows for: 100% TTL-level
control inputs, fixed power supplies during block
erase, full chip erase, (multi) word/byte write and
block lock-bit configuration, and minimal processor
overhead with RAM-Like interface timings.

After initial device power-up or return from deep
power-down mode (see Bus Operations), the device
defaults to read array mode. Manipulation of external
memory control pins allow array read, standby, and
output disable operations.

Status register, query structure and identifier codes
can be accessed through the CUI independent of the
V

voltage. High voltage on V

enables successful

block erase, full chip erase, (multi) word/byte write
and block lock-bit configuration. All functions
associated with altering memory contents

block

erase, full chip erase, (multi) word/byte write and
block lock-bit configuration, status, query and
identifier codes

are accessed via the CUI and

verified through the status register.

Commands are written using standard
microprocessor write timings. The CUI contents serve
as input to the WSM, which controls the block erase,
full chip erase, (multi) word/byte write and block lock-
bit configuration. The internal algorithms are
regulated by the WSM, including pulse repetition,
internal verification, and margining of data.
Addresses and data are internally latch during write
cycles. Writing the appropriate command outputs
array data, accesses the identifier codes, outputs
query structure or outputs status register data.

Interface software that initiates and polls progress of
block erase, full chip erase, (multi) word/byte write
and block lock-bit configuration can be stored in any
block. This code is copied to and executed from
system RAM during flash memory updates. After
successful completion, reads are again possible via
the Read Array command. Block erase suspend
allows system software to suspend a block erase to
read or write data from any other block. Write
suspend allows system software to suspend a (multi)
word/byte write to read data from any other flash
memory array location.

2.1 Data Protection

Depending on the application, the system designer
may choose to make the V

power supply

switchable (available only when block erase, full chip
erase, (multi) word/byte write and block lock-bit
configuration are required) or hardwired to V

PPH1

The device accommodates either design practice and
encourages optimization of the processor-memory
interface.

When V

PPLK

, memory contents cannot be

altered. The CUI, with multi-step block erase, full chip
erase, (multi) word/byte write and block lock-bit
configuration command sequences, provides
protection from unwanted operations even when high
voltage is applied to V

. All write functions are

disabled when V

is below the write lockout voltage

LKO

or when RP# is at V

. The device's block

locking capability provides additional protection from
inadvertent code or data alteration by gating block
erase, full chip erase and (multi) word/byte write
operations.

sharp

1FFFFF

1F0000

1EFFFF

1E0000

1DFFFF

1D0000

1CFFFF

1C0000

1BFFFF

1B0000

1AFFFF

1A0000

19FFFF

190000

18FFFF

180000

17FFFF

170000

16FFFF

160000

15FFFF

150000

14FFFF

140000

13FFFF

130000

12FFFF

120000

11FFFF

110000

10FFFF

100000

0FFFFF

0F0000

0EFFFF

0E0000

0DFFFF

0D0000

0CFFFF

0C0000

0BFFFF

0B0000

0AFFFF

0A0000

09FFFF

090000

08FFFF

080000

07FFFF

070000

06FFFF

060000

05FFFF

050000

04FFFF

040000

03FFFF

030000

02FFFF

020000

01FFFF

010000

00FFFF

000000

64-Kbyte Block 27

64-Kbyte Block 28

64-Kbyte Block 26

64-Kbyte Block 25

64-Kbyte Block 24

64-Kbyte Block 21

64-Kbyte Block 29

64-Kbyte Block 30

64-Kbyte Block 31

64-Kbyte Block 20

64-Kbyte Block 19

64-Kbyte Block 18

64-Kbyte Block 17

64-Kbyte Block 16

64-Kbyte Block 23

64-Kbyte Block 22

64-Kbyte Block 11

64-Kbyte Block 12

64-Kbyte Block 10

64-Kbyte Block 9

64-Kbyte Block 8

64-Kbyte Block 5

64-Kbyte Block 13

64-Kbyte Block 14

64-Kbyte Block 15

64-Kbyte Block 4

64-Kbyte Block 3

64-Kbyte Block 2

64-Kbyte Block 1

64-Kbyte Block 0

64-Kbyte Block 7

64-Kbyte Block 6

3FFFFF

3F0000

3EFFFF

3E0000

3DFFFF

3D0000

3CFFFF

3C0000

3BFFFF

3B0000

3AFFFF

3A0000

39FFFF

390000

38FFFF

380000

37FFFF

370000

36FFFF

360000

35FFFF

350000

34FFFF

340000

33FFFF

330000

32FFFF

320000

31FFFF

310000

30FFFF

300000

2FFFFF

2F0000

2EFFFF

2E0000

2DFFFF

2D0000

2CFFFF

2C0000

2BFFFF

2B0000

2AFFFF

2A0000

29FFFF

290000

28FFFF

280000

27FFFF

270000

26FFFF

260000

25FFFF

250000

24FFFF

240000

23FFFF

230000

22FFFF

220000

21FFFF

210000

20FFFF

200000

64-Kbyte Block 59

64-Kbyte Block 60

64-Kbyte Block 58

64-Kbyte Block 57

64-Kbyte Block 56

64-Kbyte Block 53

64-Kbyte Block 61

64-Kbyte Block 62

64-Kbyte Block 63

64-Kbyte Block 52

64-Kbyte Block 51

64-Kbyte Block 50

64-Kbyte Block 49

64-Kbyte Block 48

64-Kbyte Block 55

64-Kbyte Block 54

64-Kbyte Block 43

64-Kbyte Block 44

64-Kbyte Block 42

64-Kbyte Block 41

64-Kbyte Block 40

64-Kbyte Block 37

64-Kbyte Block 45

64-Kbyte Block 46

64-Kbyte Block 47

64-Kbyte Block 36

64-Kbyte Block 35

64-Kbyte Block 34

64-Kbyte Block 33

64-Kbyte Block 32

64-Kbyte Block 39

64-Kbyte Block 38

LHF32K10

Rev. 1.55

Figure 3. Memory Map

sharp

LHF32K10

Rev. 1.55

3 BUS OPERATION

The local CPU reads and writes flash memory in-
system. All bus cycles to or from the flash memory
conform to standard microprocessor bus cycles.

3.1 Read

Information can be read from any block, identifier
codes, query structure, or status register independent
of the V

voltage. RP# must be at V

The first task is to write the appropriate read mode
command (Read Array, Read Identifier Codes, Query
or Read Status Register) to the CUI. Upon initial
device power-up or after exit from deep power-down
mode, the device automatically resets to read array
mode. Five control pins dictate the data flow in and
out of the component: CE# (CE

#, CE

#), OE#, WE#,

RP# and WP#. CE

#, CE

# and OE# must be driven

active to obtain data at the outputs. CE

#, CE

# is

the device selection control, and when active enables
the selected memory device. OE# is the data output
(DQ

-DQ

) control and when active drives the

selected memory data onto the I/O bus. WE# and
RP# must be at V

. Figure 17, 18 illustrates a read

cycle.

3.2 Output Disable

With OE# at a logic-high level (V

), the device

outputs are disabled. Output pins DQ

-DQ

are

placed in a high-impedance state.

3.3 Standby

Either CE

# or CE

# at a logic-high level (V

) places

the device in standby mode which substantially
reduces device power consumption. DQ

-DQ

outputs are placed in a high-impedance state
independent of OE#. If deselected during block
erase, full chip erase, (multi) word/byte write and

block lock-bit configuration, the device continues
functioning, and consuming active power until the
operation completes.

3.4 Deep Power-Down

RP# at V

initiates the deep power-down mode.

In read modes, RP#-low deselects the memory,
places output drivers in a high-impedance state and
turns off all internal circuits. RP# must be held low for
a minimum of 100 ns. Time t

PHQV

is required after

return from power-down until initial memory access
outputs are valid. After this wake-up interval, normal
operation is restored. The CUI is reset to read array
mode and status register is set to 80H.

During block erase, full chip erase, (multi) word/byte
write or block lock-bit configuration modes, RP#-low
will abort the operation. STS remains low until the
reset operation is complete. Memory contents being
altered are no longer valid; the data may be partially
erased or written. Time t

PHWL

is required after RP#

goes to logic-high (V

) before another command can

be written.

As with any automated device, it is important to
assert RP# during system reset. When the system
comes out of reset, it expects to read from the flash
memory. Automated flash memories provide status
information when accessed during block erase, full
chip erase, (multi) word/byte write and block lock-bit
configuration. If a CPU reset occurs with no flash
memory reset, proper CPU initialization may not
occur because the flash memory may be providing
status information instead of array data. SHARP's
flash memories allow proper CPU initialization
following a system reset through the use of the RP#
input. In this application, RP# is controlled by the
same RESET# signal that resets the system CPU.

sharp

00FFFF

000006

000004

000002

000000

01FFFF

010006

010004
010003

010000

3FFFFF

3F0005
3F0004
3F0003

3F0000

Reserved for

Future Implementation

Block 63 Status Code

Block 63

(Blocks 2 through 62)

Device Code

Manufacturer Code

Reserved for

Future Implementation

Block 1

Reserved for

Future Implementation

Block 0

Reserved for

Future Implementation

Block 1 Status Code

Block 0 Status Code

Reserved for

Future Implementation

3EFFFF

020000

3F0006

010005

000005

000003

000001

LHF32K10

Rev. 1.55

3.5 Read Identifier Codes Operation

The read identifier codes operation outputs the
manufacturer code, device code, block status codes
for each block (see Figure 4). Using the manufacturer
and device codes, the system CPU can automatically
match the device with its proper algorithms. The
block status codes identify locked or unlocked block
setting and erase completed or erase uncompleted
condition.

Figure 4. Device Identifier Code Memory Map

3.6 Query Operation

The query operation outputs the query structure.
Query database is stored in the 48Byte ROM. Query
structure allows system software to gain critical
information for controlling the flash component.
Query structure are always presented on the lowest-
order data output (DQ

-DQ

) only.

3.7 Write

Writing commands to the CUI enable reading of
device data and identifier codes. They also control
inspection and clearing of the status register. When
V

CC1/2

and V

PPH1

, the CUI additionally

controls block erase, full chip erase, (multi) word/byte
write and block lock-bit configuration.

The Block Erase command requires appropriate
command data and an address within the block to be
erased. The Word/byte Write command requires the
command and address of the location to be written.
Set Block Lock-Bit command requires the command
and block address within the device (Block Lock) to
be locked. The Clear Block Lock-Bits command
requires the command and address within the device.

The CUI does not occupy an addressable memory
location. It is written when WE# and CE# are active.
The address and data needed to execute a command
are latched on the rising edge of WE# or CE#
(whichever goes high first). Standard microprocessor
write timings are used. Figures 19 and 20 illustrate
WE# and CE#-controlled write operations.

4 COMMAND DEFINITIONS

When the V

voltage

PPLK,

Read operations from

the status register, identifier codes, query, or blocks
are enabled. Placing V

PPH1

on V

enables

successful block erase, full chip erase, (multi)
word/byte write and block lock-bit configuration
operations.

Device operations are selected by writing specific
commands into the CUI. Table 4 defines these
commands.

sharp

LHF32K10

Rev. 1.55

Table 3. Bus Operations(BYTE#=V

)

Mode

Notes

RP#

OE#

WE#

Address

0-15

STS

Read

1,2,3,9

OUT

Output Disable

High Z

Standby

High Z

Deep Power-Down

High Z

Read Identifier
Codes

See

Figure 4

Note 5

High Z

Query

See Table

7~11

Note 6

High Z

Write

3,7,8,9

Table 3.1. Bus Operations(BYTE#=V

)

Mode

Notes

RP#

OE#

WE#

Address

0-7

STS

Read

1,2,3,9

OUT

Output Disable

High Z

Standby

High Z

Deep Power-Down

High Z

Read Identifier
Codes

See

Figure 4

Note 5

High Z

Query

See Table

7~11

Note 6

High Z

Write

3,7,8,9

NOTES:
1. Refer to DC Characteristics. When V

PPLK

, memory contents can be read, but not altered.

2. X can be V

or V

for control pins and addresses, and V

PPLK

or V

PPH1

for V

. See DC Characteristics for

PPLK

and V

PPH1

voltages.

3. STS is V

(if configured to RY/BY# mode) when the WSM is executing internal block erase, full chip erase,

(multi) word/byte write or block lock-bit configuration algorithms. It is floated during when the WSM is not busy,
in block erase suspend mode with (multi) word/byte write inactive, (multi) word/byte write suspend mode, or
deep power-down mode.

4. RP# at GND

±0.2V ensures the lowest deep power-down current.

5. See Section 4.2 for read identifier code data.
6. See Section 4.5 for query data.
7. Command writes involving block erase, full chip erase, (multi) word/byte write or block lock-bit configuration are

reliably executed when V

PPH1

and V

CC1/2

8. Refer to Table 4 for valid D

during a write operation.

9. Don't use the timing both OE# and WE# are V

sharp

LHF32K10

Rev. 1.55

Table 4. Command Definitions

(10)

Bus Cycles Notes

First Bus Cycle

Second Bus Cycle

Command

Req'd

Oper

(1)

Addr

(2)

Data

(3)

Oper

(1)

Addr

(2)

Data

(3)

Read Array/Reset

Write

FFH

Read Identifier Codes

Write

90H

Read

Query

Write

98H

Read

Read Status Register

Write

70H

Read

SRD

Clear Status Register

Write

50H

Block Erase Setup/Confirm

Write

20H

Write

D0H

Full Chip Erase Setup/Confirm

Write

30H

Write

D0H

Word/Byte Write Setup/Write

5,6

Write

40H

Write

Alternate Word/Byte Write
Setup/Write

5,6

Write

10H

Write

Multi Word/Byte Write
Setup/Confirm

Write

E8H

Write

N-1

Block Erase and (Multi)
Word/byte Write Suspend

Write

B0H

Confirm and Block Erase and
(Multi) Word/byte Write Resume

Write

D0H

Block Lock-Bit Set Setup/Confirm

Write

60H

Write

01H

Block Lock-Bit Reset
Setup/Confirm

Write

60H

Write

D0H

STS Configuration
Level-Mode for Erase and Write
(RY/BY# Mode)

Write

B8H

Write

00H

STS Configuration
Pulse-Mode for Erase

Write

B8H

Write

01H

STS Configuration
Pulse-Mode for Write

Write

B8H

Write

02H

STS Configuration
Pulse-Mode for Erase and Write

Write

B8H

Write

03H

NOTES:
1. BUS operations are defined in Table 3 and Table 3.1.
2. X=Any valid address within the device.

IA=Identifier Code Address: see Figure 4.
QA=Query Offset Address.
BA=Address within the block being erased or locked.
WA=Address of memory location to be written.

3. SRD=Data read from status register. See Table 14 for a description of the status register bits.

WD=Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high
first).
ID=Data read from identifier codes.
QD=Data read from query database.

4. Following the Read Identifier Codes command, read operations access manufacturer, device and block status

codes. See Section 4.2 for read identifier code data.

5. If the block is locked, WP# must be at V

to enable block erase or (multi) word/byte write operations. Attempts

to issue a block erase or (multi) word/byte write to a locked block while RP# is V

6. Either 40H or 10H are recognized by the WSM as the byte write setup.
7. A block lock-bit can be set while WP# is V

8. WP# must be at V

to clear block lock-bits. The clear block lock-bits operation simultaneously clears all block

lock-bits.

9. Following the Third Bus Cycle, inputs the write address and write data of 'N' times. Finally, input the confirm

command 'D0H'.

10. Commands other than those shown above are reserved by SHARP for future device implementations and

should not be used.

sharp

LHF32K10

Rev. 1.55

4.1 Read Array Command

Upon initial device power-up and after exit from deep
power-down mode, the device defaults to read array
mode. This operation is also initiated by writing the
Read Array command. The device remains enabled
for reads until another command is written. Once the
internal WSM has started a block erase, full chip
erase, (multi) word/byte write or block lock-bit
configuration, the device will not recognize the Read
Array command until the WSM completes its
operation unless the WSM is suspended via an Erase
Suspend and (Multi) Word/byte Write Suspend
command. The Read Array command functions
independently of the V

voltage and RP# must be

4.2 Read Identifier Codes Command

The identifier code operation is initiated by writing the
Read Identifier Codes command. Following the
command write, read cycles from addresses shown in
Figure 4 retrieve the manufacturer, device, block lock
configuration and block erase status (see Table 5 for
identifier code values). To terminate the operation,
write another valid command. Like the Read Array
command, the Read Identifier Codes command
functions independently of the V

voltage and RP#

must be V

. Following the Read Identifier Codes

command, the following information can be read:

Table 5. Identifier Codes

Code

Address

-A

Data

Manufacture Code

000000
000001

Device Code

000002
000003

Block Status Code

X0004

(1)

X0005

(1)

·Block is Unlocked

·Block is Locked

·Last erase operation

completed successfully

·Last erase operation did

not completed successfully

·Reserved for Future Use

2-7

NOTE:
1. X selects the specific block status code to be

read. See Figure 4 for the device identifier code
memory map.

4.3 Read Status Register Command

The status register may be read to determine when a
block erase, full chip erase, (multi) word/byte write or
block lock-bit configuration is complete and whether
the operation completed successfully(see Table 14).
It may be read at any time by writing the Read Status
Register command. After writing this command, all
subsequent read operations output data from the
status register until another valid command is written.
The status register contents are latched on the falling
edge of OE# or CE#(Either CE

# or CE

#),

whichever occurs. OE# or CE#(Either CE

# or CE

must toggle to V

before further reads to update the

status register latch. The Read Status Register
command functions independently of the V

voltage.

RP# must be V

The extended status register may be read to
determine multi word/byte write availability(see Table
14.1). The extended status register may be read at
any time by writing the Multi Word/Byte Write
command. After writing this command, all subsequent
read operations output data from the extended status
register, until another valid command is written. Multi
Word/Byte Write command must be re-issued to
update the extended status register latch.

4.4 Clear Status Register Command

Status register bits SR.5, SR.4, SR.3 and SR.1 are
set to "1"s by the WSM and can only be reset by the
Clear Status Register command. These bits indicate
various failure conditions (see Table 14). By allowing
system software to reset these bits, several
operations (such as cumulatively erasing or locking
multiple blocks or writing several bytes in sequence)
may be performed. The status register may be polled
to determine if an error occurs during the sequence.

To clear the status register, the Clear Status Register
command (50H) is written. It functions independently
of the applied V

Voltage. RP# must be V

. This

command is not functional during block erase, full
chip erase, (multi) word/byte write block lock-bit
configuration, block erase suspend or (multi)
word/byte write suspend modes.

sharp

LHF32K10

Rev. 1.55

4.5 Query Command

Query database can be read by writing Query
command (98H). Following the command write, read
cycle from address shown in Table 7~11 retrieve the
critical information to write, erase and otherwise
control the flash component. A

of query offset

address is ignored when X8 mode (BYTE#=V

Query data are always presented on the low-byte
data output (DQ

-DQ

). In x16 mode, high-byte

(DQ

-DQ

) outputs 00H. The bytes not assigned to

any information or reserved for future use are set to
"0". This command functions independently of the
V

voltage. RP# must be V

Table 6. Example of Query Structure Output

Mode

Offset Address

Output

15~8

7~0

X8 mode

, A

1 , 0 , 0 , 0 , 0 , 0 (20H)
1 , 0 , 0 , 0 , 0 , 1 (21H)
1, 0 , 0 , 0 , 1 , 0 (22H)
1 , 0 , 0 , 0 , 1 , 1 (23H)

High-Z
High-Z
High-Z
High-Z

"Q"
"Q"

"R"
"R"

X16 mode

, A

1 , 0 , 0 , 0 , 0 (10H)
1 , 0 , 0 , 0 , 1 (11H)

00H
00H

"Q"

"R"

4.5.1 Block Status Register

This field provides lock configuration and erase status for the specified block. These informations are only available
when device is ready (SR.7=1). If block erase or full chip erase operation is finished irregulary, block erase status
bit will be set to "1". If bit 1 is "1", this block is invalid.

Table 7. Query Block Status Register

Offset

(Word Address)

Length

Description

(BA+2)H

01H

Block Status Register
bit0 Block Lock Configuration
0=Block is unlocked
1=Block is Locked
bit1 Block Erase Status
0=Last erase operation completed successfully
1=Last erase operation not completed successfully
bit2-7 reserved for future use

Note:
1. BA=The beginning of a Block Address.

sharp

LHF32K10

Rev. 1.55

4.5.2 CFI Query Identification String

The Identification String provides verification that the component supports the Common Flash Interface
specification. Additionally, it indicates which version of the spec and which Vendor-specified command set(s) is(are)
supported.

Table 8. CFI Query Identification String

Offset

(Word Address)

Length

Description

10H,11H,12H

03H

Query Unique ASCII string "QRY"
51H,52H,59H

13H,14H

02H

Primary Vendor Command Set and Control Interface ID Code
01H,00H (SCS ID Code)

15H,16H

02H

Address for Primary Algorithm Extended Query Table
31H,00H (SCS Extended Query Table Offset)

17H,18H

02H

Alternate Vendor Command Set and Control Interface ID Code
0000H (0000H means that no alternate exists)

19H,1AH

02H

Address for Alternate Algorithm Extended Query Table
0000H (0000H means that no alternate exists)

4.5.3 System Interface Information

The following device information can be useful in optimizing system interface software.

Table 9. System Information String

Offset

(Word Address)

Length

Description

1BH

01H

Logic Supply Minimum Write/Erase voltage

45H (4.5V)

1CH

01H

Logic Supply Maximum Write/Erase voltage

55H (5.5V)

1DH

01H

Programming Supply Minimum Write/Erase voltage

45H (4.5V)

1EH

01H

Programming Supply Maximum Write/Erase voltage

55H (5.5V)

1FH

01H

Typical Timeout per Single Byte/Word Write
04H (2

=16µs)

20H

01H

Typical Timeout for Maximum Size Buffer Write (32 Bytes)
06H (2

=64µs)

21H

01H

Typical Timeout per Individual Block Erase
09H (09H=9, 2

=512ms)

22H

01H

Typical Timeout for Full Chip Erase
0FH (0FH=15, 2

=32768ms)

23H

01H

Maximum Timeout per Single Byte/Word Write, 2

times of typical.

04H (2

=16, 16µsx16=256µs)

24H

01H

Maximum Timeout Maximum Size Buffer Write, 2

times of typical.

04H (24=16, 64µsx16=1024µs)

25H

01H

Maximum Timeout per Individual Block Erase, 2

times of typical.

04H (2

=16, 1024msx16=16384ms)

26H

01H

Maximum Timeout for Full Chip Erase, 2

times of typical.

04H (2

=16, 32768msx16=524288ms)

sharp

LHF32K10

Rev. 1.55

4.5.4 Device Geometry Definition

This field provides critical details of the flash device geometry.

Table 10. Device Geometry Definition

Offset

(Word Address)

Length

Description

27H

01H

Device Size
16H (16H=22, 2

=4194304=4M Bytes)

28H,29H

02H

Flash Device Interface description
02H,00H (x8/x16 supports x8 and x16 via BYTE#)

2AH,2BH

02H

Maximum Number of Bytes in Multi-byte
05H,00H (2

=32 Bytes )

2CH

01H

Number of Erase Block Regions within device
01H (symmetrically blocked)

2DH,2EH

02H

The Number of Erase Blocks
3FH,00H (3FH=63 ==> 63+1=64 Blocks)

2FH,30H

02H

The Number of "256 Bytes" cluster in a Erase block
00H,01H (0100H=256 ==>256 Bytes x 256= 64K Bytes in a Erase Block)

4.5.5 SCS OEM Specific Extended Query Table

Certain flash features and commands may be optional in a vendor-specific algorithm specification. The optional
vendor-specific Query table(s) may be used to specify this and other types of information. These structures are
defined solely by the flash vendor(s).

Table 11. SCS OEM Specific Extended Query Table

Offset

(Word Address)

Length

Description

31H,32H,33H

03H

PRI
50H,52H,49H

34H

01H

31H (1) Major Version Number , ASCII

35H

01H

30H (0) Minor Version Number, ASCII

36H,37H,
38H,39H

04H

0FH,00H,00H,00H
Optional Command Support
bit0=1 : Chip Erase Supported
bit1=1 : Suspend Erase Supported
bit2=1 : Suspend Write Supported
bit3=1 : Lock/Unlock Supported
bit4=0 : Queued Erase Not Supported
bit5-31=0 : reserved for future use

3AH

01H

01H
Supported Functions after Suspend
bit0=1 : Write Supported after Erase Suspend
bit1-7=0 : reserved for future use

3BH,3CH

02H

03H,00H
Block Status Register Mask
bit0=1 : Block Status Register Lock Bit [BSR.0] active
bit1=1 : Block Status Register Valid Bit [BSR.1] active
bit2-15=0 : reserved for future use

3DH

01H

Logic Supply Optimum Write/Erase voltage(highest performance)

50H(5.0V)

3EH

01H

Programming Supply Optimum Write/Erase voltage(highest performance)

50H(5.0V)

3FH

reserved

Reserved for future versions of the SCS Specification

sharp

LHF32K10

Rev. 1.55

4.6 Block Erase Command

Block erase is executed one block at a time and
initiated by a two-cycle command. A block erase
setup is first written, followed by an block erase
confirm. This command sequence requires
appropriate sequencing and an address within the
block to be erased (erase changes all block data to
FFH). Block preconditioning, erase and verify are
handled internally by the WSM (invisible to the
system). After the two-cycle block erase sequence is
written, the device automatically outputs status
register data when read (see Figure 5). The CPU can
detect block erase completion by analyzing the
output data of the STS pin or status register bit SR.7.

When the block erase is complete, status register bit
SR.5 should be checked. If a block erase error is
detected, the status register should be cleared before
system software attempts corrective actions. The CUI
remains in read status register mode until a new
command is issued.

This two-step command sequence of set-up followed
by execution ensures that block contents are not
accidentally erased. An invalid Block Erase command
sequence will result in both status register bits SR.4
and SR.5 being set to "1". Also, reliable block erasure
can only occur when V

CC1/2

and V

PPH1

. In

the absence of this high voltage, block contents are
protected against erasure. If block erase is attempted
while V

PPLK

, SR.3 and SR.5 will be set to "1".

Successful block erase requires that the
corresponding block lock-bit be cleared or if set, that
WP#=V

. If block erase is attempted when the

corresponding block lock-bit is set and WP#=V

SR.1 and SR.5 will be set to "1".

4.7 Full Chip Erase Command

This command followed by a confirm command
(D0H) erases all of the unlocked blocks. A full chip

erase setup is first written, followed by a full chip
erase confirm. After a confirm command is written,
device erases the all unlocked blocks from block 0 to
Block 63 block by block. This command sequence
requires appropriate sequencing. Block
preconditioning, erase and verify are handled
internally by the WSM (invisible to the system). After
the two-cycle full chip erase sequence is written, the
device automatically outputs status register data
when read (see Figure 6). The CPU can detect full
chip erase completion by analyzing the output data of
the STS pin or status register bit SR.7.

When the full chip erase is complete, status register
bit SR.5 should be checked. If erase error is
detected, the status register should be cleared before
system software attempts corrective actions. The CUI
remains in read status register mode until a new
command is issued. If error is detected on a block
during full chip erase operation, WSM stops erasing
the block and begin to erase the next block. Reading
the block valid status by issuing Read ID Codes
command or Query command informs which blocks
failed to its erase.

This two-step command sequence of set-up followed
by execution ensures that block contents are not
accidentally erased. An invalid Full Chip Erase
command sequence will result in both status register
bits SR.4 and SR.5 being set to "1". Also, reliable full
chip erasure can only occur when V

CC1/2

and

PPH1

. In the absence of this high voltage, block

contents are protected against erasure. If full chip
erase is attempted while V

PPLK

, SR.3 and SR.5

will be set to "1". When WP#=V

, all blocks are

erased independent of block lock-bits status. When
WP#=V

, only unlocked blocks are erased. Full chip

erase can not be suspended.

sharp

LHF32K10

Rev. 1.55

4.8 Word/Byte Write Command

Word/byte write is executed by a two-cycle command
sequence. Word/Byte Write setup (standard 40H or
alternate 10H) is written, followed by a second write
that specifies the address and data (latched on the
rising edge of WE#). The WSM then takes over,
controlling the word/byte write and write verify
algorithms internally. After the word/byte write
sequence is written, the device automatically outputs
status register data when read (see Figure 7). The
CPU can detect the completion of the word/byte write
event by analyzing the STS pin or status register bit
SR.7.

When word/byte write is complete, status register bit
SR.4 should be checked. If word/byte write error is
detected, the status register should be cleared. The
internal WSM verify only detects errors for "1"s that
do not successfully write to "0"s. The CUI remains in
read status register mode until it receives another
command.

Reliable word/byte writes can only occur when
V

CC1/2

and V

PPH1

. In the absence of this

high voltage, memory contents are protected against
word/byte writes. If word/byte write is attempted while
V

PPLK

, status register bits SR.3 and SR.4 will be

set to "1". Successful word/byte write requires that
the corresponding block lock-bit be cleared or, if set,
that WP#=V

. If word/byte write is attempted when

the corresponding block lock-bit is set and WP#=V

SR.1 and SR.4 will be set to "1". Word/byte write
operations with V

<WP#<V

produce spurious

results and should not be attempted.

4.9 Multi Word/Byte Write Command

Multi word/byte write is executed by at least four-
cycle or up to 35-cycle command sequence. Up to
32 bytes in x8 mode (16 words in x16 mode) can be
loaded into the buffer and written to the Flash Array.
First, multi word/byte write setup (E8H) is written with
the write address. At this point, the device
automatically outputs extended status register data
(XSR) when read (see Figure 8, 9). If extended
status register bit XSR.7 is 0, no Multi Word/Byte
Write command is available and multi word/byte write
setup which just has been written is ignored. To retry,

continue monitoring XSR.7 by writing multi word/byte
write setup with write address until XSR.7 transitions
to 1. When XSR.7 transitions to 1, the device is ready
for loading the data to the buffer. A word/byte count
(N)-1 is written with write address. After writing a
word/byte count(N)-1, the device automatically turns
back to output status register data. The word/byte
count (N)-1 must be less than or equal to 1FH in x8
mode (0FH in x16 mode). On the next write, device
start address is written with buffer data. Subsequent
writes provide additional device address and data,
depending on the count. All subsequent address
must lie within the start address plus the count. After
the final buffer data is written, write confirm (D0H)
must be written. This initiates WSM to begin copying
the buffer data to the Flash Array. An invalid Multi
Word/Byte Write command sequence will result in
both status register bits SR.4 and SR.5 being set to
"1". For additional multi word/byte write, write another
multi word/byte write setup and check XSR.7. The
Multi Word/Byte Write command can be queued
while WSM is busy as long as XSR.7 indicates "1",
because LH28F320S5NS-L90 has two buffers. If an
error occurs while writing, the device will stop writing
and flush next multi word/byte write command loaded
in multi word/byte write command. Status register bit
SR.4 will be set to "1". No multi word/byte write
command is available if either SR.4 or SR.5 are set
to "1". SR.4 and SR.5 should be cleared before
issuing multi word/byte write command. If a multi
word/byte write command is attempted past an erase
block boundary, the device will write the data to Flash
Array up to an erase block boundary and then stop
writing. Status register bits SR.4 and SR.5 will be set
to "1".

Reliable multi byte writes can only occur when
V

CC1/2

and V

PPH1

. In the absence of this

high voltage, memory contents are protected against
multi word/byte writes. If multi word/byte write is
attempted while V

PPLK

, status register bits SR.3

and SR.4 will be set to "1". Successful multi
word/byte write requires that the corresponding block
lock-bit be cleared or, if set, that WP#=V

. If multi

byte write is attempted when the corresponding block
lock-bit is set and WP#=V

, SR.1 and SR.4 will be

set to "1".

sharp

LHF32K10

Rev. 1.55

4.10 Block Erase Suspend Command

The Block Erase Suspend command allows block-
erase interruption to read or (multi) word/byte-write
data in another block of memory. Once the block-
erase process starts, writing the Block Erase
Suspend command requests that the WSM suspend
the block erase sequence at a predetermined point in
the algorithm. The device outputs status register data
when read after the Block Erase Suspend command
is written. Polling status register bits SR.7 and SR.6
can determine when the block erase operation has
been suspended (both will be set to "1"). STS will
also transition to High Z. Specification t

WHRH2

defines

the block erase suspend latency.

At this point, a Read Array command can be written
to read data from blocks other than that which is
suspended. A (Multi) Word/Byte Write command
sequence can also be issued during erase suspend
to program data in other blocks. Using the (Multi)
Word/Byte Write Suspend command (see Section
4.11), a (multi) word/byte write operation can also be
suspended. During a (multi) word/byte write operation
with block erase suspended, status register bit SR.7
will return to "0" and the STS (if set to RY/BY#)
output will transition to V

. However, SR.6 will

remain "1" to indicate block erase suspend status.

The only other valid commands while block erase is
suspended are Read Status Register and Block
Erase Resume. After a Block Erase Resume
command is written to the flash memory, the WSM
will continue the block erase process. Status register
bits SR.6 and SR.7 will automatically clear and STS
will return to V

. After the Erase Resume command

is written, the device automatically outputs status
register data when read (see Figure 10). V

must

remain at V

PPH1

(the same V

level used for block

erase) while block erase is suspended. RP# must
also remain at V

. Block erase cannot resume until

(multi) word/byte write operations initiated during
block erase suspend have completed.

4.11 (Multi) Word/Byte Write Suspend

Command

The (Multi) Word/Byte Write Suspend command
allows (multi) word/byte write interruption to read data
in other flash memory locations. Once the (multi)
word/byte write process starts, writing the (Multi)
Word/Byte Write Suspend command requests that
the WSM suspend the (multi) word/byte write
sequence at a predetermined point in the algorithm.
The device continues to output status register data
when read after the (Multi) Word/Byte Write Suspend
command is written. Polling status register bits SR.7
and SR.2 can determine when the (multi) word/byte
write operation has been suspended (both will be set
to "1"). STS will also transition to High Z.
Specification t

WHRH1

defines the (multi) word/byte

write suspend latency.

At this point, a Read Array command can be written
to read data from locations other than that which is
suspended. The only other valid commands while
(multi) word/byte write is suspended are Read Status
Register and (Multi) Word/Byte Write Resume. After
(Multi) Word/Byte Write Resume command is written
to the flash memory, the WSM will continue the
(multi) word/byte write process. Status register bits
SR.2 and SR.7 will automatically clear and STS will
return to V

. After the (Multi) Word/Byte Write

command is written, the device automatically outputs
status register data when read (see Figure 11). V

must remain at V

PPH1

(the same V

level used for

(multi) word/byte write) while in (multi) word/byte
write suspend mode. WP# must also remain at V

sharp

LHF32K10

Rev. 1.55

4.12 Set Block Lock-Bit Command

A flexible block locking and unlocking scheme is
enabled via block lock-bits. The block lock-bits gate
program and erase operations With WP#=V

individual block lock-bits can be set using the Set
Block Lock-Bit command. See Table 13 for a
summary of hardware and software write protection
options.

Set block lock-bit is executed by a two-cycle
command sequence. The set block lock-bit setup
along with appropriate block or device address is
written followed by either the set block lock-bit
confirm (and an address within the block to be
locked). The WSM then controls the set block lock-bit
algorithm. After the sequence is written, the device
automatically outputs status register data when read
(see Figure 12). The CPU can detect the completion
of the set block lock-bit event by analyzing the STS
pin output or status register bit SR.7.

When the set block lock-bit operation is complete,
status register bit SR.4 should be checked. If an error
is detected, the status register should be cleared.
The CUI will remain in read status register mode until
a new command is issued.

This two-step sequence of set-up followed by
execution ensures that block lock-bits are not
accidentally set. An invalid Set Block Lock-Bit
command will result in status register bits SR.4 and
SR.5 being set to "1". Also, reliable operations occur
only when V

CC1/2

and V

PPH1

. In the

absence of this high voltage, block lock-bit contents
are protected against alteration.

A successful set block lock-bit operation requires
WP#=V

. If it is attempted with WP#=V

, SR.1 and

SR.4 will be set to "1" and the operation will fail. Set
block lock-bit operations with WP#<V

produce

spurious results and should not be attempted.

4.13 Clear Block Lock-Bits Command

All set block lock-bits are cleared in parallel via the
Clear Block Lock-Bits command. With WP#=V

block lock-bits can be cleared using only the Clear
Block Lock-Bits command. See Table 13 for a
summary of hardware and software write protection
options.

Clear block lock-bits operation is executed by a two-
cycle command sequence. A clear block lock-bits
setup is first written. After the command is written, the
device automatically outputs status register data
when read (see Figure 13). The CPU can detect
completion of the clear block lock-bits event by
analyzing the STS Pin output or status register bit
SR.7.

When the operation is complete, status register bit
SR.5 should be checked. If a clear block lock-bit error
is detected, the status register should be cleared.
The CUI will remain in read status register mode until
another command is issued.

This two-step sequence of set-up followed by
execution ensures that block lock-bits are not
accidentally cleared. An invalid Clear Block Lock-Bits
command sequence will result in status register bits
SR.4 and SR.5 being set to "1". Also, a reliable clear
block lock-bits operation can only occur when
V

CC1/2

and V

PPH1

. If a clear block lock-bits

operation is attempted while V

PPLK

, SR.3 and

SR.5 will be set to "1". In the absence of this high
voltage, the block lock-bits content are protected
against alteration. A successful clear block lock-bits
operation requires WP#=V

. If it is attempted with

WP#=V

, SR.1 and SR.5 will be set to "1" and the

operation will fail. Clear block lock-bits operations
with V

<RP# produce spurious results and should

not be attempted.

If a clear block lock-bits operation is aborted due to
V

or V

transitioning out of valid range or RP#

active transition, block lock-bit values are left in an
undetermined state. A repeat of clear block lock-bits
is required to initialize block lock-bit contents to
known values.

sharp

LHF32K10

Rev. 1.55

4.14 STS Configuration Command

The Status (STS) pin can be configured to different
states using the STS Configuration command. Once
the STS pin has been configured, it remains in that
configuration until another configuration command is
issued, the device is powered down or RP# is set to
V

. Upon initial device power-up and after exit from

deep power-down mode, the STS pin defaults to
RY/BY# operation where STS low indicates that the
WSM is busy. STS High Z indicates that the WSM is
ready for a new operation.

To reconfigure the STS pin to other modes, the STS
Configuration is issued followed by the appropriate
configuration code. The three alternate configurations
are all pulse mode for use as a system interrupt. The
STS Configuration command functions independently
of the V

voltage and RP# must be V

Table 12. STS Configuration Coding Description
Configuration

Bits

Effects

00H

Set STS pin to default level mode
(RY/BY#). RY/BY# in the default
level-mode of operation will indicate
WSM status condition.

01H

Set STS pin to pulsed output signal
for specific erase operation. In this
mode, STS provides low pulse at
the completion of BLock Erase,
Full Chip Erase and Clear Block
Lock-bits operations.

02H

Set STS pin to pulsed output signal
for a specific write operation. In this
mode, STS provides low pulse at
the completion of (Multi) Byte Write
and Set Block Lock-bit operation.

03H

Set STS pin to pulsed output signal
for specific write and erase
operation. STS provides low pulse
at the completion of Block Erase,
Full Chip Erase, (Multi) Word/Byte
Write and Block Lock-bit
Configuration operations.

Table 13. Write Protection Alternatives

Operation

Block

Lock-Bit

WP#

Effect

Block Erase,

or V

Block Erase and (Multi) Word/Byte Write Enabled

(Multi) Word/Byte
Write

Block is Locked. Block Erase and (Multi) Word/Byte Write
Disabled

Block Lock-Bit Override. Block Erase and (Multi) Word/Byte
Write Enabled

Full Chip Erase

0,1

All unlocked blocks are erased, locked blocks are not erased

All blocks are erased

Set Block Lock-Bit

Set Block Lock-Bit Disabled

Set Block Lock-Bit Enabled

Clear Block Lock-Bits

Clear Block Lock-Bits Disabled

Clear Block Lock-Bits Enabled

sharp

LHF32K10

Rev. 1.55

Table 14. Status Register Definition

WSMS

BESS

ECBLBS

WSBLBS

VPPS

WSS

DPS

SR.7 = WRITE STATE MACHINE STATUS
1 = Ready
0 = Busy

SR.6 = BLOCK ERASE SUSPEND STATUS
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed

SR.5 = ERASE AND CLEAR BLOCK LOCK-BITS

STATUS

1 = Error in Erase or Clear Blocl Lock-Bits
0 = Successful Erase or Clear Block Lock-Bits

SR.4 = WRITE AND SET BLOCK LOCK-BIT STATUS
1 = Error in Write or Set Block Lock-Bit
0 = Successful Write or Set Block Lock-Bit

SR.3 = V

STATUS

1 = V

Low Detect, Operation Abort

0 = V

SR.2 = WRITE SUSPEND STATUS
1 = Write Suspended
0 = Write in Progress/Completed

SR.1 = DEVICE PROTECT STATUS
1 = Block Lock-Bit and/or WP# Lock Detected,

Operation Abort

0 = Unlock

SR.0 = RESERVED FOR FUTURE ENHANCEMENTS

NOTES:

Check STS or SR.7 to determine block erase, full chip
erase, (multi) word/byte write or block lock-bit
configuration completion.
SR.6-0 are invalid while SR.7="0".

If both SR.5 and SR.4 are "1"s after a block erase, full
chip erase, (multi) word/byte write, block lock-bit
configuration or STS configuration attempt, an improper
command sequence was entered.

SR.3 does not provide a continuous indication of V

level. The WSM interrogates and indicates the V

level

only after block erase, full chip erase, (multi) word/byte
write or block lock-bit configuration command
sequences. SR.3 is not guaranteed to reports accurate
feedback only when V

PPH1

SR.1 does not provide a continuous indication of block
lock-bit values. The WSM interrogates block lock-bit,
and WP# only after block erase, full chip erase, (multi)
word/byte write or block lock-bit configuration command
sequences. It informs the system, depending on the
attempted operation, if the block lock-bit is set and/or
WP# is not V

. Reading the block lock configuration

codes after writing the Read Identifier Codes command
indicates block lock-bit status.

SR.0 is reserved for future use and should be masked
out when polling the status register.

Table 14.1. Extended Status Register Definition

SMS

XSR.7 = STATE MACHINE STATUS
1 = Multi Word/Byte Write available
0 = Multi Word/Byte Write not available

XSR.6-0=RESERVED FOR FUTURE ENHANCEMENTS

NOTES:

After issue a Multi Word/Byte Write command: XSR.7
indicates that a next Multi Word/Byte Write command is
available.

XSR.6-0 is reserved for future use and should be
masked out when polling the extended status register.

sharp

Bus

Operation

Command

Comments

Write

Read

Standby

Erase Setup

Erase

Confirm

Data=20H

Addr=Within Block to be Erased

Data=D0H

Addr=Within Block to be Erased

Status Register Data

Check SR.7

1=WSM Ready

0=WSM Busy

Repeat for subsequent block erasures.

Full status check can be done after each block erase or after a sequence of

block erasures.

Write FFH after the last operation to place device in read array mode.

Bus

Operation

Command

Comments

Standby

1=V

Error Detect

1=Device Protect Detect

Check SR.4,5

SR.5,SR.4,SR.3 and SR.1 are only cleared by the Clear Status

before full status is checked.

If error is detected, clear the Status Register before attempting

retry or other error recovery.

Check SR.5

1=Block Erase Error

Standby

Check SR.3

Check SR.1

WP#=V

,Block Lock-Bit is Set

Only required for systems

implementing lock-bit configuration

Both 1=Command Sequence Error

FULL STATUS CHECK PROCEDURE

Read Status Register

Data(See Above)

SR.3=

Range Error

Device Protect Error

Command Sequence

Error

Block Erase Error

SR.1=

SR.4,5=

SR.5=

Block Erase Successful

Start

Write 20H,

Block Address

Write D0H,

Block Address

Read Status

SR.7=

Suspend

Block Erase

Yes

Suspend Block

Erase Loop

Full Status

Check if Desired

Block Erase

Complete

Write 70H

Read Status

SR.7=

Write

Read

Read Status

Data=70H

Addr=X

Standby

Status Register Data

Check SR.7

1=WSM Ready

0=WSM Busy

LHF32K10

Rev. 1.55

Figure 5. Automated Block Erase Flowchart

sharp

Bus

Operation

Command

Comments

Write

Read

Standby

Full Chip Erase

Confirm

Data=30H

Addr=X

Data=D0H

Addr=X

Status Register Data

Check SR.7

1=WSM Ready

0=WSM Busy

Full status check can be done after each full chip erase.

Write FFH after the last operation to place device in read array mode.

Bus

Operation

Command

Comments

Standby

1=V

Error Detect

Check SR.4,5

SR.5,SR.4,SR.3 and SR.1 are only cleared by the Clear Status

before full status is checked.

If error is detected, clear the Status Register before attempting

retry or other error recovery.

Check SR.5

1=Full Chip Erase Error

Standby

Check SR.3

Both 1=Command Sequence Error

FULL STATUS CHECK PROCEDURE

Read Status Register

Data(See Above)

SR.3=

Range Error

Command Sequence

Error

Full Chip Erase Error

SR.4,5=

SR.5=

Full Chip Erase

Successful

Start

Write 30H

Write D0H

Read Status

SR.7=

Full Status

Check if Desired

Full Chip Erase

Complete

Write 70H

Read Status

SR.7=

Write

Read

Read Status

Data=70H

Addr=X

Standby

Status Register Data

Check SR.7

1=WSM Ready

0=WSM Busy

Full Chip Erase

Setup

LHF32K10

Rev. 1.55

Figure 6. Automated Full Chip Erase Flowchart

sharp

Bus

Operation

Command

Comments

Write

Read

Standby

Setup Word/Byte

Word/Byte Write

Data=40H or 10H

Addr=Location to Be Written

Data=Data to Be Written

Addr=Location to Be Written

Status Register Data

Check SR.7

1=WSM Ready

0=WSM Busy

Repeat for subsequent word/byte writes.

SR full status check can be done after each word/byte write, or after a sequence of

word/byte writes.

Write FFH after the last word/byte write operation to place device in

read array mode.

Bus

Operation

Command

Comments

1=V

Error Detect

1=Device Protect Detect

SR.4,SR.3 and SR.1 are only cleared by the Clear Status Register

command in cases where multiple locations are written before

full status is checked.

If error is detected, clear the Status Register before attempting

retry or other error recovery.

Check SR.4

1=Data Write Error

Standby

Check SR.3

Check SR.1

WP#=V

,Block Lock-Bit is Set

Only required for systems

implementing lock-bit configuration

Start

Write 40H or 10H,

Address

Write Word/Byte

Data and Address

Read

Status Register

SR.7=

Suspend

Word/Byte

Yes

Suspend Word/Byte

Write Loop

Full Status

Check if Desired

Word/byte Write

Complete

FULL STATUS CHECK PROCEDURE

Read Status Register

Data(See Above)

SR.3=

Range Error

Device Protect Error

Word/byte Write Error

SR.1=

SR.4=

Word/Byte Write

Write 70H

Read Status

SR.7=

Write

Read

Read Status

Data=70H

Addr=X

Standby

Status Register Data

Check SR.7

1=WSM Ready

0=WSM Busy

Write

Successful

Write

LHF32K10

Rev. 1.55

Figure 7. Automated Word/byte Write Flowchart

sharp

Bus

Operation

Command

Comments

Write

Data=Word or Byte Count (N)-1

Addr=Start Address

Data=Buffer Data

Addr=Start Address

Check SR.7

1=WSM Ready

0=WSM Busy

SR full status check can be done after each multi word/byte write,

or after a sequence of multi word/byte writes.

Write FFH after the last multi word/byte write operation to place device in

read array mode.

Start

Write Word or Byte Count (N)-1,

Start Address

Write Buffer Data,

Start Address

X=0

X = N

Suspend

Multi Word/Byte

Yes

Suspend Multi Word/Byte

Write Loop

Full Status

Check if Desired

Write E8H,

Read Extend

Status Register

XSR.7=

Write

Read

Data=E8H

Addr=Start Address

Standby

Extended Status Register Data

Check XSR.7

1=Multi Word/Byte Write Ready

0=Multi Word/Byte Write Busy

Start Address

Write Buffer Data,

Device Address

X=X+1

Abort Buffer

Write Commnad?

Write Another

Block Address

Abort

Multi Word/Byte Write

Write D0H

Another

Write ?

Buffer

Read Status

SR.7=

Complete

Yes

Multi Word/Byte Write

Write

Data=Buffer Data

Addr=Device Address

Standby

Write

Read

Data=D0H

Addr=X

Status Register Data

1. Byte or word count values on DQ

0-7

are loaded into the count register.

2. Write Buffer contents will be programmed at the start address.

3. Align the start address on a Write Buffer boundary for maximum

programming performance.

4.The device aborts the Multi Word/Byte Write command if the current address is

outside of the original block address.

5.The Status Register indicates an "improper command sequence" if the Multi

Word/Byte command is aborted. Follow this with a Clear Status Register command.

(Note2,3)

(Note1)

(Note4,5)

Multi Word/Byte Write

Write Buffer

Time Out

Yes

Setup

Write

LHF32K10

Rev. 1.6

Figure 8. Automated Multi Word/Byte Write Flowchart

sharp

Bus

Operation

Command

Comments

1=V

Error Detect

1=Device Protect Detect

SR.5,SR.4,SR.3 and SR.1 are only cleared by the Clear Status Register

command in cases where multiple locations are written before

full status is checked.

If error is detected, clear the Status Register before attempting

retry or other error recovery.

Check SR.4

1=Data Write Error

Standby

Check SR.3

Check SR.1

WP#=V

,Block Lock-Bit is Set

Only required for systems

implementing lock-bit configuration

FULL STATUS CHECK PROCEDURE FOR

Read Status Register

SR.3=

Range Error

Device Protect Error

Multi Word/Byte Write

SR.1=

SR.4=

Multi Word/Byte Write

Command Sequence

SR.4,5=

Error

MULTI WORD/BYTE WRITE OPERATION

Successful

Check SR.4,5

Both 1=Command Sequence Error

Standby

Error

LHF32K10

Rev. 1.55

Figure 9. Full Status Check Procedure for Automated Multi Word/Byte Write

sharp

Start

Write 60H,

Block Address

Write 01H,

Block Address

Read

Status Register

SR.7=

Full Status

Check if Desired

Complete

Set Block Lock-Bit

FULL STATUS CHECK PROCEDURE

Read Status Register

Data(See Above)

SR.3=

Range Error

Device Protect Error

Command Sequence

Error

Set Block Lock-Bit Error

SR.1=

SR.4,5=

SR.4=

Set Block Lock-Bit

Bus

Operation

Command

Comments

Write

Read

Standby

Data=60H

Addr=Block Address

Data=01H,

Addr=Block Address

Status Register Data

Check SR.7

1=WSM Ready

0=WSM Busy

Repeat for subsequent block lock-bit set operations.

Full status check can be done after each block lock-bit set operation

or after a sequence of block lock-bit set operations.

Write FFH after the last block lock-bit set operation to place device in

read array mode.

Set Block

Lock-Bit Setup

Set Block

Lock-Bit Confirm

Bus

Operation

Command

Comments

Standby

1=V

Error Detect

1=Device Protect Detect

Check SR.4,5

Sequence Error

SR.5,SR.4,SR.3 and SR.1 are only cleared by the Clear Status

full status is checked.

If error is detected, clear the Status Register before attempting

retry or other error recovery.

Check SR.4

1=Set Block Lock-Bit Error

Standby

Check SR.3

Check SR.1

WP#=V

Both 1=Command

Successful

LHF32K10

Rev. 1.55

Figure 12. Set Block Lock-Bit Flowchart

sharp

Start

Write 60H

Write D0H

Read

Status Register

SR.7=

Full Status

Check if Desired

Complete

Clear Block Lock-Bits

FULL STATUS CHECK PROCEDURE

Read Status Register

Data(See Above)

SR.3=

Range Error

Device Protect Error

Command Sequence

Error

Clear Block Lock-Bits

SR.1=

SR.4,5=

SR.5=

Clear Block Lock-Bits

Error

Successful

Bus

Operation

Command

Comments

Write

Read

Standby

Data=60H

Addr=X

Data=D0H

Addr=X

Status Register Data

Check SR.7

1=WSM Ready

0=WSM Busy

Write FFH after the Clear Block Lock-Bits operation to

place device in read array mode.

Clear Block

Lock-Bits Setup

Clear Block

Lock-Bits Confirm

Bus

Operation

Command

Comments

Standby

1=V

Error Detect

1=Device Protect Detect

Check SR.4,5

Sequence Error

SR.5,SR.4,SR.3 and SR.1 are only cleared by the Clear Status

If error is detected, clear the Status Register before attempting

retry or other error recovery.

Check SR.5

1=Clear Block Lock-Bits Error

Standby

Check SR.3

Check SR.1

Both 1=Command

WP#=V

LHF32K10

Rev. 1.55

Figure 13. Clear Block Lock-Bits Flowchart

sharp

LHF32K10

Rev. 1.55

5 DESIGN CONSIDERATIONS

5.1 Three-Line Output Control

The device will often be used in large memory arrays.
SHARP provides three control inputs to
accommodate multiple memory connections. Three-
Line control provides for:

a. Lowest possible memory power dissipation.

b. Complete assurance that data bus contention will

not occur.

To use these control inputs efficiently, an address
decoder should enable CE# while OE# should be
connected to all memory devices and the system's
READ# control line. This assures that only selected
memory devices have active outputs while
deselected memory devices are in standby mode.
RP# should be connected to the system
POWERGOOD signal to prevent unintended writes
during system power transitions. POWERGOOD
should also toggle during system reset.

5.2 STS and Block Erase, Full Chip

Erase, (Multi) Word/Byte Write and
Block Lock-Bit Configuration Polling

STS is an open drain output that should be
connected to V

by a pullup resistor to provide a

hardware method of detecting block erase, full chip
erase, (multi) word/byte write and block lock-bit
configuration completion. In default mode, it
transitions low after block erase, full chip erase,
(multi) word/byte write or block lock-bit configuration
commands and returns to V

when the WSM has

finished executing the internal algorithm. For
alternate STS pin configurations, see the
Configuration command.

STS can be connected to an interrupt input of the
system CPU or controller. It is active at all times.

STS, in default mode, is also High-Z when the device
is in block erase suspend (with (multi) word/byte write
inactive), (multi) word/byte write suspend or deep
power-down modes.

5.3 Power Supply Decoupling

Flash memory power switching characteristics require
careful device decoupling. System designers are
interested in three supply current issues; standby
current levels, active current levels and transient
peaks produced by falling and rising edges of CE#
and OE#. Transient current magnitudes depend on
the device outputs' capacitive and inductive loading.
Two-line control and proper decoupling capacitor
selection will suppress transient voltage peaks. Each
device should have a 0.1 µF ceramic capacitor
connected between its V

and GND and between its

and GND. These high-frequency, low inductance

capacitors should be placed as close as possible to
package leads. Additionally, for every eight devices,
a 4.7 µF electrolytic capacitor should be placed at the
array's power supply connection between V

and

GND. The bulk capacitor will overcome voltage
slumps caused by PC board trace inductance.

5.4 V

Trace on Printed Circuit Boards

Updating flash memories that reside in the target
system requires that the printed circuit board
designer pay attention to the V

Power supply trace.

The V

pin supplies the memory cell current for

block erase, full chip erase, (multi) word/byte write
and block lock-bit configuration. Use similar trace
widths and layout considerations given to the V

power bus. Adequate V

supply traces and

decoupling will decrease V

voltage spikes and

overshoots.

sharp

LHF32K10

Rev. 1.55

5.5 V

, V

, RP# Transitions

Block erase, full chip erase, (multi) word/byte write
and block lock-bit configuration are not guaranteed if
V

falls outside of a valid V

PPH1

range, V

falls

outside of a valid V

CC1/2

range, or RP#=V

. If V

error is detected, status register bit SR.3 is set to "1"
along with SR.4 or SR.5, depending on the attempted
operation. If RP# transitions to V

during block

erase, full chip erase, (multi) word/byte write or block
lock-bit configuration, STS(if set to RY/BY# mode)
will remain low until the reset operation is complete.
Then, the operation will abort and the device will
enter deep power-down. The aborted operation may
leave data partially altered. Therefore, the command
sequence must be repeated after normal operation is
restored. Device power-off or RP# transitions to V

clear the status register.

The CUI latches commands issued by system
software and is not altered by V

or CE# transitions

or WSM actions. Its state is read array mode upon
power-up, after exit from deep power-down or after
V

transitions below V

LKO

After block erase, full chip erase, (multi) word/byte
write or block lock-bit configuration, even after V

transitions down to V

PPLK

, the CUI must be placed in

read array mode via the Read Array command if
subsequent access to the memory array is desired.

5.6 Power-Up/Down Protection

The device is designed to offer protection against
accidental block and full chip erasure, (multi)
word/byte writing or block lock-bit configuration during
power transitions. Upon power-up, the device is
indifferent as to which power supply (V

or V

)

powers-up first. Internal circuitry resets the CUI to
read array mode at power-up.

A system designer must guard against spurious
writes for V

voltages above V

LKO

when V

active. Since both WE# and CE# must be low for a
command write, driving either to V

will inhibit writes.

The CUI's two-step command sequence architecture
provides added level of protection against data
alteration.

In-system block lock and unlock capability prevents
inadvertent data alteration. The device is disabled
while RP#=V

regardless of its control inputs state.

5.7 Power Dissipation

When designing portable systems, designers must
consider battery power consumption not only during
device operation, but also for data retention during
system idle time. Flash memory's nonvolatility
increases usable battery life because data is retained
when system power is removed.

In addition, deep power-down mode ensures
extremely low power consumption even when system
power is applied. For example, portable computing
products and other power sensitive applications that
use an array of devices for solid-state storage can
consume negligible power by lowering RP# to V

standby or sleep modes. If access is again needed,
the devices can be read following the t

PHQV

and

PHWL

wake-up cycles required after RP# is first

raised to V

. See AC Characteristics

Read Only

and Write Operations and Figures 17, 18, 19, 20 for
more information.

sharp

LHF32K10

Rev. 1.55

6 ELECTRICAL SPECIFICATIONS

6.1 Absolute Maximum Ratings*

Operating Temperature

During Read, Erase, Write and
Block Lock-Bit Configuration ........0°C to +70°C

(1)

Temperature under Bias............... -10°C to +80°C

Storage Temperature........................ -65°C to +125°C

Voltage On Any Pin

(except V

, V

)............... -0.5V to V

+0.5V

(2)

Suply Voltage ............................-0.2V to +7.0V

(2)

Update Voltage during

Erase, Write and
Block Lock-Bit Configuration ......-0.2V to +7.0V

(2)

Output Short Circuit Current ........................ 100mA

(3)

*WARNING: Stressing the device beyond the
"Absolute Maximum Ratings" may cause permanent
damage. These are stress ratings only. Operation
beyond the "Operating Conditions" is not
recommended and extended exposure beyond the
"Operating Conditions" may affect device reliability.

NOTES:
1. Operating temperature is for commercial

temperature product defined by this specification.

2. All specified voltages are with respect to GND.

Minimum DC voltage is -0.5V on input/output pins
and -0.2V on V

and V

pins. During

transitions, this level may undershoot to -2.0V for
periods <20ns. Maximum DC voltage on
input/output pins and V

is V

+0.5V which,

during transitions, may overshoot to V

+2.0V for

periods <20ns.

3. Output shorted for no more than one second. No

more than one output shorted at a time.

6.2 Operating Conditions

Temperature and V

Operating Conditions

Symbol

Parameter

Min.

Max.

Unit

Test Condition

Operating Temperature

+70

°C

Ambient Temperature

CC1

Supply Voltage (5V±0.25V)

4.75

5.25

CC2

Supply Voltage (5V±0.5V)

4.50

5.50

6.2.1 CAPACITANCE

(1)

=+25°C, f=1MHz

Symbol

Parameter

Typ.

Max.

Unit

Condition

Input Capacitance

=0.0V

OUT

Output Capacitance

OUT

=0.0V

NOTE:
1. Sampled, not 100% tested.

sharp

AC test inputs are driven at 3.0V for a Logic "1" and 0.0V for a Logic "0." Input timing begins, and output timing ends, at 1.5V.

Input rise and fall times (10% to 90%) <10 ns.

3.0

0.0

INPUT

TEST POINTS

OUTPUT

1.5

AC test inputs are driven at V

(2.4 V

TTL

) for a Logic "1" and V

(0.45 V

TTL

) for a Logic "0." Input timing begins at V

(2.0 V

TTL

) and V

(0.8 V

TTL

). Output timing ends at V

and V

. Input rise and fall times (10% to 90%) <10 ns.

2.4

0.45

INPUT

0.8

2.0

TEST POINTS

2.0

0.8

OUTPUT

1.3V

1N914

DEVICE

UNDER

TEST

OUT

Includes Jig

=3.3k

Capacitance

LHF32K10

Rev. 1.6

6.2.2 AC INPUT/OUTPUT TEST CONDITIONS

Figure 14. Transient Input/Output Reference Waveform for V

=5V±0.25V

(High Speed Testing Configuration)

Figure 15. Transient Input/Output Reference Waveform for V

=5V±0.5V

(Standard Testing Configuration)

Test Configuration Capacitance Loading Value

Test Configuration

(pF)

=5V±0.25V

=5V±0.5V

100

Figure 16. Transient Equivalent Testing

Load Circuit

sharp

LHF32K10

Rev. 1.55

6.2.3 DC CHARACTERISTICS

DC Characteristics

=5V

Test

Symbol

Parameter

Notes

Typ.

Max.

Unit

Conditions

Input Load Current

±1

µA

Max.

or GND

Output Leakage Current

±10

µA

Max.

OUT

or GND

CCS

Standby Current

1,3,6

100

µA

CMOS Inputs
V

Max.

CE#=RP#=V

±0.2V

TTL Inputs
V

Max.

CE#=RP#=V

CCD

Deep Power-Down

Current

µA

RP#=GND±0.2V
I

OUT

(STS)=0mA

CCR

Read Current

1,5,6

CMOS Inputs
V

Max.,

CE#=GND
f=8MHz, I

OUT

=0mA

TTL Inputs
V

Max., CE#=V

f=8MHz, I

OUT

=0mA

CCW

Write Current

((Multi) W/B Write or Set Block
Lock Bit)

1,7

=5.0V±0.5V

CCE

Erase Current

(Block Erase, Full Chip Erase,
Clear Block Lock Bits)

1,7

=5.0V±0.5V

CCWS

CCES

Write or Block Erase

Suspend Current

1,2

CE#=V

PPS

Standby Current

±2

±15

µA

PPR

Read Current

200

µA

PPD

Deep Power-Down

Current

0.1

µA

RP#=GND±0.2V

PPW

Write Current

((Multi) W/B Write or Set Block
Lock Bit)

1,7

=5.0V±0.5V

PPE

Erase Current

(Block Erase, Full Chip Erase,
Clear Block Lock Bits)

1,7

=5.0V±0.5V

PPWS

PPES

Write or Block Erase

Suspend Current

200

µA

PPH1

sharp

LHF32K10

Rev. 1.6

DC Characteristics (Continued)

=5V

Test

Symbol

Parameter

Notes

Min.

Max.

Unit

Conditions

Input Low Voltage

-0.5

0.8

Input High Voltage

2.0

+0.5

Output Low Voltage

3,7

0.45

Min.

=5.8mA

OH1

Output High Voltage
(TTL)

3,7

2.4

Min.

=-2.5mA

OH2

Output High Voltage
(CMOS)

3,7

0.85

Min.

=-2.5mA

-0.4

Min.

=-100µA

PPLK

Lockout during Normal

Operations

4,7

1.5

PPH1

during Write or Erase

Operations

4.5

5.5

LKO

Lockout Voltage

2.0

NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at nominal V

voltage and T

=+25°C.These

currents are valid for all product versions (packages and speeds).

2. I

CCWS

and I

CCES

are specified with the device de-selected. If read or byte written while in erase suspend mode,

the device's current draw is the sum of I

CCWS

or I

CCES

and I

CCR

or I

CCW

, respectively.

3. Includes STS.
4. Block erases, full chip erases, (multi) word/byte writes and block lock-bit configurations are inhibited when

PPLK

, and not guaranteed in the range between V

PPLK

(max.) and V

PPH1

(min.) and above V

PPH1

(max.).

5. Automatic Power Savings (APS) reduces typical I

CCR

to 1mA at 5V V

in static operation.

6. CMOS inputs are either V

±0.2V or GND±0.2V. TTL inputs are either V

or V

7. Sampled, not 100% tested.

sharp

LHF32K10

Rev. 1.55

6.2.4 AC CHARACTERISTICS - READ-ONLY OPERATIONS

(1)

=5V±0.5V, 5V±0.25V, T

=0°C to +70°C

=5V±0.25V LH28F320S5-L90

(5)

Versions

(4)

=5V±0.5V

LH28F320S5-

L100

(6)

Sym.

Parameter

Notes

Min.

Max.

Min.

Max.

Unit

AVAV

Read Cycle Time

100

AVQV

Address to Output Delay

100

ELQV

CE# to Output Delay

100

PHQV

RP# High to Output Delay

400

GLQV

OE# to Output Delay

ELQX

CE# to Output in Low Z

EHQZ

CE# High to Output in High Z

GLQX

OE# to Output in Low Z

GHQZ

OE# High to Output in High Z

Output Hold from Address, CE# or
OE# Change, Whichever Occurs First

FLQV

FHQV

BYTE# to Output Delay

100

FLQZ

BYTE# to Output in High Z

ELFL

ELFH

CE# Low to BYTE# High or Low

NOTES:
1. See AC Input/Output Reference Waveform for maximum allowable input slew rate.
2. OE# may be delayed up to t

ELQV

-t

GLQV

after the falling edge of CE# without impact on t

ELQV

3. Sampled, not 100% tested.
4. See Ordering Information for device speeds (valid operational combinations).
5. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (High Speed

Configuration) for testing characteristics.

6. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (Standard

Configuration) for testing characteristics.

sharp

LHF32K10

Rev. 1.55

6.2.5 AC CHARACTERISTICS - WRITE OPERATIONS

(1)

=5V±0.5V, 5V±0.25V, T

=0°C to +70°C

=5V±0.25V LH28F320S5-L90

(6)

Versions

(5)

=5V±0.5V

LH28F320S5-

L100

(7)

Sym.

Parameter

Notes

Min.

Max.

Min.

Max.

Unit

AVAV

Write Cycle Time

100

PHWL

RP# High Recovery to WE# Going
Low

µs

ELWL

CE# Setup to WE# Going Low

WLWH

WE# Pulse Width

SHWH

WP# V

Setup to WE# Going High

100

VPWH

Setup to WE# Going High

100

AVWH

Address Setup to WE# Going High

DVWH

Data Setup to WE# Going High

WHDX

Data Hold from WE# High

WHAX

Address Hold from WE# High

WHEH

CE# Hold from WE# High

WHWL

WE# Pulse Width High

WHRL

WE# High to STS Going Low

WHGL

Write Recovery before Read

QVVL

Hold from Valid SRD, STS High Z

2,4

QVSL

WP# V

Hold from Valid SRD, STS

High Z

2,4

NOTES:
1. Read timing characteristics during block erase, full chip erase, (multi) wrod/byte write and block lock-bit

configuration operations are the same as during read-only operations. Refer to AC Characteristics for read-only
operations.

2. Sampled, not 100% tested.
3. Refer to Table 4 for valid A

and D

for block erase, full chip erase, (multi) word/byte write or block lock-bit

configuration.

4. V

should be held at V

PPH1

until determination of block erase, full chip erase, (multi) word/byte write or block

lock-bit configuration success (SR.1/3/4/5=0).

5. See Ordering Information for device speeds (valid operational combinations).
6. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (High Seed

Configuration) for testing characteristics.

7. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (Standard

Configuration) for testing characteristics.

sharp

LHF32K10

Rev. 1.55

6.2.6 ALTERNATIVE CE#-CONTROLLED WRITES

(1)

=5V±0.5V, 5V±0.25V, T

=0°C to +70°C

=5V±0.25V LH28F320S5-L90

(6)

Versions

(5)

=5V±0.5V

LH28F320S5-

L100

(7)

Sym.

Parameter

Notes

Min.

Max.

Min.

Max.

Unit

AVAV

Write Cycle Time

100

PHEL

RP# High Recovery to CE# Going Low

µs

WLEL

WE# Setup to CE# Going Low

ELEH

CE# Pulse Width

SHEH

WP# V

Setup to CE# Going High

100

VPEH

Setup to CE# Going High

100

AVEH

Address Setup to CE# Going High

DVEH

Data Setup to CE# Going High

EHDX

Data Hold from CE# High

EHAX

Address Hold from CE# High

EHWH

WE# Hold from CE# High

EHEL

CE# Pulse Width High

EHRL

CE# High to STS Going Low

EHGL

Write Recovery before Read

QVVL

Hold from Valid SRD, STS High Z

2,4

QVSL

WP# V

Hold from Valid SRD, STS

High Z

2,4

NOTES:
1. In systems where CE# defines the write pulse width (within a longer WE# timing waveform), all setup, hold and

inactive WE# times should be measured relative to the CE# waveform.

2. Sampled, not 100% tested.
3. Refer to Table 4 for valid A

and D

for block erase, full chip erase, (multi) word/byte write or block lock-bit

configuration.

4. V

should be held at V

PPH1

until determination of block erase, full chip erase, (multi) word/byte write or block

lock-bit configuration success (SR.1/3/4/5=0).

5. See Ordering Information for device speeds (valid operational combinations).
6. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (High Seed

Configuration) for testing characteristics.

7. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (Standard

Configuration) for testing characteristics.

sharp

RP#(P)

PLPH

PLRH

(A)Reset During Read Array Mode

(B)Reset During Block Erase, Full Chip Erase, (Multi) Word/Byte Write

High Z

PLPH

STS(R)

RP#(P)

5VPH

or Block Lock-Bit Configuretion

(C)V

Power Up Timing

LHF32K10

Rev. 1.55

6.2.7 RESET OPERATIONS

Figure 21. AC Waveform for Reset Operation

Reset AC Specifications

(1)

=5V

Symbol

Parameter

Notes

Min.

Max.

Unit

PLPH

RP# Pulse Low Time
(If RP# is tied to V

, this specification is not applicable)

100

PLRH

RP# Low to Reset during Block Erase, Full Chip Erase,
(Multi) Word/Byte Write or Block Lock-Bit Configuration

2,3

13.1

µs

5VPH

at 4.5V to RP# High

100

NOTES:
1. These specifications are valid for all product versions (packages and speeds).
2. If RP# is asserted while a block erase, full chip erase, (multi) word/byte write or block lock-bit configuration

operation is not executing, the reset will complete within 100ns.

3. A reset time, t

PHQV

, is required from the latter of STS going High Z or RP# going high until outputs are valid.

4. When the device power-up, holding RP# low minimum 100ns is required after V

has been in predefined range

and also has been in stable there.

sharp

LHF32K10

Rev. 1.55

6.2.8 BLOCK ERASE, FULL CHIP ERASE, (MULTI) WORD/BYTE WRITE AND BLOCK

LOCK-BIT CONFIGURATION PERFORMANCE

(3,4)

=5V±0.5V, 5V±0.25V, T

=0°C to +70°C

=4.5V-5.5V

Sym.

Parameter

Notes

Typ.

(1)

Max.

Unit

WHQV1

EHQV1

Word/Byte Write Time
(using W/B write, in word mode)

9.24

120

µs

WHQV1

EHQV1

Word/Byte Write Time
(using W/B write, in byte mode)

9.24

120

µs

Word/Byte Write Time
(using multi word/byte write)

120

µs

Block Write Time
(using W/B write, in word mode)

0.31

3.7

Block Write Time
(using W/B write, in byte mode)

0.61

7.5

Block Write Time
(using multi word/byte write)

0.13

1.5

WHQV2

EHQV2

Block Erase Time

0.34

Full Chip Erase Time

21.8

640

WHQV3

EHQV3

Set Block Lock-Bit Time

9.24

120

µs

WHQV4

EHQV4

Clear Block Lock-Bits Time

0.34

WHRH1

EHRH1

Write Suspend Latency Time to Read

5.6

µs

WHRH2

EHRH2

Erase Suspend Latency Time to Read

9.4

13.1

µs

NOTES:
1. Typical values measured at T

=+25°C and nominal voltages. Assumes corresponding block lock-bits are not

set. Subject to change based on device characterization.

2. Excludes system-level overhead.
3. These performance numbers are valid for all speed versions.
4. Sampled but not 100% tested.

sharp

Rev. 1.10

A-1 RECOMMENDED OPERATING CONDITIONS

A-1.1 At Device Power-Up

AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up.

If the timing in the figure is ignored, the device may not operate correctly.

Figure A-1. AC Timing at Device Power-Up

For the AC specifications t

, t

in the figure, refer to the next page. See the "ELECTRICAL SPECIFICATIONS"

described in specifications for the supply voltage range, the operating temperature and the AC specifications not shown in
the next page.

2VPH

GND

(min)

RP#

(P)

PHQV

CCW

GND

CCWH1/2

(V)

CE#

(E)

WE#

(W)

OE#

(G)

WP#

(S)

(D/Q)

DATA

High Z

Valid

Output

ELQV

GLQV

(A)

ADDRESS

Valid

(RST#)

)

Address

AVQV

*1 t

5VPH

for the device in 5V operations.

*2 To prevent the unwanted writes, system designers should consider the V

CCW

) switch, which connects V

CCW

)

to GND during read operations and V

CCWH1/2

PPH1/2

) during write or erase operations.

PPH1/2

)

See the application note AP-007-SW-E for details.

sharp

SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.

Suggested applications (if any) are for standard use; See Important Restrictions for limitations on special applications. See Limited
Warranty for SHARP's product warranty. The Limited Warranty is in lieu, and exclusive of, all other warranties, express or implied.
ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND
FITNESS FOR A PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED. In no event will SHARP be liable, or in any way responsible,
for any incidental or consequential economic or property damage.

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Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: LHF32K10

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: LHF32K10