Integrated Circuits Group
LRS13A0
Stacked Chip
128M (x16) Flash and 16M (x16) SRAM
(Model No.:
LRS13A0)
Spec No.:
MFM2-J14Y10A
Issue Date:
March 17, 2003
P
RELIMINARY
P
RODUCT
S
PECIFICATIONS
L R S 1 3 A 0
Handle this document carefully for it contains material protected by international copyright law.
Any reproduction, full or in part, of this material is prohibited without the express written permission
of the company.
When using the products covered herein, please observe the conditions written herein and the
precautions outlined in the following paragraphs. In no event shall the company be liable for
any damages resulting from failure to strictly adhere to these conditions and precautions.
(1) The products covered herein are designed and manufactured for the following application areas.
When using the products covered herein for the equipment listed in Paragraph (2), even for the
following application areas, be sure to observe the precautions given in Paragraph (2). Never use
the products for the equipment listed in Paragraph (3).
Office electronics
Instrumentation and measuring equipment
Machine tools
Audiovisual equipment
Home appliance
Communication equipment other than for trunk lines
(2) Those contemplating using the products covered herein for the following equipment
which demands high reliability, should first contact a sales representative of the company and
then accept responsibility for incorporating into the design fail-safe operation, redundancy, and
other appropriate measures for ensuring reliability and safety of the equipment and the overall
system.
Control and safety devices for airplanes, trains, automobiles, and other transportation
equipment
Mainframe computers
Traffic control systems
Gas leak detectors and automatic cutoff devices
Rescue and security equipment
Other safety devices and safety equipment, etc.
(3) Do not use the products covered herein for the following equipment which demands extremely
high performance in terms of functionality, reliability, or accuracy.
Aerospace equipment
Communications equipment for trunk lines
Control equipment for the nuclear power industry
Medical equipment related to life support, etc.
(4) Please direct all queries and comments regarding the interpretation of the above three
Paragraphs to a sales representative of the company.
Please direct all queries regarding the products covered herein to a sales representative of the
company.
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L R S 1 3 A 0
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Contents
1. Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3. Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1
Bus Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2
Simultaneous Operation Modes Allowed with Four Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5. Command Definitions for Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.1
Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.2
Identifier Codes for Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.3
Functions of Block Lock and Block Lock-Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.4
Block Locking State Transitions upon Command Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.5
Block Locking State Transitions upon F-WP Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6. Status Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7. Memory Map for Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.1
Memory Map - F
1
Selected (F
1
-CE = "V
IL
", F
2
-CE = "V
IH
") . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.2
Memory Map - F
2
Selected (F
1
-CE = "V
IH
", F
2
-CE = "V
IL
") . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
8. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
9. Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
10. Pin Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
11. DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
12. AC Electrical Characteristics for Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
12.1 AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
12.2 Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
12.3 Write Cycle (F-WE / F-CE Controlled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
12.4 Block Erase, Advanced Factory Program, (Page Buffer) Program Performance . . . . . . . . . . . . . . . . . . . . . . . . 23
12.5 Flash Memory AC Characteristics Timing Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
12.6 Reset Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
13. AC Electrical Characteristics for SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
13.1 AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
13.2 Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
13.3 Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
13.4 SRAM AC Characteristics Timing Chart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
14. Data Retention Characteristics for SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
15. Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
16. Flash Memory Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
17. Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
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L R S 1 3 A 0
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1. Description
The LRS13A0 is a combination memory organized as 4,194,304 x16 bit flash memory, 4,194,304 x16 bit flash memory and
1,048,576 x16 bit static RAM in one package.
Features
- Power supply
1.7V to 1.95V
- Operating temperature
-25C to +85C
- Not designed or rated as radiation hardened
- 72pin CSP (LCSP072-P-0811) plastic package
- Flash memory has P-type bulk silicon, and SRAM has P-type bulk silicon
Flash Memory
- F
1
: 64M (x16) bit Flash Memory, F
2
: 64M (x16) bit Flash Memory
- Access Time
70 ns
(Max.)
- Power supply current for each Chip (The current for F-V
CC
pin and F-V
PP
pin)
Read
25 mA
(Max. t
CYCLE
= 200ns, CMOS Input)
Word write
60 mA
(Max.)
Block erase
30 mA
(Max.)
Reset Power-Down
50 A
(Max. F-RST = GND 0.2V,
I
OUT
(F-RY/BY) = 0mA)
Standby
50 A
(Max. F-CE = F-RST = F-V
CC
0.2V)
- Optimized Array Blocking Architecture for each Chip
Eight 4K-word Parameter Blocks
One-hundred and twenty-seven 32K-word Main Blocks
F
1
: Bottom Parameter Location, F
2
: Top Parameter Location
- Extended Cycling Capability
100,000 Block Erase Cycles
(F-V
PP
= 0.9V to 1.95V)
1,000 Block Erase Cycles and total 80 hours
(F-V
PP
= 11.7V to 12.3V)
- Enhanced Automated Suspend Options
Word Write Suspend to Read
Block Erase Suspend to Word Write
Block Erase Suspend to Read
* In the following pages, F
1
, F
2
and F are defined as F
1
: 64M (x16) bit Flash, F
2
: 64M (x16) bit Flash, F: both Flashes in common.
SRAM
- Access Time
70 ns
(Max.)
- Power Supply current
Operating current
25 mA
(Max. t
RC
, t
WC
= Min.)
Standby current
15 A
(Max.)
Data retention current
8 A
(Max. S-V
CC
= 1.2V)
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L R S 1 3 A 0
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2. Pin Configuration
NC
NC
GND
A
16
A
11
A
8
A
10
A
15
A
14
A
9
DQ
15
A
13
A
12
1
2
3
4
5
6
7
8
S-WE
F-WE
F-RST
T
1
F-A
21
F-
RY/BY
S-A
17
T
2
DQ
12
DQ
13
DQ
6
S-CE
2
F-WP
S-LB
F-V
PP
S-UB S-OE
A
19
DQ
11
T
4
DQ
9
T
3
DQ
10
DQ
8
A
B
C
D
E
F
G
A
18
F-A
17
A
7
A
6
A
3
A
2
GND
9
DQ
14
DQ
4
S-V
CC
DQ
2
DQ
0
A
1
NC
10
DQ
7
DQ
5
F-V
CC
DQ
3
DQ
1
S-CE
1
NC
11
NC
12
NC
H
NC
NC
A
5
A
4
A
0
GND
F-OE F
2
-CE
NC
NC
F
1
-CE
INDEX
(TOP View)
F-A
20
Note) From T
1
to T
4
pins are needed to be open.
Two NC pins at the corner are connected.
Do not float any GND pins.
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L R S 1 3 A 0
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Pin
Description
Type
A
0
to A
16
, A
18
, A
19
Address Inputs (Common)
Input
F-A
17
, F-A
20,
F-A
21
Address Inputs (Flash)
Input
S-A
17
Address Input (SRAM)
Input
F
1,2
-CE
Chip Enable Input (Flash)
Input
S-CE
1
, S-CE
2
Chip Enable Input (SRAM)
Input
F-WE
Write Enable Input (Flash)
Input
S-WE
Write Enable Input (SRAM)
Input
F-OE
Output Enable Input (Flash)
Input
S-OE
Output Enable Input (SRAM)
Input
S-LB
SRAM Byte Enable Input (DQ
0
to DQ
7
)
Input
S-UB
SRAM Byte Enable Input (DQ
8
to DQ
15
)
Input
F-RST
Reset Power Down Input (Flash)
Block erase and Write : V
IH
Read : V
IH
Reset Power Down : V
IL
Input
F-WP
Write Protect Input (Flash)
When F-WP is V
IL
, locked-down blocks cannot be unlocked. Erase or
program operation can be executed to the blocks which are not locked and
locked-down. When F-WP is V
IH
, lock-down is disabled.
Input
F-RY/BY
Ready/Busy Output (Flash)
During an Erase or Write operation : V
OL
Block Erase and Write Suspend : High-Z (High impedance)
Open Drain
Output
DQ
0
to DQ
15
Data Inputs and Outputs (Common)
Input/Output
F-V
CC
Power Supply (Flash)
Power
S-V
CC
Power Supply (SRAM)
Power
F-V
PP
Monitoring Power Supply Voltage (Flash)
Block Erase and Write : F-V
PP
= V
PPH1/2
All Blocks Locked : F-V
PP
< V
PPLK
Input/Power
GND
GND (Common)
Power
NC
Non Connection
-
T
1
to T
4
Test pins (Should be all open)
-
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L R S 1 3 A 0
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3. Truth Table
3.1 Bus Operation
(1)
Notes:
1. L = V
IL
, H = V
IH
, X = H or L, High-Z = High impedance. Refer to the DC Characteristics.
2. Command writes involving block erase (page buffer) program are reliably executed when F-V
PP
= V
PPH1/2
and F-V
CC
= 1.7V to 1.95V.
Command writes involving advanced factory program is reliably executed when F-V
PP
= V
PPH2
and F-V
CC
= 1.7V to
1.95V.
Block erase, advanced factory program, (page buffer) program with F-V
PP
< V
PPH1/2
(Min.) produce spurious results and
should not be attempted.
3. Never hold F-OE low and F-WE low at the same timing.
4. Refer to Section 5. Command Definitions for Flash Memory valid D
IN
during a write operation.
5. F-WP set to V
IL
or V
IH
.
6. Electricity consumption of Flash Memory is lowest when F-RST = GND 0.2V.
7. Never hold F
1
-CE low and F
2
-CE low at the same timing.
8. Read Bus operation or Write Bus operation is not simultaneously operated to F
1
and F
2
.
9. Flash Read Mode
10. SRAM Standby Mode
11.S-UB, S-LB Control Mode
Flash
SRAM
Notes F-CE
(7)
F-RST F-OE F-WE S-CE
1
S-CE
2
S-OE S-WE S-LB
S-UB DQ
0
to DQ
15
Read
Standby
3,5,8
L
H
L
H
(10)
X
X
(10)
(9)
Output
Disable
5,8
H
High - Z
Write
2,3,4,5,8
L
D
IN
Standby
Read
5,6
H
H
X
X
L
H
L
H
(11)
Output
Disable
5,6
X
H
H
H
High - Z
H
H
X
X
Write
5,6
X
L
(11)
Reset Power
Down
Read
5,6
X
L
X
X
L
H
L
H
(11)
Output
Disable
5,6
X
H
H
H
High - Z
H
H
X
X
Write
5,6
X
L
(11)
Standby
Standby
5
H
H
X
X
(10)
X
X
(10)
High - Z
Reset Power
Down
5,6
X
L
Mode
Address
DQ
0
to DQ
15
Read Array
X
D
OUT
Read Identifier Codes
See 5.2
See 5.2
Read Query
Refer to the Appendix Refer to the Appendix
S-CE
1
S-CE
2
S-LB
S-UB
S-LB S-UB
DQ
0
to DQ
7
DQ
8
to DQ
15
H
X
X
X
L
L
D
OUT
/D
IN
D
OUT
/D
IN
X
L
X
X
L
H
D
OUT
/D
IN
High - Z
X
X
H
H
H
L
High - Z
D
OUT
/D
IN
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L R S 1 3 A 0
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3.2 Simultaneous Operation Modes Allowed with Four Planes
(1, 2, 3)
Notes:
1. "X" denotes the operation available.
2. Configurative Partition Dual Work Restrictions:
Only one partition can be erased or programmed at a time - no command queuing.
Commands must be written to an address within the block targeted by that command.
3. This table shows operation which can be performed by only the selected chip, not during 2 chips of F
1
and F
2
.
IF ONE
PARTITION IS:
THEN THE MODES ALLOWED IN THE OTHER PARTITION IS:
Read
Array
Read ID
Read
Status
Read
Query
Word
Program
Page
Buffer
Program
Block
Erase
Advanced
Factory
Program
Program
Suspend
Block
Erase
Suspend
Read Array
X
X
X
X
X
X
X
X
X
Read ID
X
X
X
X
X
X
X
X
X
Read Status
X
X
X
X
X
X
X
X
X
X
Read Query
X
X
X
X
X
X
X
X
X
Word Program
X
X
X
X
X
Page Buffer
Program
X
X
X
X
X
Block Erase
X
X
X
X
Advanced
Factory Program
X
Program
Suspend
X
X
X
X
X
Block Erase
Suspend
X
X
X
X
X
X
X
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4. Block Diagram
F
1
: 64M (x16) bit
Flash memory
16M (x16) bit
SRAM
S-A
17
S-CE
1
S-CE
2
S-OE
S-WE
S-LB
S-UB
S-V
CC
F-V
PP
F-V
CC
F
1
-CE
A
0
to A
16
, A
18
, A
19
DQ
0
to DQ
15
F-RY/BY
F-A
17
, F-A
20
, F-A
21
F-OE
F-WE
F-WP
F-RST
F
2
-CE
GND
F
2
: 64M (x16) bit
Flash memory
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5. Command Definitions for Flash Memory
(11)
5.1 Command Definitions
Notes:
1. Bus operations are defined in 3.1 Bus Operation.
2. The address which is written at the first bus cycle should be the same as the address which is written at the second bus
cycle.
X=Any valid address within the device.
PA=Address within the selected partition.
IA=Identifier codes address (See 5.2 Identifier Codes for Read Operation).
QA=Query codes address. Refer to the LH28F128BN series Appendix for details.
BA=Address within the block being erased, set/cleared block lock bit or set block lock-down bit.
WA=Address of memory location for the Program command or the first address for the Page Buffer Program command.
PCRC=Partition configuration register code presented on the address A
0
-A
15
.
3. ID=Data read from identifier codes (See 5.2 Identifier Codes for Read Operation).
QD=Data read from query database. Refer to the LH28F128BN series Appendix for details.
SRD=Data read from status register. See 6. Status Register Definition for a description of the status register bits.
WD=Data to be programmed at location WA. Data is latched on the rising edge of F-WE or F-CE (whichever goes high first).
N-1=N is the number of the words to be loaded into a page buffer.
4. Following the Read Identifier Codes command, read operations access manufacturer code, device code, block lock
configuration code, partition configuration register code (See 5.2 Identifier Codes for Read Operation).
The Read Query command is available for reading CFI (Common Flash Interface) information.
5. Block erase, advanced factory program or (page buffer) program cannot be executed when the selected block is locked.
Unlocked block can be erased or programmed when F-RST is V
IH
.
6. Either 40H or 10H are recognized by the CUI (Command User Interface) as the program setup.
7. Following the third bus cycle, inputs the program sequential address and write data of "N" times. Finally, input the any
valid address within the target partition to be programmed and the confirm command (D0H). Refer to the LH28F128BN
series Appendix for details.
Command
Bus
Cycles
Req'd
Notes
First Bus Cycle
Second Bus Cycle
Oper
(1)
Address
(2)
Data
Oper
(1)
Address
(2)
Data
(3)
Read Array
1
2
Write
PA
FFH
Read Identifier Codes
2
2,3,4
Write
PA
90H
Read
IA
ID
Read Query
2
2,3,4
Write
PA
98H
Read
QA
QD
Read Status Register
2
2,3
Write
PA
70H
Read
PA
SRD
Clear Status Register
1
2
Write
PA
50H
Block Erase
2
2,3,5
Write
BA
20H
Write
BA
D0H
Advanced Factory Program
2
2,5,9
Write
X
30H
Write
X
D0H
Program
2
2,3,5,6
Write
WA
40H or
10H
Write
WA
WD
Page Buffer Program
4
2,3,5,7
Write
WA
E8H
Write
WA
N-1
Block Erase and (Page Buffer)
Program Suspend
1
2,8,9
Write
PA
B0H
Block Erase and (Page Buffer)
Program Resume
1
2,8,9
Write
PA
D0H
Set Block Lock Bit
2
2
Write
BA
60H
Write
BA
01H
Clear Block Lock Bit
2
2,10
Write
BA
60H
Write
BA
D0H
Set Block Lock-down Bit
2
2
Write
BA
60H
Write
BA
2FH
Set Partition Configuration
Register
2
2,3
Write
PCRC
60H
Write
PCRC
04H
sharp
L R S 1 3 A 0
9
8. If the program operation in one partition is suspended and the erase operation in other partition is also suspended, the
suspended program operation should be resumed first, and then the suspended erase operation should be resumed next.
9. Advanced factory program operation can not be suspended.
10. Following the Clear Block Lock Bit command, block which is not locked-down is unlocked when F-WP is V
IL
.
When F-WP is V
IH
, lock-down bit is disabled and the selected block is unlocked regardless of lock-down configuration.
11. Commands other than those shown above are reserved by SHARP for future device implementations and should not be
used.
sharp
L R S 1 3 A 0
10
5.2 Identifier Codes for Read Operation
Notes:
1. Bottom parameter device has its parameter blocks in the plane 0 (The lowest address).
Top parameter device has its parameter blocks in the plane 3 (The highest address).
2. Block Address = The beginning location of a block address within the partition to which the Read Identifier Codes
command (90H) has been written.
DQ
15
-DQ
2
is reserved for future implementation.
3. PCRC=Partition Configuration Register Code.
4. The address A
21
-A
16
are shown in below table for reading the manufacturer, device, device configuration code.
The address to read the identifier codes is dependent on the partition which is selected when writing the Read Identifier
Codes command (90H).
See Chapter 6. Partition Configuration Register Definition (P.15) for the partition configuration register.
Identifier Codes for Read Operation on Partition Configuration (64M-bit device)
Code
Address
[A
15
-A
0
]
Data
[DQ
15
-DQ
0
]
Notes
Manufacturer Code
Manufacturer Code
0000H
00B0H
4
Device Code
64M Bottom Parameter Device Code (F
1
Selected)
64M Top Parameter Device Code (F
2
Selected)
0001H
00BBH (F
1
Selected)
00BAH (F
2
Selected)
2
Block Lock Configuration
Code
Block is Unlocked
Block
Address
+ 2
DQ
0
= 0
2
Block is Locked
DQ
0
= 1
2
Block is not Locked-Down
DQ
1
= 0
2
Block is Locked-Down
DQ
1
= 1
2
Device Configuration
Code
Partition Configuration Register
0006H
PCRC
3, 4
Partition Configuration Register
Address (64M-bit device)
[A
21
-A
16
]
PCR.10
PCR.9
PCR.8
0
0
0
00H
0
0
1
00H or 10H
0
1
0
00H or 20H
1
0
0
00H or 30H
0
1
1
00H or 10H or 20H
1
1
0
00H or 20H or 30H
1
0
1
00H or 10H or 30H
1
1
1
00H or 10H or 20H or 30H
sharp
L R S 1 3 A 0
11
5.3 Functions of Block Lock and Block Lock-Down
Notes:
1. DQ
0
= 1: a block is locked; DQ
0
= 0: a block is unlocked.
DQ
1
= 1: a block is locked-down; DQ
1
= 0: a block is not locked-down.
2. Erase and program are general terms, respectively, to express: block erase, advanced factory program and (page buffer)
program
operations.
3. At power-up or device reset, all blocks default to locked state and are not locked-down, that is, [001] (F-WP = 0) or [101]
(F-WP = 1), regardless of the states before power-off or reset operation.
4. When F-WP is driven to V
IL
in [110] state, the state changes to [011] and the blocks are automatically locked.
5.4 Block Locking State Transitions upon Command Write
(4)
Notes:
1. "Set Lock" means Set Block Lock Bit command, "Clear Lock" means Clear Block Lock Bit command and "Set Lock-
down" means Set Block Lock-Down Bit command.
2. When the Set Block Lock-Down Bit command is written to the unlocked block (DQ
0
= 0), the corresponding block is
locked-down and automatically locked at the same time.
3. "No Change" means that the state remains unchanged after the command written.
4. In this state transitions table, assumes that F-WP is not changed and fixed V
IL
or V
IH
.
Current State
Erase/Program Allowed
(2)
State
F-WP
DQ
1
(1)
DQ
0
(1)
State Name
[000]
0
0
0
Unlocked
Yes
[001]
(3)
0
0
1
Locked
No
[011]
0
1
1
Locked-down
No
[100]
1
0
0
Unlocked
Yes
[101]
(3)
1
0
1
Locked
No
[110]
(4)
1
1
0
Lock-down Disable
Yes
[111]
1
1
1
Lock-down Disable
No
Current State
Result after Lock Command Written (Next State)
State
F-WP
DQ
1
DQ
0
Set Lock
(1)
Clear Lock
(1)
Set Lock-down
(1)
[000]
0
0
0
[001]
No Change
[011]
(2)
[001]
0
0
1
No Change
(3)
[000]
[011]
[011]
0
1
1
No Change
No Change
No Change
[100]
1
0
0
[101]
No Change
[111]
(2)
[101]
1
0
1
No Change
[100]
[111]
[110]
1
1
0
[111]
No Change
[111]
(2)
[111]
1
1
1
No Change
[110]
No Change
sharp
L R S 1 3 A 0
12
5.5 Block Locking State Transitions upon F-WP Transition
(4)
Notes:
1. "F-WP = 0
1" means that F-WP is driven to V
IH
and "F-WP = 1
0" means that F-WP is driven to V
IL
.
2. State transition from the current state [011] to the next state depends on the previous state.
3. When F-WP is driven to V
IL
in [110] state, the state changes to [011] and the blocks are automatically locked.
4. In this state transitions table, assumes that lock configuration commands are not written in previous, current and next state.
Previous State
Current State
Result after F-WP Transition (Next State)
State
F-WP
DQ
1
DQ
0
F-WP = 0
1
(1)
F-WP = 1
0
(1)
-
[000]
0
0
0
[100]
-
-
[001]
0
0
1
[101]
-
[110]
(2)
[011]
0
1
1
[110]
-
Other than [110]
(2)
[111]
-
-
[100]
1
0
0
-
[000]
-
[101]
1
0
1
-
[001]
-
[110]
1
1
0
-
[011]
(3)
-
[111]
1
1
1
-
[011]
sharp
L R S 1 3 A 0
13
6. Status Register Definition
Status Register Definition
R
R
R
R
R
R
R
R
15
14
13
12
11
10
9
8
WSMS
BESS
BES
PBPS
VPPS
PBPSS
DPS
PPES
7
6
5
4
3
2
1
0
SR.15 - SR.8 = RESERVED FOR FUTURE
ENHANCEMENTS (R)
SR.7 = WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
SR.6 = BLOCK ERASE SUSPEND STATUS (BESS)
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
SR.5 = BLOCK ERASE STATUS (BES)
1 = Error in Block Erase
0 = Successful Block Erase
SR.4 = (PAGE BUFFER) PROGRAM STATUS (PBPS)
1 = Error in (Page Buffer) Program
0 = Successful (Page Buffer) Program
SR.3 = F-V
PP
STATUS (VPPS)
1 = F-V
PP
LOW Detect, Operation Abort
0 = F-V
PP
OK
SR.2 = (PAGE BUFFER) PROGRAM SUSPEND
STATUS (PBPSS)
1 = (Page Buffer) Program Suspended
0 = (Page Buffer) Program in Progress/Completed
SR.1 = DEVICE PROTECT STATUS (DPS)
1 = Erase or Program Attempted on a
Locked Block, Operation Abort
0 = Unlocked
SR.0 = PARTITION PROGRAM AND ERASE STATUS
(PPES)
1 = Another Partition is busy.
AFP: Program or Verify busy.
0 = Depending on status of SR.7.
The addressed partition is busy or no other partition is
busy.
AFP: Program or Verify done, AFP ready.
Notes:
Status Register indicates the status of the WSM (Write State
Machine).
Check SR.7 or F-RY/BY to determine block erase, (page
buffer) program completion. SR.6 - SR.1 are invalid while
SR.7= "0".
If both SR.5 and SR.4 are "1"s after a block erase, (page
buffer) program, set/clear block lock bit, set block lock-down
bit, set partition configuration register attempt, an improper
command sequence was entered.
SR.3 does not provide a continuous indication of F-V
PP
level.
The WSM interrogates and indicates the F-V
PP
level only after
Block Erase, (Page Buffer) Program command sequences.
SR.3 is not guaranteed to report accurate feedback when F-
V
PP
V
PPH1/2
or V
PPLK
.
SR.1 does not provide a continuous indication of block lock
bit. The WSM interrogates the block lock bit only after Block
Erase, (Page Buffer) Program command sequences. It informs
the system, depending on the attempted operation, if the block
lock bit is set. Reading the block lock configuration codes after
writing the Read Identifier Codes command indicates block
lock bit status.
SR.15 - SR.8 are reserved for future use and should be masked
out when polling the status register.
If SR.7="0" and SR.0="0", the addressed partition is busy and
no other partition is busy. In AFP Mode, it indicates that the
device is finished programming or verifying data or is ready
for data.
If SR.7="0" and SR.0="1", another partition is busy (the
addressed partition is not busy). In AFP Mode, it indicates that
the device is programming or verifying data.
If SR.7="1" and SR.0="0", no partition is busy. In AFP Mode,
it indicates that the device has exited AFP mode.
SR.7="1" and SR.0="1" will not occur.
sharp
L R S 1 3 A 0
14
Extended Status Register Definition
R
R
R
R
R
R
R
R
15
14
13
12
11
10
9
8
SMS
R
R
R
R
R
R
R
7
6
5
4
3
2
1
0
XSR.15-8 = RESERVED FOR FUTURE
ENHANCEMENTS (R)
XSR.7 = STATE MACHINE STATUS (SMS)
1 = Page Buffer Program available
0 = Page Buffer Program not available
XSR.6-0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
Notes:
After issue a Page Buffer Program command (E8H),
XSR.7="1" indicates that the entered command is accepted. If
XSR.7 is "0", the command is not accepted and a next Page
Buffer Program command (E8H) should be issued again to
check if page buffer is available or not.
XSR.15-8 and XSR.6-0 are reserved for future use and should
be masked out when polling the extended status register.
sharp
L R S 1 3 A 0
15
Partition Configuration Register Definition
Partition Configuration
R
R
R
R
R
PC2
PC1
PC0
15
14
13
12
11
10
9
8
R
R
R
R
R
R
R
R
7
6
5
4
3
2
1
0
PCR.15-11 = RESERVED FOR FUTURE
ENHANCEMENTS (R)
PCR.10-8 = PARTITION CONFIGURATION (PC2-0)
000 = No partitioning. Dual Work is not allowed.
001 = Plane1-3 are merged into one partition.
(default in a bottom parameter device)
010 = Plane 0-1 and Plane2-3 are merged into one
partition respectively.
100 = Plane 0-2 are merged into one partition.
(default in a top parameter device)
011 = Plane 2-3 are merged into one partition. There are
three partitions in this configuration. Dual work
operation is available between any two partitions.
110 = Plane 0-1 are merged into one partition. There are
three partitions in this configuration. Dual work
operation is available between any two partitions.
101 = Plane 1-2 are merged into one partition. There are
three partitions in this configuration. Dual work
operation is available between any two partitions.
111 = There are four partitions in this configuration.
Each plane corresponds to each partition
respectively. Dual work operation is available
between any two partitions.
PCR.7-0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
Notes:
After power-up or device reset, PCR10-8 (PC2-0) is set to
"001" in a bottom parameter device and "100" in a top
parameter device.
See the table below for more details.
PCR.15-11 and PCR.7-0 are reserved for future use and should
be masked out when checking the partition configuration
register.
PLANE1
PLANE0
PLANE2
PLANE3
PARTITION1
PLANE1
PLANE0
PLANE2
PLANE3
PARTITION0
PLANE1
PLANE0
PLANE2
PLANE3
PARTITION0
PLANE1
PLANE0
PLANE2
PLANE3
PARTITION0
PARTITION1
PARTITION1
PARTITION0
PLANE1
PLANE0
PLANE2
PLANE3
PARTITION1
PLANE1
PLANE0
PLANE2
PLANE3
PARTITION0
PLANE1
PLANE0
PLANE2
PLANE3
PARTITION0
PLANE1
PLANE0
PLANE2
PLANE3
PARTITION0
PARTITION1
PARTITION1
PARTITION0
PARTITION2
PARTITION3
PARTITION2
PARTITION2
PARTITION1
PARTITION2
0 0 0
0 0 1
0 1 0
1 0 0
0 1 1
1 1 0
1 0 1
1 1 1
PC2 PC1PC0
PARTITIONING FOR DUAL WORK
PARTITIONING FOR DUAL WORK
PC2 PC1PC0
sharp
L R S 1 3 A 0
16
7. Memory Map for Flash Memory
7.1 Memory Map - F
1
Selected (F
1
-CE = "V
IL
", F
2
-CE = "V
IH
")
6
5
4
3
2
1
0
7
4K-WORD
007000H - 007FFFH
4K-WORD
006000H - 006FFFH
4K-WORD
005000H - 005FFFH
4K-WORD
004000H - 004FFFH
4K-WORD
003000H - 003FFFH
4K-WORD
002000H - 002FFFH
4K-WORD
001000H - 001FFFH
4K-WORD
000000H - 000FFFH
PLANE2
(
UNIFORM
PLANE)
92
93
94
95
64
65
72
73
74
75
32K-WORD
278000H - 27FFFFH
32K-WORD
270000H - 277FFFH
32K-WORD
268000H - 26FFFFH
32K-WORD
260000H - 267FFFH
32K-WORD
258000H - 25FFFFH
32K-WORD
250000H - 257FFFH
32K-WORD
248000H - 24FFFFH
32K-WORD
240000H - 247FFFH
32K-WORD
238000H - 23FFFFH
32K-WORD
230000H - 237FFFH
32K-WORD
228000H - 22FFFFH
32K-WORD
220000H - 227FFFH
32K-WORD
218000H - 21FFFFH
32K-WORD
210000H - 217FFFH
32K-WORD
208000H - 20FFFFH
32K-WORD
200000H - 207FFFH
2F8000H - 2FFFFFH
2F0000H - 2F7FFFH
2E8000H - 2EFFFFH
2E0000H - 2E7FFFH
2D8000H - 2DFFFFH
2D0000H - 2D7FFFH
2C8000H - 2CFFFFH
2C0000H - 2C7FFFH
2B8000H - 2BFFFFH
2B0000H - 2B7FFFH
2A8000H - 2AFFFFH
2A0000H - 2A7FFFH
298000H - 29FFFFH
290000H - 297FFFH
288000H - 28FFFFH
280000H - 287FFFH
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
76
78
79
80
81
82
83
77
84
85
66
68
69
70
71
67
86
88
89
90
91
87
PLANE1
(
UNIFORM
PLANE)
BLOCK NUMBER ADDRESS RANGE
62
63
32
33
34
35
42
43
44
45
32K-WORD
178000H - 17FFFFH
32K-WORD
170000H - 177FFFH
32K-WORD
168000H - 16FFFFH
32K-WORD
160000H - 167FFFH
32K-WORD
158000H - 15FFFFH
32K-WORD
150000H - 157FFFH
32K-WORD
148000H - 14FFFFH
32K-WORD
140000H - 147FFFH
32K-WORD
138000H - 13FFFFH
32K-WORD
130000H - 137FFFH
32K-WORD
128000H - 12FFFFH
32K-WORD
120000H - 127FFFH
32K-WORD
118000H - 11FFFFH
32K-WORD
110000H - 117FFFH
32K-WORD
108000H - 10FFFFH
32K-WORD
100000H - 107FFFH
1F8000H - 1FFFFFH
1F0000H - 1F7FFFH
1E8000H - 1EFFFFH
1E0000H - 1E7FFFH
1D8000H - 1DFFFFH
1D0000H - 1D7FFFH
1C8000H - 1CFFFFH
1C0000H - 1C7FFFH
1B8000H - 1BFFFFH
1B0000H - 1B7FFFH
1A8000H - 1AFFFFH
1A0000H - 1A7FFFH
198000H - 19FFFFH
190000H - 197FFFH
188000H - 18FFFFH
180000H - 187FFFH
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
46
48
49
50
51
52
53
47
54
55
36
38
39
40
41
37
56
58
59
60
61
57
12
13
14
15
32K-WORD
078000H - 07FFFFH
32K-WORD
070000H - 077FFFH
32K-WORD
068000H - 06FFFFH
32K-WORD
060000H - 067FFFH
32K-WORD
058000H - 05FFFFH
32K-WORD
050000H - 057FFFH
32K-WORD
PLANE0
(
PARAMETER
PLANE)
048000H - 04FFFFH
32K-WORD
040000H - 047FFFH
32K-WORD
038000H - 03FFFFH
32K-WORD
030000H - 037FFFH
32K-WORD
028000H - 02FFFFH
32K-WORD
020000H - 027FFFH
32K-WORD
018000H - 01FFFFH
32K-WORD
010000H - 017FFFH
32K-WORD
008000H - 00FFFFH
0F8000H - 0FFFFFH
0F0000H - 0F7FFFH
0E8000H - 0EFFFFH
0E0000H - 0E7FFFH
0D8000H - 0DFFFFH
0D0000H - 0D7FFFH
0C8000H - 0CFFFFH
0C0000H - 0C7FFFH
0B8000H - 0BFFFFH
0B0000H - 0B7FFFH
0A8000H - 0AFFFFH
0A0000H - 0A7FFFH
098000H - 09FFFFH
090000H - 097FFFH
088000H - 08FFFFH
080000H - 087FFFH
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
16
18
19
20
21
22
23
17
24
25
8
9
10
11
26
28
29
30
31
27
127
128
129
130
131
132
133
32K-WORD
PLANE3
(
UNIFORM
PLANE)
3F8000H - 3FFFFFH
122
123
124
102
103
104
105
32K-WORD
378000H - 37FFFFH
32K-WORD
370000H - 377FFFH
32K-WORD
368000H - 36FFFFH
32K-WORD
360000H - 367FFFH
32K-WORD
358000H - 35FFFFH
32K-WORD
350000H - 357FFFH
32K-WORD
348000H - 34FFFFH
32K-WORD
340000H - 347FFFH
32K-WORD
338000H - 33FFFFH
32K-WORD
330000H - 337FFFH
32K-WORD
328000H - 32FFFFH
32K-WORD
320000H - 327FFFH
32K-WORD
318000H - 31FFFFH
32K-WORD
310000H - 317FFFH
32K-WORD
308000H - 30FFFFH
32K-WORD
300000H - 307FFFH
3F0000H - 3F7FFFH
3E8000H - 3EFFFFH
3E0000H - 3E7FFFH
3D8000H - 3DFFFFH
3D0000H - 3D7FFFH
3C8000H - 3CFFFFH
3C0000H - 3C7FFFH
3B8000H - 3BFFFFH
3B0000H - 3B7FFFH
3A8000H - 3AFFFFH
3A0000H - 3A7FFFH
398000H - 39FFFFH
390000H - 397FFFH
388000H - 38FFFFH
380000H - 387FFFH
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
106
108
109
110
111
112
113
107
114
115
96
98
99
100
101
97
116
118
119
120
121
117
125
126
134
BLOCK NUMBER ADDRESS RANGE
Bottom Parameter
sharp
L R S 1 3 A 0
17
7.2 Memory Map - F
2
Selected (F
1
-CE = "V
IH
", F
2
-CE = "V
IL
")
127
128
129
130
131
132
133
4K-WORD
3FF000H - 3FFFFFH
4K-WORD
3FE000H - 3FEFFFH
4K-WORD
3FD000H - 3FDFFFH
4K-WORD
3FC000H - 3FCFFFH
4K-WORD
3FB000H - 3FBFFFH
4K-WORD
3FA000H - 3FAFFFH
4K-WORD
PLANE3
(
PARAMETER
PLANE)
3F9000H - 3F9FFFH
3F8000H - 3F8FFFH
PLANE2
(
UNIFORM
PLANE)
0
1
2
3
4
5
12
13
14
15
32K-WORD
078000H - 07FFFFH
32K-WORD
070000H - 077FFFH
32K-WORD
068000H - 06FFFFH
32K-WORD
060000H - 067FFFH
32K-WORD
058000H - 05FFFFH
32K-WORD
050000H - 057FFFH
32K-WORD
PLANE0
(
UNIFORM
PLANE)
048000H - 04FFFFH
32K-WORD
040000H - 047FFFH
32K-WORD
038000H - 03FFFFH
32K-WORD
030000H - 037FFFH
32K-WORD
028000H - 02FFFFH
32K-WORD
020000H - 027FFFH
32K-WORD
018000H - 01FFFFH
32K-WORD
010000H - 017FFFH
32K-WORD
008000H - 00FFFFH
32K-WORD
000000H - 007FFFH
0F8000H - 0FFFFFH
0F0000H - 0F7FFFH
0E8000H - 0EFFFFH
0E0000H - 0E7FFFH
0D8000H - 0DFFFFH
0D0000H - 0D7FFFH
PLANE1
(
UNIFORM
PLANE)
0C8000H - 0CFFFFH
0C0000H - 0C7FFFH
0B8000H - 0BFFFFH
0B0000H - 0B7FFFH
0A8000H - 0AFFFFH
0A0000H - 0A7FFFH
098000H - 09FFFFH
090000H - 097FFFH
088000H - 08FFFFH
080000H - 087FFFH
BLOCK NUMBER ADDRESS RANGE
BLOCK NUMBER ADDRESS RANGE
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
16
18
19
20
21
22
23
17
24
25
6
8
9
10
11
7
26
28
29
30
31
27
62
63
32
33
34
35
42
43
44
45
32K-WORD
178000H - 17FFFFH
32K-WORD
170000H - 177FFFH
32K-WORD
168000H - 16FFFFH
32K-WORD
160000H - 167FFFH
32K-WORD
158000H - 15FFFFH
32K-WORD
150000H - 157FFFH
32K-WORD
148000H - 14FFFFH
32K-WORD
140000H - 147FFFH
32K-WORD
138000H - 13FFFFH
32K-WORD
130000H - 137FFFH
32K-WORD
128000H - 12FFFFH
32K-WORD
120000H - 127FFFH
32K-WORD
118000H - 11FFFFH
32K-WORD
110000H - 117FFFH
32K-WORD
108000H - 10FFFFH
32K-WORD
100000H - 107FFFH
1F8000H - 1FFFFFH
1F0000H - 1F7FFFH
1E8000H - 1EFFFFH
1E0000H - 1E7FFFH
1D8000H - 1DFFFFH
1D0000H - 1D7FFFH
1C8000H - 1CFFFFH
1C0000H - 1C7FFFH
1B8000H - 1BFFFFH
1B0000H - 1B7FFFH
1A8000H - 1AFFFFH
1A0000H - 1A7FFFH
198000H - 19FFFFH
190000H - 197FFFH
188000H - 18FFFFH
180000H - 187FFFH
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
46
48
49
50
51
52
53
47
54
55
36
38
39
40
41
37
56
58
59
60
61
57
92
93
94
95
64
65
72
73
74
75
32K-WORD
278000H - 27FFFFH
32K-WORD
270000H - 277FFFH
32K-WORD
268000H - 26FFFFH
32K-WORD
260000H - 267FFFH
32K-WORD
258000H - 25FFFFH
32K-WORD
250000H - 257FFFH
32K-WORD
248000H - 24FFFFH
32K-WORD
240000H - 247FFFH
32K-WORD
238000H - 23FFFFH
32K-WORD
230000H - 237FFFH
32K-WORD
228000H - 22FFFFH
32K-WORD
220000H - 227FFFH
32K-WORD
218000H - 21FFFFH
32K-WORD
210000H - 217FFFH
32K-WORD
208000H - 20FFFFH
32K-WORD
200000H - 207FFFH
2F8000H - 2FFFFFH
2F0000H - 2F7FFFH
2E8000H - 2EFFFFH
2E0000H - 2E7FFFH
2D8000H - 2DFFFFH
2D0000H - 2D7FFFH
2C8000H - 2CFFFFH
2C0000H - 2C7FFFH
2B8000H - 2BFFFFH
2B0000H - 2B7FFFH
2A8000H - 2AFFFFH
2A0000H - 2A7FFFH
298000H - 29FFFFH
290000H - 297FFFH
288000H - 28FFFFH
280000H - 287FFFH
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
76
78
79
80
81
82
83
77
84
85
66
68
69
70
71
67
86
88
89
90
91
87
122
123
124
102
103
104
105
32K-WORD
378000H - 37FFFFH
32K-WORD
370000H - 377FFFH
32K-WORD
368000H - 36FFFFH
32K-WORD
360000H - 367FFFH
32K-WORD
358000H - 35FFFFH
32K-WORD
350000H - 357FFFH
32K-WORD
348000H - 34FFFFH
32K-WORD
340000H - 347FFFH
32K-WORD
338000H - 33FFFFH
32K-WORD
330000H - 337FFFH
32K-WORD
328000H - 32FFFFH
32K-WORD
320000H - 327FFFH
32K-WORD
318000H - 31FFFFH
32K-WORD
310000H - 317FFFH
32K-WORD
308000H - 30FFFFH
32K-WORD
300000H - 307FFFH
3F0000H - 3F7FFFH
3E8000H - 3EFFFFH
3E0000H - 3E7FFFH
3D8000H - 3DFFFFH
3D0000H - 3D7FFFH
3C8000H - 3CFFFFH
3C0000H - 3C7FFFH
3B8000H - 3BFFFFH
3B0000H - 3B7FFFH
3A8000H - 3AFFFFH
3A0000H - 3A7FFFH
398000H - 39FFFFH
390000H - 397FFFH
388000H - 38FFFFH
380000H - 387FFFH
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
106
108
109
110
111
112
113
107
114
115
96
98
99
100
101
97
116
118
119
120
121
117
125
126
134
4K-WORD
Top Parameter
sharp
L R S 1 3 A 0
18
8. Absolute Maximum Ratings
Notes:
1. The maximum applicable voltage on any pins with respect to GND.
2. Except F-V
PP
.
3. -1.0V undershoot and V
CC
+1.0V overshoot are allowed when the pulse width is less than 20 nsec.
4. V
IN
should not be over 2.45V.
5. Applying 12V 0.3V to F-V
PP
during erase/write can only be done for a maximum of 1000 cycles on each block.
F-V
PP
may be connected to 12V 0.3V for total of 80 hours maximum. +12.6V overshoot is allowed when the pulse width
is less than 20 nsec.
9. Recommended DC Operating Conditions
(T
A
= -25C to +85C)
Notes:
1. V
CC
includes both F-V
CC
and S-V
CC
.
2. V
CC
is the lower of F-V
CC
or S-V
CC
.
3. Please contact your local Sharp when need to lower V
CC
/V
CCQ
to 1.65V.
10. Pin Capacitance
(1)
(T
A
= 25C, f = 1MHz)
Note:
1. Sampled but not 100% tested.
Symbol
Parameter
Notes
Ratings
Unit
V
CC
Supply voltage
1,2
-0.2
to
+2.3
V
V
IN
Input voltage
1,2,3,4
-0.2
to
V
CC
+0.3
V
T
A
Operating temperature
-25
to
+85
C
T
STG
Storage temperature
-65
to
+125
C
F-V
PP
F-V
PP
voltage
1,3,5
-0.2
to
+12.6
V
Symbol
Parameter
Notes
Min.
Typ.
Max.
Unit
V
CC
Supply Voltage
1,3
1.7
1.8
1.95
V
V
PP
F-V
PP
Voltage (Write Operation)
0.9
1.8
1.95
V
F-V
PP
Voltage (Read Operation)
0
1.95
V
V
IH
Input Voltage
2
1.4
V
CC
+0.2
V
V
IL
Input Voltage
-0.2
0.4
V
Symbol
Parameter
Notes
Min.
Typ.
Max.
Unit
Condition
C
IN
Input capacitance
20
pF
V
IN
= 0V
C
I/O
I/O capacitance
30
pF
V
I/O
= 0V
sharp
L R S 1 3 A 0
19
11. DC Electrical Characteristics
(1)
DC Electrical Characteristics
(T
A
= -25C to +85C, V
CC
= 1.7V to 1.95V)
Symbol
Parameter
Notes
Min.
Typ.
Max.
Unit
Test Conditions
I
LI
Input Leakage Current
2
A
V
IN
= V
CC
or GND
I
LO
Output Leakage Current
2
A
V
OUT
= V
CC
or GND
I
CCS
F-V
CC
Standby Current
2,11,12
16
100
A
F-V
CC
= F-V
CC
Max.,
F-CE = F-RST = F-V
CC
0.2V,
F-WP = F-V
CC
or GND
I
CCAS
F-V
CC
Automatic Power Savings
Current
2,5,8,11
16
100
A
F-V
CC
= F-V
CC
Max.,
F-CE = GND 0.2V,
F-WP = F-V
CC
or GND
I
CCD
F-V
CC
Reset Power-Down Current
2,11
16
100
A
F-RST = GND 0.2V
I
OUT
(F-RY/BY) = 0mA
I
CCR
Average F-V
CC
Read Current
Normal Mode
2,8,10,11
15
25
mA
F-V
CC
= F-V
CC
Max.,
F-CE = V
IL
, F-OE = V
IH
, f = 5MHz
I
OUT
= 0mA
Average F-V
CC
Read Current
Page Mode
8 Word Read
2,8,10,11
5
10
mA
I
CCW
F-V
CC
(Page Buffer) Program
Current
2,6,9,10,11
20
60
mA
F-V
PP
= V
PPH1
2,6,9,10,11
10
20
mA
F-V
PP
= V
PPH2
I
CCE
F-V
CC
Block Erase Current
2,6,9,10,11
10
30
mA
F-V
PP
= V
PPH1
2,6,9,10,11
4
10
mA
F-V
PP
= V
PPH2
I
CCWS
I
CCES
F-V
CC
(Page Buffer) Program or
Block Erase Suspend Current
2,3,10,11
10
200
A
F-CE = V
IH
I
PPS
I
PPR
F-V
PP
Standby or Read Current
2,7,10,11
4
10
A
F-V
PP
F-V
CC
I
PPW
F-V
PP
(Page Buffer) Program
Current
2,6,7,9,10,11
2
5
A
F-V
PP
= V
PPH1
2,6,7,9,10,11
10
30
mA
F-V
PP
= V
PPH2
I
PPE
F-V
PP
Block Erase Erase Current
2,6,7,9,10,11
2
5
A
F-V
PP
= V
PPH1
2,6,7,9,10,11
5
15
mA
F-V
PP
= V
PPH2
I
PPWS
F-V
PP
(Page Buffer) Program
Suspend Current
2,7,10,11
2
5
A
F-V
PP
= V
PPH1
2,7,10,11
10
200
A
F-V
PP
= V
PPH2
I
PPES
F-V
PP
Block Erase Suspend Current
2,7,10,11
2
5
A
F-V
PP
= V
PPH1
2,7,10,11
10
200
A
F-V
PP
= V
PPH2
sharp
L R S 1 3 A 0
20
DC Electrical Characteristics (Continue)
(T
A
= -25C to +85C, V
CC
= 1.7V to 1.95V)
Notes:
1. V
CC
includes both F-V
CC
and S-V
CC
.
2. I
CCWS
and I
CCES
are specified with the device de-selected. If read or (page buffer) program is executed while in block
erase suspend mode, the device's current draw is the sum of I
CCES
and I
CCR
or I
CCW
. If read is executed while in (page
buffer) program suspend mode, the device's current draw is the sum of I
CCWS
and I
CCR
.
3. I
CCWS
and I
CCES
are specified with the device de-selected. If read or (page buffer) program while in block erase suspend
mode, the device's current draw is the sum of I
CCWS
or I
CCES
and I
CCR
or I
CCW
, respectively.
4. Block erase, advanced factory program, (page buffer) program are inhibited when F-V
PP
V
PPLK
, and not guaranteed in
the range between V
PPLK
(max.) and V
PPH1
(min.) , between V
PPH1
(max.) and V
PPH2
(min.), and above V
PPH2
(max.).
5. The Automatic Power Savings (APS) feature automatically places the device in power save mode after read cycle
completion. Standard address access timings (t
AVQV
) provide new data when addresses are changed.
6. Sampled, not 100% tested.
7. F-V
PP
is not used for power supply pin. With F-V
PP
V
PPLK
, block erase, advanced factory program, (page buffer)
program cannot be executed and should not be attempted.
Applying 12V 0.3V to F-V
PP
provides fast erasing or fast programming mode. In this mode, F-V
PP
is power supply pin
and supplies the memory cell current for block erasing and (page buffer) programming. Use similar power supply trace
widths and layout considerations given to the V
CC
power bus.
Applying 12V 0.3V to F-V
PP
during erase/program can only be done for a maximum of 1000 cycles on each block.
F-V
PP
may be connected to 12V 0.3V for a total of 80 hours maximum.
8. Never hold F
1
-CE low and F
2
-CE low at the same timing.
9. F
1
and F
2
should not be operated at the same timing to Block erase, advanced factory program, (page buffer) program.
10. The operating current in dual work is the sum of the operating current (read, erase, program) in each plane.
11. For all pins other than those shown in test conditions, input level is V
CCQ
0.2V or GND0.2V.
12. Includes F-RY/BY.
Symbol
Parameter
Notes
Min.
Typ.
Max.
Unit
Test Conditions
I
SB
S-V
CC
Standby Current
1
15
A
S-CE
1
, S-CE
2
S-V
CC
- 0.2V or
S-CE
2
0.2V
I
CC1
S-V
CC
Operation Current
25
mA
S-CE
1
= V
IL
,
S-CE
2
= V
IH
,
V
IN
= V
IL
or V
IH
t
CYCLE
= Min.
I
I/O
= 0mA
I
CC2
S-V
CC
Operation Current
3
mA
S-CE
1
0.2V,
S-CE
S-V
CC
-0.2V,
V
IN
S-V
CC
-0.2V
or
0.2V
t
CYCLE
= 1s,
I
I/O
= 0mA
V
IL
Input Low Voltage
6
-0.2
0.4
V
V
IH
Input High Voltage
6
1.4
V
CC
+0.2
V
V
OL
Output Low Voltage
6,12
0.4
V
F-V
CC
= F-V
CC
(Min.)
I
OL
= 100A
V
OH
Output High Voltage
6
1.4
V
F-V
CC
= F-V
CC
(Min.)
I
OH
= -100A
V
PPLK
F-V
PP
Lockout during Normal
Operations
4,6,7
0.4
V
V
PPH1
F-V
PP
during Block Erase,
Advanced Factory Program,
(PageBuffer) Program Operations
7
0.9
1.8
1.95
V
V
PPH2
F-V
PP
during Block Erase,
(PageBuffer) Program
7
11.7
12
12.3
V
V
LKO
F-V
CC
Lockout Voltage
1
V
sharp
L R S 1 3 A 0
21
12. AC Electrical Characteristics for Flash Memory
12.1 AC Test Conditions
12.2 Read Cycle
(T
A
= -25C to +85C, F-V
CC
= 1.7V to 1.95V)
Notes:
1. Sampled, not 100% tested.
2. F-OE may be delayed up to t
ELQV
t
GLQV
after the falling edge of F-CE without impact to t
ELQV
.
Input pulse level
0 V to V
CC
Input rise and fall time
5 ns
Input and Output timing Ref. level
V
CC
/ 2
Output load
C
L
(50pF)
Symbol
Parameter
Notes
Min.
Max.
Unit
t
AVAV
Read Cycle Time
70
ns
t
AVQV
Address to Output Delay
70
ns
t
ELQV
F-CE to Output Delay
2
70
ns
t
APA
Page Address Access Time
20
ns
t
GLQV
F-OE to Output Delay
2
20
ns
t
PHQV
F-RST High to Output Delay
200
ns
t
EHQZ
, t
GHQZ
F-CE or F-OE to Output in High-Z, Whichever Occurs First
1
15
ns
t
ELQX
F-CE to Output in Low-Z
1
0
ns
t
GLQX
F-OE to Output in Low-Z
1
0
ns
t
OH
Output Hold from First Occurring Address, F-CE or F-OE change
1
0
ns
sharp
L R S 1 3 A 0
22
12.3 Write Cycle (F-WE / F-CE Controlled)
(1,2,9)
(T
A
= -25C to +85C, F-V
CC
= 1.7V to 1.95V)
Notes:
1. The timing characteristics for reading the status register during block erase, advanced factory program, (page buffer)
program operations are the same as during read-only operations. See the AC Characteristics for read cycle.
2. A write operation can be initiated and terminated with either F-CE or F-WE.
3. Sampled, not 100% tested.
4. Write pulse width (t
WP
) is defined from the falling edge of F-CE or F-WE (whichever goes low last) to the rising edge of
F-CE or F-WE (whichever goes high first). Hence, t
WP
=t
WLWH
=t
ELEH
=t
WLEH
=t
ELWH
.
5. Write pulse width high (t
WPH
) is defined from the rising edge of F-CE or F-WE (whichever goes high first) to the falling
edge of F-CE or F-WE (whichever goes low last). Hence, t
WPH
=t
WHWL
=t
EHEL
=t
WHEL
=t
EHWL
.
6. F-V
PP
should be held at F-V
PP
=V
PPH1/2
until determination of block erase, (page buffer) program success (SR.1/3/4/5=0)
and held at F-V
PP
=V
PPH1
until determination of advanced factory program success (SR.1/3/5=0).
7. t
WHR0
(t
EHR0
) after the Read Query or Read Identifier Codes command=t
AVQV
+100ns.
8. See 5.1 Command Definitions for valid address and data for block erase, advanced factory program, (page buffer) program
or lock bit configuration.
9. F
1
and F
2
should not be operated at the same timing to Block erase, advanced factory program, (page buffer) program.
Symbol
Parameter
Notes
Min.
Max.
Unit
t
AVAV
Write Cycle Time
70
ns
t
PHWL
(t
PHEL
)
F-RST High Recovery to F-WE (F-CE) Going Low
3
150
ns
t
ELWL
(t
WLEL
)
F-CE (F-WE) Setup to F-WE (F-CE) Going Low
0
ns
t
WLWH
(t
ELEH
)
F-WE (F-CE) Pulse Width
4
45
ns
t
DVWH
(t
DVEH
) Data Setup to F-WE (F-CE) Going High
8
45
ns
t
AVWH
(t
AVEH
)
Address Setup to F-WE (F-CE) Going High
8
45
ns
t
WHEH
(t
EHWH
) F-CE (F-WE) Hold from F-WE (F-CE) High
0
ns
t
WHDX
(t
EHDX
) Data Hold from F-WE (F-CE) High
0
ns
t
WHAX
(t
EHAX
) Address Hold from F-WE (F-CE) High
0
ns
t
WHWL
(t
EHEL
)
F-WE (F-CE) Pulse Width High
5
25
ns
t
SHWH
(t
SHEH
)
F-WP High Setup to F-WE (F-CE) Going High
3
0
ns
t
VVWH
(t
VVEH
) F-V
PP
Setup to F-WE (F-CE) Going High
3
150
ns
t
WHGL
(t
EHGL
)
Write Recovery before Read
30
ns
t
QVSL
F-WP High Hold from Valid SRD, F-RY/BY High-Z
3, 6
0
ns
t
QVVL
F-V
PP
Hold from Valid SRD, F-RY/BY High-Z
3, 6
0
ns
t
WHR0
(t
EHR0
)
F-WE (F-CE) High to SR.7 Going "0"
3, 7
t
AVQV
+19
ns
t
WHRL
(t
EHRL
)
F-WE (F-CE) High to F-RY/BY Going Low
3
100
ns
sharp
L R S 1 3 A 0
23
12.4 Block Erase, Advanced Factory Program, (Page Buffer) Program Performance
(3)
(T
A
= -25C to +85C, F-V
CC
= 1.7V to 1.95V)
Notes:
1. Typical values measured at F-V
CC
=1.8V, F-V
PP
=1.8V or 12V, and T
A
=+25 C. Assumes corresponding lock bits are not
set. Subject to change based on device characterization.
2. Excludes external system-level overhead.
3. Sampled, but not 100% tested.
4. A latency time is required from writing suspend command (F-WE or F-CE going high) until SR.7 going "1"or F-RY/BY
going High-Z.
5. If the interval time from a Block Erase Resume command to a subsequent Block Erase Suspend command is shorter than
t
ERES
and its sequence is repeated, the block erase operation may not be finished.
6. AFP mode is allowed only when T
A
=+20 C to +30 C.
Symbol
Parameter
Notes
PBP (Page
Buffer) is
Used, AFP
(Advanced
Factory
Program) is
Used or not
F-V
PP
=V
PPH1
(In System)
F-V
PP
=V
PPH2
(In Manufacturing)
Unit
Min.
Typ.
(1)
Max.
(2)
Min.
Typ.
(1)
Max.
(2)
t
WPB
4K-Word Parameter Block
Program Time
2
-
0.09
0.23
0.06
0.15
s
2
PBP
0.05
0.2
0.02
0.06
s
2, 6
AFP
-
-
0.015
-
s
t
WMB
32K-Word Main Block
Program Time
2
-
0.72
1.8
0.46
1.15
s
2
PBP
0.34
1.4
0.17
0.5
s
2, 6
AFP
-
-
0.12
-
s
t
WHQV1
/
t
EHQV1
Word Program Time
2
-
22
150
14
130
s
2
PBP
10
100
5
90
s
2, 6
AFP
-
-
3.5
16
s
t
WHQV2
/
t
EHQV2
4K-Word Parameter Block
Erase Time
2
-
0.3
2.5
0.2
2.5
s
t
WHQV3
/
t
EHQV3
32K-Word Main Block
Erase Time
2
-
0.8
4
0.5
4
s
t
WHRH1
/
t
EHRH1
(Page Buffer) Program Suspend
Latency Time to Read
4
-
5
10
5
10
s
t
WHRH2
/
t
EHRH2
Block Erase Suspend
Latency Time to Read
4
-
5
20
5
20
s
t
ERES
Latency Time from Block Erase
Resume Command to Block
Erase Suspend Command
5
-
500
500
s
t
ARES
Latency Time for AFP Set-Up
2, 6
AFP
-
-
-
5
s
Latency for AFP Verify
Transition
2, 6
AFP
-
-
2.7
5.6
s
Latency for AFP Verify
2, 6
AFP
-
-
1.7
130
s
sharp
L R S 1 3 A 0
24
12.5 Flash Memory AC Characteristics Timing Chart
AC Waveform for Single Asynchronous Read Operations from Status Register, Identifier Codes or Query Code
t
AVQV
t
EHQZ
t
GHQZ
t
ELQV
t
PHQV
t
GLQV
t
OH
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
IH
V
IL
(P)
(D/Q)
(W)
(G)
(E)
(A)
A
21-0
DQ
15-0
F-CE
F-OE
F-WE
F-RST
High-Z
t
ELQX
VALID
OUTPUT
VALID
ADDRESS
t
GLQX
t
AVAV
sharp
L R S 1 3 A 0
25
AC Waveform for Asynchronous Page Mode Read Operations from Main Blocks or Parameter Blocks
t
AVQV
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
t
AVAV
t
ELQV
t
EHQZ
t
GHQZ
t
OH
t
APA
t
GLQV
t
PHQV
High-Z
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
IH
V
IL
(P)
(D/Q)
(W)
(G)
(E)
(A)
A
21-3
V
IH
V
IL
(A)
A
2-0
DQ
15-0
F-CE
F-OE
F-WE
F-RST
t
GLQX
t
ELQX
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
sharp
L R S 1 3 A 0
26
AC Waveform for Write Operations(F-WE / F-CE Controlled)
t
AVAV
t
AVWH
(t
AVEH
)
t
WHAX
(t
EHAX
)
t
ELWL
(t
WLEL
)
t
PHWL
(t
PHEL
)
t
WLWH
t
WHWL
(t
EHEL
)
t
WHDX
(t
EHDX
)
t
DVWH
(t
DVEH
)
t
SHWH
(t
SHEH
)
t
VVWH
(t
VVEH
)
t
WHQV1,2,3
(t
EHQV1,2,3
)
t
QVSL
t
QVVL
t
WHEH
(t
EHWH
)
t
WHGL
(t
EHGL
)
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
(D/Q)
(W)
(G)
(E)
(A)
NOTES 5, 6
NOTES 5, 6
A
21-0
DQ
15-0
(V)
F-V
PP
V
IH
V
PPH1,2
V
PPLK
V
IL
V
IL
(P)
F-RST
F-CE
F-OE
F-WE
V
IH
V
IL
(S)
F-WP
(t
ELEH
)
NOTE 1
NOTE 2
NOTE 3
NOTE 4NOTE 5
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
DATA IN
DATA IN
VALID
SRD
Notes:
1. F-V
CC
power-up and standby.
2. Write each first cycle command.
3. Write each second cycle command or valid address and data.
4. Automated erase or program delay.
5. Read status register data.
6. For read operation, F-OE and F-CE must be driven active, and F-WE de-asserted.
(
1
)
(
0
)
(R)
(SR.7)
t
WHR0
(t
EHR0
)
F-RY/BY
High-Z
V
OL
t
WHRL
(t
EHRL
)
sharp
L R S 1 3 A 0
27
12.6 Reset Operations
(T
A
= -25C to +85C, F-V
CC
= 1.7V to 1.95V)
Notes:
1. A reset time, t
PHQV
, is required from the later of SR.7 (F-RY/BY) going "1" (High-Z) or F-RST going high until outputs
are valid. See the AC Characteristics - read cycle for t
PHQV
.
2. t
PLPH
is <100ns the device may still reset but this is not guaranteed.
3. Sampled, not 100% tested.
4. If F-RST asserted while a block erase, advanced factory program or (page buffer) program operation is not executing, the
reset will complete within 100ns.
5. When the device power-up, holding F-RST low minimum 100ns is required after F-V
CC
has been in predefined range and
also has been in stable there.
AC Waveform for Reset Operation
Symbol
Parameter
Notes
Min.
Max.
Unit
t
PLPH
F-RST Low to Reset during Read
(F-RST should be low during power-up.)
1, 2, 3
100
ns
t
PLRH
F-RST Low to Reset during Erase or Program
1, 3, 4
20
s
t
VPH
F-V
CC
1.65V to F-RST High
1, 3, 5
100
ns
t
VHQV
F-V
CC
1.65V to Output Delay
3
1
ms
ABORT
COMPLETE
t
PLPH
t
PLPH
t
VPH
t
PLRH
t
PHQV
t
PHQV
(A) Reset during Read Array Mode
(B) Reset during Erase or Program Mode
(C) F-RST rising timing
F-RST
F-RST
V
IL
V
IH
V
IL
V
IH
F-V
CC
GND
2.7V
F-RST
V
IL
V
IH
SR.7=
1
V
OH
V
OL
(D/Q)
DQ
15-0
VALID
OUTPUT
High-Z
(P)
(P)
(P)
V
OH
V
OL
(D/Q)
DQ
15-0
VALID
OUTPUT
High-Z
V
OH
V
OL
(D/Q)
DQ
15-0
VALID
OUTPUT
High-Z
t
PHQV
t
VHQV
sharp
L R S 1 3 A 0
28
13. AC Electrical Characteristics for SRAM
13.1 AC Test Conditions
Note:
1. Including scope and socket capacitance.
13.2 Read Cycle
(T
A
= -25C to +85C, S-V
CC
= 1.7V to 1.95V)
Note:
1. Active output to High-Z and High-Z to output active tests specified for a 200mV transition from steady state levels into
the test load.
Input pulse level
0.2 V to V
CC
-0.2 V
Input rise and fall time
5 ns
Input and Output timing Ref. level
0.9 V
Output load
1TTL +C
L
(30pF)
(1)
Symbol
Parameter
Notes
Min.
Max.
Unit
t
RC
Read Cycle Time
70
ns
t
AA
Address Access Time
70
ns
t
ACE1
Chip Enable Access Time (S-CE
1
)
70
ns
t
ACE2
Chip Enable Access Time (S-CE
2
)
70
ns
t
BE
Byte Enable Access Time
70
ns
t
OE
Output Enable to Output Valid
35
ns
t
OH
Output Hold from Address Change
10
ns
t
LZ1
S-CE
1
Low to Output Active
1
10
ns
t
LZ2
S-CE
2
High to Output Active
1
10
ns
t
OLZ
S-OE Low to Output Active
1
5
ns
t
BLZ
S-UB or S-LB Low to Output Active
1
10
ns
t
HZ1
S-CE
1
High to Output in High-Z
1
0
25
ns
t
HZ2
S-CE
2
Low to Output in High-Z
1
0
25
ns
t
OHZ
S-OE High to Output in High-Z
1
0
25
ns
t
BHZ
S-UB or S-LB High to Output in High-Z
1
0
25
ns
sharp
L R S 1 3 A 0
29
13.3 Write Cycle
(T
A
= -25C to +85C, S-V
CC
= 1.7V to 1.95V)
Note:
1. Active output to High-Z and High-Z to output active tests specified for a 200mV transition from steady state levels into
the test load.
Symbol
Parameter
Notes
Min.
Max.
Unit
t
WC
Write Cycle Time
70
ns
t
CW
Chip Enable to End of Write
60
ns
t
AW
Address Valid to End of Write
60
ns
t
BW
Byte Select Time
60
ns
t
AS
Address Setup Time
0
ns
t
WP
Write Pulse Width
50
ns
t
WR
Write Recovery Time
0
ns
t
DW
Input Data Setup Time
30
ns
t
DH
Input Data Hold Time
0
ns
t
OW
S-WE High to Output Active
1
5
ns
t
WZ
S-WE Low to Output in High-Z
1
0
25
ns
sharp
L R S 1 3 A 0
30
13.4 SRAM AC Characteristics Timing Chart
Read Cycle Timing Chart
V
IH
V
IL
Address
V
IH
V
IL
S-CE
1
V
IH
V
IL
S-CE
2
V
IH
V
IL
S-UB
S-LB
V
IH
V
IL
S-OE
V
IH
V
IL
S-WE
V
OH
V
OL
DQ
OUT
t
AA
High - Z
High - Z
t
RC
t
HZ1,2
t
BHZ
t
OHZ
t
ACE1,2
t
LZ1,2
t
BLZ
t
OLZ
t
BE
t
OE
t
OH
Address Stable
Data Valid
Data Valid
Standby
Device
Address Selection
sharp
L R S 1 3 A 0
31
Write Cycle Timing Chart (S-WE Controlled)
V
IH
V
IL
Address
V
IH
V
IL
S-CE
1
V
IH
V
IL
S-CE
2
V
IH
V
IL
S-UB
S-LB
V
IH
V
IL
S-OE
V
IH
V
IL
S-WE
V
OH
t
WZ
t
OW
t
DH
t
DW
t
AW
High - Z
High - Z
t
WC
(5)
t
WR
(2)
t
CW
(3)
t
BW
(1)
t
WP
(4)
t
AS
Address Stable
Data Valid
Data Valid
Data Undefined
Standby
Device
Address Selection
V
OL
(7,8)
DQ
OUT
V
IH
V
IL
(6)
DQ
IN
Notes:
1. A write occurs during the overlap of a low S-CE
1
, ahigh S-CE
2
and a low S-WE.
A write begins at the latest transition among S-CE
1
going low, S-CE
2
going high and S-WE going low.
A write ends at the earliest transition among S-CE
1
going high, S-CE
2
going low and S-WE going high.
t
WP
is measured from the beginning of write to the end of write.
2. t
CW
is measured from the later of S-CE
1
going low or S-CE
2
going high to the end of write.
3. t
BW
is measured from the time of going low S-UB or low S-LB to the end of write.
4. t
AS
is measured from the address valid to beginning of write.
5. t
WR
is measured from the end of write to the address change. t
WR
applies in case a write ends at S-CE
1
going high, S-CE
2
going low or S-WE going high.
6. During this period DQ pins are in the output state, therefore the input signals of opposite phase to the
outputs must not be applied.
7. If S-CE
1
goes low or S-CE
2
goes high simultaneously with S-WE going low or after S-WE going low,
the outputs remain in high impedance state.
8. If S-CE
1
goes high or S-CE
2
goes low simultaneously with S-WE going high or before S-WE going high,
the outputs remain in high impedance state.
sharp
L R S 1 3 A 0
32
Write Cycle Timing Chart (S-CE Controlled)
t
AW
(1)
t
WP
V
IH
V
IL
Address
V
IH
V
IL
S-CE
1
V
IH
V
IL
S-CE
2
V
IH
V
IL
S-UB
S-LB
V
IH
V
IL
S-OE
V
IH
V
IL
S-WE
V
OH
t
DH
t
DW
High - Z
t
WC
(5)
t
WR
(2)
t
CW
(3)
t
BW
(4)
t
AS
Address Stable
Data Valid
Data Valid
Standby
Device
Address Selection
V
OL
DQ
OUT
V
IH
V
IL
DQ
IN
Notes:
1. A write occurs during the overlap of a low S-CE
1
, ahigh S-CE
2
and a low S-WE.
A write begins at the latest transition among S-CE
1
going low, S-CE
2
going high and S-WE going low.
A write ends at the earliest transition among S-CE
1
going high, S-CE
2
going low and S-WE going high.
t
WP
is measured from the beginning of write to the end of write.
2. t
CW
is measured from the later of S-CE
1
going low or S-CE
2
going high to the end of write.
3. t
BW
is measured from the time of going low S-UB or low S-LB to the end of write.
4. t
AS
is measured from the address valid to beginning of write.
5. t
WR
is measured from the end of write to the address change. t
WR
applies in case a write ends at S-CE
1
going high, S-CE
2
going low or S-WE going high.
sharp
L R S 1 3 A 0
33
Write Cycle Timing Chart (S-UB, S-LB Controlled)
V
IH
V
IL
Address
V
IH
V
IL
S-CE
1
V
IH
V
IL
S-CE
2
V
IH
V
IL
S-UB
S-LB
V
IH
V
IL
S-OE
V
IH
V
IL
S-WE
V
OH
t
DH
t
DW
t
AW
High - Z
t
WC
(5,6)
t
WR
(2)
t
CW
(3)
t
BW
(1)
t
WP
(4,6)
t
AS
Address Stable
Data Valid
Data Valid
Standby
Device
Address Selection
V
OL
DQ
OUT
V
IH
V
IL
DQ
IN
Notes:
1. A write occurs during the overlap of a low S-CE
1
, a high S-CE
2
and a low S-WE.
A write begins at the latest transition among S-CE
1
going low, S-CE
2
going high and S-WE going low.
A write ends at the earliest transition among S-CE
1
going high, S-CE
2
going low and S-WE going high.
t
WP
is measured from the beginning of write to the end of write.
2. t
CW
is measured from the later of S-CE
1
going low or S-CE
2
going high to the end of write.
3. t
BW
is measured from the time of going low S-UB or low S-LB to the end of write.
4. t
AS
is measured from the address valid to beginning of write.
5. t
WR
is measured from the end of write to the address change. t
WR
applies in case a write ends at S-CE
1
going high, S-CE
2
going low or S-WE going high.
6. S-UB and S-LB need to make the time of start of a cycle, and an end high level for reservation of t
AS
and t
WR
.
sharp
L R S 1 3 A 0
34
14. Data Retention Characteristics for SRAM
(T
A
= -25C to +85C)
Notes
1. Reference value at T
A
= 25C
2. S-CE
1
S-V
CC
- 0.2V, S-CE
2
S-V
CC
- 0.2V (S-CE
1
controlled) or S-CE
2
0.2V (S-CE
2
controlled).
Data Retention timing chart (S-CE
1
Controlled)
(1)
Data Retention timing chart (S-CE
2
Controlled)
Symbol
Parameter
Note
Min.
Typ.
(1)
Max.
Unit
Conditions
V
CCDR
Data Retention Supply voltage
2
1
2.2
V
S-CE
2
0.2V or
S-CE
1
S-V
CC
- 0.2V
I
CCDR
Data Retention Supply current
2
0.5
8
A
S-V
CC
= 1.2V,
S-CE
2
0.2V or
S-CE
1
S-V
CC
- 0.2V
t
CDR
Chip enable setup time
0
ns
t
R
Chip enable hold time
t
RC
ns
S-V
CC
V
CCDR
S-CE
1
0V
Data Retention mode
S-CE
1
S-V
CC
-0.2V
t
CDR
t
R
Note:
1. To control the data retention mode at S-CE
1
, fix the input level of
S-CE
2
between V
CCDR
and V
CCDR
-0.2V or 0V and 0.2V during the data retention mode.
1.4V
1.7V
S-V
CC
S-CE
2
V
CCDR
0V
Data Retention mode
S-CE
2
0.2V
t
CDR
t
R
0.4V
1.7V
sharp
L R S 1 3 A 0
35
15. Notes
This product is a stacked CSP package that a 64M (x16) bit Flash Memory, a 64M (x16) bit Flash Memory and a 16M (x16) bit
SRAM are assembled into.
- Supply Power
Maximum difference (between F-V
CC
and S-V
CC
) of the voltage is less than 0.3V.
- Power Supply and Chip Enable of Flash Memory and SRAM
Two or more chips among Flash memory (F
1
, F
2
) and SRAM should not be active simultaneously.
If the two memories are active together, possibly they may not operate normally by interference noises or data collision
on DQ bus.
Both F-V
CC
and S-V
CC
are needed to be applied by the recommended supply voltage at the same time except SRAM
data retention mode.
- Power Up Sequence
When turning on Flash memory power supply, keep F-RST low. After F-V
CC
reaches over 1.7V, keep F-RST low for
more than 100 nsec.
- Device Decoupling
The power supply is needed to be designed carefully because the Flash Memory (or the SRAM) is in standby mode
when the SRAM (or the Flash Memory) is active. A careful decoupling of power supplies is necessary between SRAM
and Flash Memory. Note peak current caused by transition of control signals (F
1,2
-CE, S-CE
1
, S-CE
2
).
sharp
L R S 1 3 A 0
36
16. Flash Memory Data Protection
Noises having a level exceeding the limit specified in the specification may be generated under specific operating conditions on
some systems. Such noises, when induced onto F-WE signal or power supply, may be interpreted as false commands and causes
undesired memory updating. To protect the data stored in the flash memory against unwanted writing, systems operating with the
flash memory should have the following write protect designs, as appropriate:
n
The below describes data protection method.
1. Protection of data in each block
ny locked block by setting its block lock bit is protected against the data alternation. When F-WP is low, any locked-down
block by setting its block lock-down bit is protected from lock status changes.
By using this function, areas can be defined, for example, program area (locked blocks), and data area (unlocked
blocks).
For detailed block locking scheme, see Chapter 5.Command Definitions for Flash Memory.
2. Protection of data with F-V
PP
control
When the level of F-V
PP
is lower than V
PPLK
(F-V
PP
lockout voltage), write functions to all blocks are disabled. All
blocks are locked and the data in the blocks are completely protected.
3. Protection of data with F-RST
Especially during power transitions such as power-up and power-down, the flash memory enters reset mode by bringing
F-RST to low, which inhibits write operation to all blocks.
For detailed description on F-RST control, see Chapter 12.6 AC Electrical Characteristics for Flash Memory, Reset
Operations.
n
Protection against noises on F-WE signal
To prevent the recognition of false commands as write commands, system designer should consider the method for
reducing noises on F-WE signal.
sharp
L R S 1 3 A 0
37
17. Design Considerations
1. Power Supply Decoupling
To avoid a bad effect to the system by flash memory power switching characteristics, each device should have a 0.1 F
ceramic capacitor connected between its F-V
CC
and GND and between its F-V
PP
and GND.
Low inductance capacitors should be placed as close as possible to package leads.
2. F-V
PP
Trace on Printed Circuit Boards
Updating the memory contents of flash memories that reside in the target system requires that the printed circuit board
designer pay attention to the F-V
PP
Power Supply trace. Use similar trace widths and layout considerations given to the F-V
CC
power bus.
3. The Inhibition of Overwrite Operation
Please do not execute reprograming "0" for the bit which has already been programed "0". Overwrite operation may
generate unerasable bit.
In case of reprograming "0" to the data which has been programed "1".
Program "0" for the bit in which you want to change data from "1" to "0".
Program "1" for the bit which has already been programed "0".
For example, changing data from "1011110110111101" to "1010110110111100"
requires "1110111111111110" programing.
4. Power Supply
Block erase, advanced factory program, (page buffer) program with an invalid F-V
PP
(See Chapter 11. DC Electrical
Characteristics) produce spurious results and should not be attempted.
Device operations at invalid F-V
CC
voltage (See Chapter 11. DC Electrical Characteristics) produce spurious results
and should not be attempted.
sharp
SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
Suggested applications (if any) are for standard use; See Important Restrictions for limitations on special applications. See Limited
Warranty for SHARP's product warranty. The Limited Warranty is in lieu, and exclusive of, all other warranties, express or implied.
ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND
FITNESS FOR A PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED. In no event will SHARP be liable, or in any way responsible,
for any incidental or consequential economic or property damage.
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Pudong Shanghai, 201206 P.R. China
Phone: (86) 21-5854-7710/21-5834-6056
Fax: (86) 21-5854-4340/21-5834-6057
Head Office:
No. 360, Bashen Road,
Xin Development Bldg. 22
Waigaoqiao Free Trade Zone Shanghai
200131 P.R. China
Email: smc@china.global.sharp.co.jp
SHARP-ROXY (Hong Kong) Ltd.
3rd Business Division,
17/F, Admiralty Centre, Tower 1
18 Harcourt Road, Hong Kong
Phone: (852) 28229311
Fax: (852) 28660779
www.sh
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