Integrated Circuits Group
LRS1828
Stacked Chip
128M (x16) Boot Block Flash and 32M (x16) SCRAM
(Model No.:
LRS1828)
Spec No.:
EL149020
Issue Date:
September 24, 2002
P
RODUCT
S
PECIFICATIONS
L R S 1 8 2 8
Handle this document carefully for it contains material protected by international copyright law.
Any reproduction, full or in part, of this material is prohibited without the express written permission
of the company.
When using the products covered herein, please observe the conditions written herein and the
precautions outlined in the following paragraphs. In no event shall the company be liable for
any damages resulting from failure to strictly adhere to these conditions and precautions.
(1) The products covered herein are designed and manufactured for the following application areas.
When using the products covered herein for the equipment listed in Paragraph (2), even for the
following application areas, be sure to observe the precautions given in Paragraph (2). Never use
the products for the equipment listed in Paragraph (3).
Office electronics
Instrumentation and measuring equipment
Machine tools
Audiovisual equipment
Home appliance
Communication equipment other than for trunk lines
(2) Those contemplating using the products covered herein for the following equipment
which demands high reliability, should first contact a sales representative of the company and
then accept responsibility for incorporating into the design fail-safe operation, redundancy, and
other appropriate measures for ensuring reliability and safety of the equipment and the overall
system.
Control and safety devices for airplanes, trains, automobiles, and other transportation
equipment
Mainframe computers
Traffic control systems
Gas leak detectors and automatic cutoff devices
Rescue and security equipment
Other safety devices and safety equipment, etc.
(3) Do not use the products covered herein for the following equipment which demands extremely
high performance in terms of functionality, reliability, or accuracy.
Aerospace equipment
Communications equipment for trunk lines
Control equipment for the nuclear power industry
Medical equipment related to life support, etc.
(4) Please direct all queries and comments regarding the interpretation of the above three
Paragraphs to a sales representative of the company.
Please direct all queries regarding the products covered herein to a sales representative of the
company.
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L R S 1 8 2 8
1
Contents
1. Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3. Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1
Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2
Simultaneous Operation Modes Allowed with Four Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5. Command Definitions for Flash Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.1
Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.2
Identifier Codes for Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.3
Functions of Block Lock and Block Lock-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.4
Block Locking State Transitions upon Command Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.5
Block Locking State Transitions upon F-WP Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6. Status Register Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7. Memory Map for Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.1
Memory Map - F
1
Selected (F
1
-CE = "V
IL
", F
2
-CE = "V
IH
") . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.2
Memory Map - F
2
Selected (F
1
-CE = "V
IH
", F
2
-CE = "V
IL
") . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
8. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
9. Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
10. Pin Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
11. DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
12. AC Electrical Characteristics for Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
12.1 AC Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
12.2 Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
12.3 Write Cycle (F-WE / F-CE Controlled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
12.4 Block Erase, Full Chip Erase, (Page Buffer) Program Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
12.5 Flash Memory AC Characteristics Timing Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
12.6 Reset Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
13. AC Electrical Characteristics for Smartcombo RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
13.1 AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
13.2 Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
13.3 Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
13.4 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
13.5 Sleep Mode Entry / Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
13.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
13.7 Mode Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
13.8 Mode Register Setting Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
13.9 Cautions for Setting Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
13.10Smartcombo RAM AC Characteristics Timing Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
14. Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
15. Flash Memory Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
16. Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
17. Related Document Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
18. Package and Packing Specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
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1. Description
The LRS1828 is a combination memory organized as 4,194,304 x16 bit flash memory, 4,194,304 x16 bit flash memory and
2,097,152 x16 bit Smartcombo RAM in one package.
Features
- Power supply
2.7V to 3.3V(Flash)
2.7V to 3.1V(Smartcombo RAM)
- Operating temperature
-30C to +85C
- Not designed or rated as radiation hardened
- 72pin CSP (LCSP072-P-0811) plastic package
- Flash memory has P-type bulk silicon, and Smartcombo RAM has P-type bulk silicon
Flash Memory
- F
1
: 64M (x16) bit Flash Memory, F
2
: 64M (x16) bit Flash Memory
- Access Time
65 ns
(Max.)
- Power supply current for each Chip (The current for F-V
CC
pin and F-V
PP
pin)
Read
26 mA
(Max. t
CYCLE
= 200ns, CMOS Input)
Word write
61 mA
(Max.)
Block erase
31 mA
(Max.)
Reset Power-Down
50 A
(Max. F-RST = GND 0.2V,
I
OUT
(F-RY/BY) = 0mA)
Standby
50 A
(Max. F-CE = F-RST = F-V
CC
0.2V)
- Optimized Array Blocking Architecture for each Chip
Eight 4K-word Parameter Blocks
One-hundred and twenty-seven 32K-word Main Blocks
F
1
: Bottom Parameter Location, F
2
: Top Parameter Location
- Extended Cycling Capability
100,000 Block Erase Cycles
(F-V
PP
= 1.65V to 3.3V)
- Enhanced Automated Suspend Options
Word Write Suspend to Read
Block Erase Suspend to Word Write
Block Erase Suspend to Read
* In the following pages, F
1
, F
2
and F are defined as F
1
: 64M (x16) bit Flash, F
2
: 64M (x16) bit Flash, F: both Flashes in common.
Smartcombo RAM
- Access Time
65 ns
(Max.)
- Cycle time
65 ns
(Min.)
- Power Supply current
Operating current
50 mA
(Max. t
RC
, t
WC
= Min.)
Standby current (Data retention current)
100 A
(Max.)
Sleep Mode (Data non-retention current)
30 A
(Max.)
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3
2. Pin Configuration
NC
NC
GND
A
16
A
11
A
8
A
10
A
15
A
14
A
9
DQ
15
A
13
A
12
1
2
3
4
5
6
7
8
S-WE
F-WE
F-RST
T
1
F-A
21
F-
RY/BY
S-A
17
T
2
DQ
12
DQ
13
DQ
6
S-CE
2
F-WP
S-LB
F-V
PP
S-UB S-OE
A
19
DQ
11
T
4
DQ
9
T
3
DQ
10
DQ
8
A
B
C
D
E
F
G
A
18
F-A
17
A
7
A
6
A
3
A
2
GND
9
DQ
14
DQ
4
S-V
CC
DQ
2
DQ
0
A
1
NC
10
DQ
7
DQ
5
F-V
CC
DQ
3
DQ
1
S-CE
1
NC
11
NC
12
NC
H
NC
NC
A
5
A
4
A
0
GND
F-OE F
2
-CE
NC
NC
F
1
-CE
INDEX
(TOP View)
A
20
Note) From T
1
to T
4
pins are needed to be open.
Two NC pins at the corner are connected.
Do not float any GND pins.
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4
Pin
Description
Type
A
0
to A
16
, A
18
to A
20
Address Inputs (Common)
Input
F-A
17
, F-A
21
Address Inputs (Flash)
Input
S-A
17
Address Input (Smartcombo RAM)
Input
F
1,2
-CE
Chip Enable Input (Flash)
Input
S-CE
1
Chip Enable Input (Smartcombo RAM)
Input
S-CE
2
Sleep State Input (Smartcombo RAM)
Input
F-WE
Write Enable Input (Flash)
Input
S-WE
Write Enable Input (Smartcombo RAM)
Input
F-OE
Output Enable Input (Flash)
Input
S-OE
Output Enable Input (Smartcombo RAM)
Input
S-LB
Smartcombo RAM Byte Enable Input (DQ
0
to DQ
7
)
Input
S-UB
Smartcombo RAM Byte Enable Input (DQ
8
to DQ
15
)
Input
F-RST
Reset Power Down Input (Flash)
Block erase and Write : V
IH
Read : V
IH
Reset Power Down : V
IL
Input
F-WP
Write Protect Input (Flash)
When F-WP is V
IL
, locked-down blocks cannot be unlocked. Erase or
program operation can be executed to the blocks which are not locked and
locked-down. When F-WP is V
IH
, lock-down is disabled.
Input
F-RY/BY
Ready/Busy Output (Flash)
During an Erase or Write operation : V
OL
Block Erase and Write Suspend : High-Z (High impedance)
Open Drain
Output
DQ
0
to DQ
15
Data Inputs and Outputs (Common)
Input / Output
F-V
CC
Power Supply (Flash)
Power
S-V
CC
Power Supply (Smartcombo RAM)
Power
F-V
PP
Monitoring Power Supply Voltage (Flash)
Block Erase and Write : F-V
PP
= V
PPH
All Blocks Locked : F-V
PP
< V
PPLK
Input
GND
GND (Common)
Power
NC
Non Connection
-
T
1
to T
4
Test pins (Should be all open)
-
* See Chapter B-1
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3. Truth Table
3.1 Bus Operation
(1)
Notes:
1. L = V
IL
, H = V
IH
, X = H or L, High-Z = High impedance. Refer to the DC Characteristics.
2. Command writes involving block erase (page buffer) program are reliably executed when F-V
PP
= V
PPH
and F-V
CC
=
2.7V to 3.3V.
Command writes involving full chip erase is reliably executed when F-V
PP
= V
PPH
and F-V
CC
= 2.7V to 3.3V.
Block erase, full chip erase, (page buffer) program with F-V
PP
< V
PPH
(Min.) produce spurious results and should not be
attempted.
3. Never hold F-OE low and F-WE low at the same timing.
4. Refer to Section 5. Command Definitions for Flash Memory valid D
IN
during a write operation.
5. F-WP set to V
IL
or V
IH
.
6. Electricity consumption of Flash Memory is lowest when F-RST = GND 0.2V.
7. Never hold F
1
-CE low and F
2
-CE low at the same timing.
8. Read Bus operation or Write Bus operation is not simultaneously operated to F
1
and F
2
.
9. Flash Read Mode
10. S-UB, S-LB Control Mode
Flash
Smart
combo
RAM
Notes F-CE
(7)
F-RST F-OE F-WE S-CE
1
S-CE
2
S-OE S-WE S-LB
S-UB DQ
0
to DQ
15
Read
Standby
3,5,8
L
H
L
H
H
H
X
X
X
(9)
Output
Disable
5,8
H
High - Z
Write
2,3,4,5,8
L
X
H
H
H
D
IN
Read
Sleep
3,5,8
L
H
L
H
X
L
X
X
X
(9)
Output
Disable
5,8
H
High - Z
Write
2,3,4,5,8
L
D
IN
Standby
Read
5,6
H
H
X
X
L
H
L
H
(10)
Output
Disable
5,6
H
H
X
X
High - Z
Write
5,6
H
L
(10)
Reset Power
Down
Read
5,6
X
L
X
X
L
H
L
H
(10)
Output
Disable
5,6
H
H
X
X
High - Z
Write
5,6
H
L
(10)
Standby
Standby
5
H
H
X
X
H
H
X
X
X
High - Z
Reset Power
Down
5,6
X
L
X
H
H
Standby
Sleep
5
H
H
X
X
X
L
X
X
X
High - Z
Reset Power
Down
5,6
X
L
Mode
Address
DQ
0
to DQ
15
S-LB S-UB
DQ
0
to DQ
7
DQ
8
to DQ
15
Read Array
X
D
OUT
L
L
D
OUT
/D
IN
D
OUT
/D
IN
Read Identifier Codes
See 5.2
See 5.2
L
H
D
OUT
/D
IN
High - Z
Read Query
Refer to the Appendix Refer to the Appendix
H
L
High - Z
D
OUT
/D
IN
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6
3.2 Simultaneous Operation Modes Allowed with Four Planes
(1, 2, 3)
Notes:
1. "X" denotes the operation available.
2. Configurative Partition Dual Work Restrictions:
Status register reflects partition state, not WSM (Write State Machine) state - this allows a status register for each partition.
Only one partition can be erased or programmed at a time - no command queuing.
Commands must be written to an address within the block targeted by that command.
3. This table shows operation which can be performed by only the selected chip, not during 2 chips of F
1
and F
2
.
IF ONE
PARTITION IS:
THEN THE MODES ALLOWED IN THE OTHER PARTITION IS:
Read
Array
Read ID
Read
Status
Read
Query
Word
Program
Page
Buffer
Program
Block
Erase
Full Chip
Erase
Program
Suspend
Block
Erase
Suspend
Read Array
X
X
X
X
X
X
X
X
X
Read ID
X
X
X
X
X
X
X
X
X
Read Status
X
X
X
X
X
X
X
X
X
X
Read Query
X
X
X
X
X
X
X
X
X
Word Program
X
X
X
X
X
Page Buffer
Program
X
X
X
X
X
Block Erase
X
X
X
X
Full Chip Erase
X
Program
Suspend
X
X
X
X
X
Block Erase
Suspend
X
X
X
X
X
X
X
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4. Block Diagram
F
1
: 64M (x16) bit
Flash memory
32M (x16) bit
Smartcombo RAM
S-A
17
S-CE
1
S-CE
2
S-OE
S-WE
S-LB
S-UB
S-V
CC
F-V
PP
F-V
CC
F
1
-CE
A
0
to A
16
, A
18
to A
20
DQ
0
to DQ
15
F-RY/BY
F-A
17
, F-A
21
F-OE
F-WE
F-WP
F-RST
F
2
-CE
GND
F
2
: 64M (x16) bit
Flash memory
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5. Command Definitions for Flash Memory
(11)
5.1 Command Definitions
Notes:
1. Bus operations are defined in 3.1 Bus Operation.
2. The address which is written at the first bus cycle should be the same as the address which is written at the second bus
cycle.
X=Any valid address within the device.
PA=Address within the selected partition.
IA=Identifier codes address (See 5.2 Identifier Codes for Read Operation).
QA=Query codes address. Refer to the LH28F320BF, LH28F640BF, LH28F128BF series Appendix for details.
BA=Address within the block being erased, set/cleared block lock bit or set block lock-down bit.
WA=Address of memory location for the Program command or the first address for the Page Buffer Program command.
PCRC=Partition configuration register code presented on the address A
0
-A
15
.
3. ID=Data read from identifier codes (See 5.2 Identifier Codes for Read Operation).
QD=Data read from query database. Refer to the LH28F320BF, LH28F640BF, LH28F128BF series Appendix for details.
SRD=Data read from status register. See 6. Status Register Definition for a description of the status register bits.
WD=Data to be programmed at location WA. Data is latched on the rising edge of F-WE or F-CE (whichever goes high first).
N-1=N is the number of the words to be loaded into a page buffer.
4. Following the Read Identifier Codes command, read operations access manufacturer code, device code, block lock
configuration code, partition configuration register code (See 5.2 Identifier Codes for Read Operation).
The Read Query command is available for reading CFI (Common Flash Interface) information.
5. Block erase, full chip erase or (page buffer) program cannot be executed when the selected block is locked. Unlocked
block can be erased or programmed when F-RST is V
IH
.
6. Either 40H or 10H are recognized by the CUI (Command User Interface) as the program setup.
7. Following the third bus cycle, inputs the program sequential address and write data of "N" times. Finally, input the any
valid address within the target partition to be programmed and the confirm command (D0H). Refer to the LH28F320BF,
LH28F640BF, LH28F128BF series Appendix for details.
Command
Bus
Cycles
Req'd
Notes
First Bus Cycle
Second Bus Cycle
Oper
(1)
Address
(2)
Data
(3)
Oper
(1)
Address
(2)
Data
(3)
Read Array
1
2
Write
PA
FFH
Read Identifier Codes
2
2,3,4
Write
PA
90H
Read
IA
ID
Read Query
2
2,3,4
Write
PA
98H
Read
QA
QD
Read Status Register
2
2,3
Write
PA
70H
Read
PA
SRD
Clear Status Register
1
2
Write
PA
50H
Block Erase
2
2,3,5
Write
BA
20H
Write
BA
D0H
Full Chip Erase
2
2,5,9
Write
X
30H
Write
X
D0H
Program
2
2,3,5,6
Write
WA
40H or
10H
Write
WA
WD
Page Buffer Program
4
2,3,5,7
Write
WA
E8H
Write
WA
N-1
Block Erase and (Page Buffer)
Program Suspend
1
2,8,9
Write
PA
B0H
Block Erase and (Page Buffer)
Program Resume
1
2,8,9
Write
PA
D0H
Set Block Lock Bit
2
2
Write
BA
60H
Write
BA
01H
Clear Block Lock Bit
2
2,10
Write
BA
60H
Write
BA
D0H
Set Block Lock-down Bit
2
2
Write
BA
60H
Write
BA
2FH
Set Partition Configuration
Register
2
2,3
Write
PCRC
60H
Write
PCRC
04H
sharp
L R S 1 8 2 8
9
8. If the program operation in one partition is suspended and the erase operation in other partition is also suspended, the
suspended program operation should be resumed first, and then the suspended erase operation should be resumed next.
9. Full chip erase operation can not be suspended.
10. Following the Clear Block Lock Bit command, block which is not locked-down is unlocked when F-WP is V
IL
.
When F-WP is V
IH
, lock-down bit is disabled and the selected block is unlocked regardless of lock-down configuration.
11. Commands other than those shown above are reserved by SHARP for future device implementations and should not be
used.
sharp
L R S 1 8 2 8
10
5.2 Identifier Codes for Read Operation
Notes:
1. Bottom parameter device has its parameter blocks in the plane 0 (The lowest address).
Top parameter device has its parameter blocks in the plane 3 (The highest address).
2. DQ
15
-DQ
2
is reserved for future implementation.
3. PCRC=Partition Configuration Register Code.
4. The address A
21
-A
16
are shown in below table for reading the manufacturer, device, lock configuration, device
configuration code.
The address to read the identifier codes is dependent on the partition which is selected when writing the Read Identifier
Codes command (90H).
See Chapter 6. Partition Configuration Register Definition (P.15) for the partition configuration register.
Identifier Codes for Read Operation on Partition Configuration (64M-bit device)
Code
Address
[A
15
-A
0
]
(4)
Data
[DQ
15
-DQ
0
]
Notes
Manufacturer Code
Manufacturer Code
0000H
00B0H
Device Code
64M Bottom Parameter Device Code (F
1
Selected)
64M Top Parameter Device Code (F
2
Selected)
0001H
00B1H (F
1
Selected)
00B0H (F
2
Selected)
1
Block Lock Configuration
Code
Block is Unlocked
Block
Address
+ 2
DQ
0
= 0
2
Block is Locked
DQ
0
= 1
2
Block is not Locked-Down
DQ
1
= 0
2
Block is Locked-Down
DQ
1
= 1
2
Device Configuration
Code
Partition Configuration Register
0006H
PCRC
3
Partition Configuration Register
Address (64M-bit device)
[A
21
-A
16
]
PCR.10
PCR.9
PCR.8
0
0
0
00H
0
0
1
00H or 10H
0
1
0
00H or 20H
1
0
0
00H or 30H
0
1
1
00H or 10H or 20H
1
1
0
00H or 20H or 30H
1
0
1
00H or 10H or 30H
1
1
1
00H or 10H or 20H or 30H
sharp
L R S 1 8 2 8
11
5.3 Functions of Block Lock and Block Lock-Down
Notes:
1. DQ
0
= 1: a block is locked; DQ
0
= 0: a block is unlocked.
DQ
1
= 1: a block is locked-down; DQ
1
= 0: a block is not locked-down.
2. Erase and program are general terms, respectively, to express: block erase, full chip erase and (page buffer) program
operations.
3. At power-up or device reset, all blocks default to locked state and are not locked-down, that is, [001] (F-WP = 0) or [101]
(F-WP = 1), regardless of the states before power-off or reset operation.
4. When F-WP is driven to V
IL
in [110] state, the state changes to [011] and the blocks are automatically locked.
5.4 Block Locking State Transitions upon Command Write
(4)
Notes:
1. "Set Lock" means Set Block Lock Bit command, "Clear Lock" means Clear Block Lock Bit command and "Set Lock-
down" means Set Block Lock-Down Bit command.
2. When the Set Block Lock-Down Bit command is written to the unlocked block (DQ
0
= 0), the corresponding block is
locked-down and automatically locked at the same time.
3. "No Change" means that the state remains unchanged after the command written.
4. In this state transitions table, assumes that F-WP is not changed and fixed V
IL
or V
IH
.
Current State
Erase/Program Allowed
(2)
State
F-WP
DQ
1
(1)
DQ
0
(1)
State Name
[000]
0
0
0
Unlocked
Yes
[001]
(3)
0
0
1
Locked
No
[011]
0
1
1
Locked-down
No
[100]
1
0
0
Unlocked
Yes
[101]
(3)
1
0
1
Locked
No
[110]
(4)
1
1
0
Lock-down Disable
Yes
[111]
1
1
1
Lock-down Disable
No
Current State
Result after Lock Command Written (Next State)
State
F-WP
DQ
1
DQ
0
Set Lock
(1)
Clear Lock
(1)
Set Lock-down
(1)
[000]
0
0
0
[001]
No Change
[011]
(2)
[001]
0
0
1
No Change
(3)
[000]
[011]
[011]
0
1
1
No Change
No Change
No Change
[100]
1
0
0
[101]
No Change
[111]
(2)
[101]
1
0
1
No Change
[100]
[111]
[110]
1
1
0
[111]
No Change
[111]
(2)
[111]
1
1
1
No Change
[110]
No Change
sharp
L R S 1 8 2 8
12
5.5 Block Locking State Transitions upon F-WP Transition
(4)
Notes:
1. "F-WP = 0
1" means that F-WP is driven to V
IH
and "F-WP = 1
0" means that F-WP is driven to V
IL
.
2. State transition from the current state [011] to the next state depends on the previous state.
3. When F-WP is driven to V
IL
in [110] state, the state changes to [011] and the blocks are automatically locked.
4. In this state transitions table, assumes that lock configuration commands are not written in previous, current and next state.
Previous State
Current State
Result after F-WP Transition (Next State)
State
F-WP
DQ
1
DQ
0
F-WP = 0
1
(1)
F-WP = 1
0
(1)
-
[000]
0
0
0
[100]
-
-
[001]
0
0
1
[101]
-
[110]
(2)
[011]
0
1
1
[110]
-
Other than [110]
(2)
[111]
-
-
[100]
1
0
0
-
[000]
-
[101]
1
0
1
-
[001]
-
[110]
1
1
0
-
[011]
(3)
-
[111]
1
1
1
-
[011]
sharp
L R S 1 8 2 8
13
6. Status Register Definition
Status Register Definition
R
R
R
R
R
R
R
R
15
14
13
12
11
10
9
8
WSMS
BESS
BEFCES
PBPS
VPPS
PBPSS
DPS
R
7
6
5
4
3
2
1
0
SR.15 - SR.8 = RESERVED FOR FUTURE
ENHANCEMENTS (R)
SR.7 = WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
SR.6 = BLOCK ERASE SUSPEND STATUS (BESS)
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
SR.5 = BLOCK ERASE AND FULL CHIP ERASE
STATUS (BEFCES)
1 = Error in Block Erase or Full Chip Erase
0 = Successful Block Erase or Full Chip Erase
SR.4 = (PAGE BUFFER) PROGRAM STATUS (PBPS)
1 = Error in (Page Buffer) Program
0 = Successful (Page Buffer) Program
SR.3 = F-V
PP
STATUS (VPPS)
1 = F-V
PP
LOW Detect, Operation Abort
0 = F-V
PP
OK
SR.2 = (PAGE BUFFER) PROGRAM SUSPEND
STATUS (PBPSS)
1 = (Page Buffer) Program Suspended
0 = (Page Buffer) Program in Progress/Completed
SR.1 = DEVICE PROTECT STATUS (DPS)
1 = Erase or Program Attempted on a
Locked Block, Operation Abort
0 = Unlocked
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
Notes:
Status Register indicates the status of the partition, not WSM
(Write State Machine). Even if the SR.7 is "1", the WSM may
be occupied by the other partition when the device is set to 2, 3
or 4 partitions configuration.
Check SR.7 or F-RY/BY to determine block erase, full chip
erase, (page buffer) program completion. SR.6 - SR.1 are
invalid while SR.7= "0".
If both SR.5 and SR.4 are "1"s after a block erase, full chip
erase, page buffer program, set/clear block lock bit, set block
lock-down bit or set partition configuration register attempt, an
improper command sequence was entered.
SR.3 does not provide a continuous indication of F-V
PP
level.
The WSM interrogates and indicates the F-V
PP
level only after
Block Erase, Full Chip Erase, (Page Buffer) Program com-
mand sequences. SR.3 is not guaranteed to report accurate
feedback when F-V
PP
V
PPH
or V
PPLK
.
SR.1 does not provide a continuous indication of block lock
bit. The WSM interrogates the block lock bit only after Block
Erase, Full Chip Erase, (Page Buffer) Program command
sequences. It informs the system, depending on the attempted
operation, if the block lock bit is set. Reading the block lock
configuration codes after writing the Read Identifier Codes
command indicates block lock bit status.
SR.15 - SR.8 and SR.0 are reserved for future use and should
be masked out when polling the status register.
sharp
L R S 1 8 2 8
14
Extended Status Register Definition
R
R
R
R
R
R
R
R
15
14
13
12
11
10
9
8
SMS
R
R
R
R
R
R
R
7
6
5
4
3
2
1
0
XSR.15-8 = RESERVED FOR FUTURE
ENHANCEMENTS (R)
XSR.7 = STATE MACHINE STATUS (SMS)
1 = Page Buffer Program available
0 = Page Buffer Program not available
XSR.6-0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
Notes:
After issue a Page Buffer Program command (E8H),
XSR.7="1" indicates that the entered command is accepted. If
XSR.7 is "0", the command is not accepted and a next Page
Buffer Program command (E8H) should be issued again to
check if page buffer is available or not.
XSR.15-8 and XSR.6-0 are reserved for future use and should
be masked out when polling the extended status register.
sharp
L R S 1 8 2 8
15
Partition Configuration Register Definition
Partition Configuration
R
R
R
R
R
PC2
PC1
PC0
15
14
13
12
11
10
9
8
R
R
R
R
R
R
R
R
7
6
5
4
3
2
1
0
PCR.15-11 = RESERVED FOR FUTURE
ENHANCEMENTS (R)
PCR.10-8 = PARTITION CONFIGURATION (PC2-0)
000 = No partitioning. Dual Work is not allowed.
001 = Plane1-3 are merged into one partition.
(default in a bottom parameter device)
010 = Plane 0-1 and Plane2-3 are merged into one
partition respectively.
100 = Plane 0-2 are merged into one partition.
(default in a top parameter device)
011 = Plane 2-3 are merged into one partition. There are
three partitions in this configuration. Dual work
operation is available between any two partitions.
110 = Plane 0-1 are merged into one partition. There are
three partitions in this configuration. Dual work
operation is available between any two partitions.
101 = Plane 1-2 are merged into one partition. There are
three partitions in this configuration. Dual work
operation is available between any two partitions.
111 = There are four partitions in this configuration.
Each plane corresponds to each partition
respectively. Dual work operation is available
between any two partitions.
PCR.7-0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
Notes:
After power-up or device reset, PCR10-8 (PC2-0) is set to
"001" in a bottom parameter device and "100" in a top
parameter device.
See the table below for more details.
PCR.15-11 and PCR.7-0 are reserved for future use and should
be masked out when polling the partition configuration
register.
PLANE1
PLANE0
PLANE2
PLANE3
PARTITION1
PLANE1
PLANE0
PLANE2
PLANE3
PARTITION0
PLANE1
PLANE0
PLANE2
PLANE3
PARTITION0
PLANE1
PLANE0
PLANE2
PLANE3
PARTITION0
PARTITION1
PARTITION1
PARTITION0
PLANE1
PLANE0
PLANE2
PLANE3
PARTITION1
PLANE1
PLANE0
PLANE2
PLANE3
PARTITION0
PLANE1
PLANE0
PLANE2
PLANE3
PARTITION0
PLANE1
PLANE0
PLANE2
PLANE3
PARTITION0
PARTITION1
PARTITION1
PARTITION0
PARTITION2
PARTITION3
PARTITION2
PARTITION2
PARTITION1
PARTITION2
0 0 0
0 0 1
0 1 0
1 0 0
0 1 1
1 1 0
1 0 1
1 1 1
PC2 PC1PC0
PARTITIONING FOR DUAL WORK
PARTITIONING FOR DUAL WORK
PC2 PC1PC0
sharp
L R S 1 8 2 8
16
7. Memory Map for Flash Memory
7.1 Memory Map - F
1
Selected (F
1
-CE = "V
IL
", F
2
-CE = "V
IH
")
6
5
4
3
2
1
0
7
4K-WORD
007000H - 007FFFH
4K-WORD
006000H - 006FFFH
4K-WORD
005000H - 005FFFH
4K-WORD
004000H - 004FFFH
4K-WORD
003000H - 003FFFH
4K-WORD
002000H - 002FFFH
4K-WORD
001000H - 001FFFH
4K-WORD
000000H - 000FFFH
PLANE2
(
UNIFORM
PLANE)
92
93
94
95
64
65
72
73
74
75
32K-WORD
278000H - 27FFFFH
32K-WORD
270000H - 277FFFH
32K-WORD
268000H - 26FFFFH
32K-WORD
260000H - 267FFFH
32K-WORD
258000H - 25FFFFH
32K-WORD
250000H - 257FFFH
32K-WORD
248000H - 24FFFFH
32K-WORD
240000H - 247FFFH
32K-WORD
238000H - 23FFFFH
32K-WORD
230000H - 237FFFH
32K-WORD
228000H - 22FFFFH
32K-WORD
220000H - 227FFFH
32K-WORD
218000H - 21FFFFH
32K-WORD
210000H - 217FFFH
32K-WORD
208000H - 20FFFFH
32K-WORD
200000H - 207FFFH
2F8000H - 2FFFFFH
2F0000H - 2F7FFFH
2E8000H - 2EFFFFH
2E0000H - 2E7FFFH
2D8000H - 2DFFFFH
2D0000H - 2D7FFFH
2C8000H - 2CFFFFH
2C0000H - 2C7FFFH
2B8000H - 2BFFFFH
2B0000H - 2B7FFFH
2A8000H - 2AFFFFH
2A0000H - 2A7FFFH
298000H - 29FFFFH
290000H - 297FFFH
288000H - 28FFFFH
280000H - 287FFFH
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
76
78
79
80
81
82
83
77
84
85
66
68
69
70
71
67
86
88
89
90
91
87
PLANE1
(
UNIFORM
PLANE)
BLOCK NUMBER ADDRESS RANGE
62
63
32
33
34
35
42
43
44
45
32K-WORD
178000H - 17FFFFH
32K-WORD
170000H - 177FFFH
32K-WORD
168000H - 16FFFFH
32K-WORD
160000H - 167FFFH
32K-WORD
158000H - 15FFFFH
32K-WORD
150000H - 157FFFH
32K-WORD
148000H - 14FFFFH
32K-WORD
140000H - 147FFFH
32K-WORD
138000H - 13FFFFH
32K-WORD
130000H - 137FFFH
32K-WORD
128000H - 12FFFFH
32K-WORD
120000H - 127FFFH
32K-WORD
118000H - 11FFFFH
32K-WORD
110000H - 117FFFH
32K-WORD
108000H - 10FFFFH
32K-WORD
100000H - 107FFFH
1F8000H - 1FFFFFH
1F0000H - 1F7FFFH
1E8000H - 1EFFFFH
1E0000H - 1E7FFFH
1D8000H - 1DFFFFH
1D0000H - 1D7FFFH
1C8000H - 1CFFFFH
1C0000H - 1C7FFFH
1B8000H - 1BFFFFH
1B0000H - 1B7FFFH
1A8000H - 1AFFFFH
1A0000H - 1A7FFFH
198000H - 19FFFFH
190000H - 197FFFH
188000H - 18FFFFH
180000H - 187FFFH
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
46
48
49
50
51
52
53
47
54
55
36
38
39
40
41
37
56
58
59
60
61
57
12
13
14
15
32K-WORD
078000H - 07FFFFH
32K-WORD
070000H - 077FFFH
32K-WORD
068000H - 06FFFFH
32K-WORD
060000H - 067FFFH
32K-WORD
058000H - 05FFFFH
32K-WORD
050000H - 057FFFH
32K-WORD
PLANE0
(
PARAMETER
PLANE)
048000H - 04FFFFH
32K-WORD
040000H - 047FFFH
32K-WORD
038000H - 03FFFFH
32K-WORD
030000H - 037FFFH
32K-WORD
028000H - 02FFFFH
32K-WORD
020000H - 027FFFH
32K-WORD
018000H - 01FFFFH
32K-WORD
010000H - 017FFFH
32K-WORD
008000H - 00FFFFH
0F8000H - 0FFFFFH
0F0000H - 0F7FFFH
0E8000H - 0EFFFFH
0E0000H - 0E7FFFH
0D8000H - 0DFFFFH
0D0000H - 0D7FFFH
0C8000H - 0CFFFFH
0C0000H - 0C7FFFH
0B8000H - 0BFFFFH
0B0000H - 0B7FFFH
0A8000H - 0AFFFFH
0A0000H - 0A7FFFH
098000H - 09FFFFH
090000H - 097FFFH
088000H - 08FFFFH
080000H - 087FFFH
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
16
18
19
20
21
22
23
17
24
25
8
9
10
11
26
28
29
30
31
27
127
128
129
130
131
132
133
32K-WORD
PLANE3
(
UNIFORM
PLANE)
3F8000H - 3FFFFFH
122
123
124
102
103
104
105
32K-WORD
378000H - 37FFFFH
32K-WORD
370000H - 377FFFH
32K-WORD
368000H - 36FFFFH
32K-WORD
360000H - 367FFFH
32K-WORD
358000H - 35FFFFH
32K-WORD
350000H - 357FFFH
32K-WORD
348000H - 34FFFFH
32K-WORD
340000H - 347FFFH
32K-WORD
338000H - 33FFFFH
32K-WORD
330000H - 337FFFH
32K-WORD
328000H - 32FFFFH
32K-WORD
320000H - 327FFFH
32K-WORD
318000H - 31FFFFH
32K-WORD
310000H - 317FFFH
32K-WORD
308000H - 30FFFFH
32K-WORD
300000H - 307FFFH
3F0000H - 3F7FFFH
3E8000H - 3EFFFFH
3E0000H - 3E7FFFH
3D8000H - 3DFFFFH
3D0000H - 3D7FFFH
3C8000H - 3CFFFFH
3C0000H - 3C7FFFH
3B8000H - 3BFFFFH
3B0000H - 3B7FFFH
3A8000H - 3AFFFFH
3A0000H - 3A7FFFH
398000H - 39FFFFH
390000H - 397FFFH
388000H - 38FFFFH
380000H - 387FFFH
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
106
108
109
110
111
112
113
107
114
115
96
98
99
100
101
97
116
118
119
120
121
117
125
126
134
BLOCK NUMBER ADDRESS RANGE
Bottom Parameter
sharp
L R S 1 8 2 8
17
7.2 Memory Map - F
2
Selected (F
1
-CE = "V
IH
", F
2
-CE = "V
IL
")
127
128
129
130
131
132
133
4K-WORD
3FF000H - 3FFFFFH
4K-WORD
3FE000H - 3FEFFFH
4K-WORD
3FD000H - 3FDFFFH
4K-WORD
3FC000H - 3FCFFFH
4K-WORD
3FB000H - 3FBFFFH
4K-WORD
3FA000H - 3FAFFFH
4K-WORD
PLANE3
(
PARAMETER
PLANE)
3F9000H - 3F9FFFH
3F8000H - 3F8FFFH
PLANE2
(
UNIFORM
PLANE)
0
1
2
3
4
5
12
13
14
15
32K-WORD
078000H - 07FFFFH
32K-WORD
070000H - 077FFFH
32K-WORD
068000H - 06FFFFH
32K-WORD
060000H - 067FFFH
32K-WORD
058000H - 05FFFFH
32K-WORD
050000H - 057FFFH
32K-WORD
PLANE0
(
UNIFORM
PLANE)
048000H - 04FFFFH
32K-WORD
040000H - 047FFFH
32K-WORD
038000H - 03FFFFH
32K-WORD
030000H - 037FFFH
32K-WORD
028000H - 02FFFFH
32K-WORD
020000H - 027FFFH
32K-WORD
018000H - 01FFFFH
32K-WORD
010000H - 017FFFH
32K-WORD
008000H - 00FFFFH
32K-WORD
000000H - 007FFFH
0F8000H - 0FFFFFH
0F0000H - 0F7FFFH
0E8000H - 0EFFFFH
0E0000H - 0E7FFFH
0D8000H - 0DFFFFH
0D0000H - 0D7FFFH
PLANE1
(
UNIFORM
PLANE)
0C8000H - 0CFFFFH
0C0000H - 0C7FFFH
0B8000H - 0BFFFFH
0B0000H - 0B7FFFH
0A8000H - 0AFFFFH
0A0000H - 0A7FFFH
098000H - 09FFFFH
090000H - 097FFFH
088000H - 08FFFFH
080000H - 087FFFH
BLOCK NUMBER ADDRESS RANGE
BLOCK NUMBER ADDRESS RANGE
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
16
18
19
20
21
22
23
17
24
25
6
8
9
10
11
7
26
28
29
30
31
27
62
63
32
33
34
35
42
43
44
45
32K-WORD
178000H - 17FFFFH
32K-WORD
170000H - 177FFFH
32K-WORD
168000H - 16FFFFH
32K-WORD
160000H - 167FFFH
32K-WORD
158000H - 15FFFFH
32K-WORD
150000H - 157FFFH
32K-WORD
148000H - 14FFFFH
32K-WORD
140000H - 147FFFH
32K-WORD
138000H - 13FFFFH
32K-WORD
130000H - 137FFFH
32K-WORD
128000H - 12FFFFH
32K-WORD
120000H - 127FFFH
32K-WORD
118000H - 11FFFFH
32K-WORD
110000H - 117FFFH
32K-WORD
108000H - 10FFFFH
32K-WORD
100000H - 107FFFH
1F8000H - 1FFFFFH
1F0000H - 1F7FFFH
1E8000H - 1EFFFFH
1E0000H - 1E7FFFH
1D8000H - 1DFFFFH
1D0000H - 1D7FFFH
1C8000H - 1CFFFFH
1C0000H - 1C7FFFH
1B8000H - 1BFFFFH
1B0000H - 1B7FFFH
1A8000H - 1AFFFFH
1A0000H - 1A7FFFH
198000H - 19FFFFH
190000H - 197FFFH
188000H - 18FFFFH
180000H - 187FFFH
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
46
48
49
50
51
52
53
47
54
55
36
38
39
40
41
37
56
58
59
60
61
57
92
93
94
95
64
65
72
73
74
75
32K-WORD
278000H - 27FFFFH
32K-WORD
270000H - 277FFFH
32K-WORD
268000H - 26FFFFH
32K-WORD
260000H - 267FFFH
32K-WORD
258000H - 25FFFFH
32K-WORD
250000H - 257FFFH
32K-WORD
248000H - 24FFFFH
32K-WORD
240000H - 247FFFH
32K-WORD
238000H - 23FFFFH
32K-WORD
230000H - 237FFFH
32K-WORD
228000H - 22FFFFH
32K-WORD
220000H - 227FFFH
32K-WORD
218000H - 21FFFFH
32K-WORD
210000H - 217FFFH
32K-WORD
208000H - 20FFFFH
32K-WORD
200000H - 207FFFH
2F8000H - 2FFFFFH
2F0000H - 2F7FFFH
2E8000H - 2EFFFFH
2E0000H - 2E7FFFH
2D8000H - 2DFFFFH
2D0000H - 2D7FFFH
2C8000H - 2CFFFFH
2C0000H - 2C7FFFH
2B8000H - 2BFFFFH
2B0000H - 2B7FFFH
2A8000H - 2AFFFFH
2A0000H - 2A7FFFH
298000H - 29FFFFH
290000H - 297FFFH
288000H - 28FFFFH
280000H - 287FFFH
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
76
78
79
80
81
82
83
77
84
85
66
68
69
70
71
67
86
88
89
90
91
87
122
123
124
102
103
104
105
32K-WORD
378000H - 37FFFFH
32K-WORD
370000H - 377FFFH
32K-WORD
368000H - 36FFFFH
32K-WORD
360000H - 367FFFH
32K-WORD
358000H - 35FFFFH
32K-WORD
350000H - 357FFFH
32K-WORD
348000H - 34FFFFH
32K-WORD
340000H - 347FFFH
32K-WORD
338000H - 33FFFFH
32K-WORD
330000H - 337FFFH
32K-WORD
328000H - 32FFFFH
32K-WORD
320000H - 327FFFH
32K-WORD
318000H - 31FFFFH
32K-WORD
310000H - 317FFFH
32K-WORD
308000H - 30FFFFH
32K-WORD
300000H - 307FFFH
3F0000H - 3F7FFFH
3E8000H - 3EFFFFH
3E0000H - 3E7FFFH
3D8000H - 3DFFFFH
3D0000H - 3D7FFFH
3C8000H - 3CFFFFH
3C0000H - 3C7FFFH
3B8000H - 3BFFFFH
3B0000H - 3B7FFFH
3A8000H - 3AFFFFH
3A0000H - 3A7FFFH
398000H - 39FFFFH
390000H - 397FFFH
388000H - 38FFFFH
380000H - 387FFFH
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
106
108
109
110
111
112
113
107
114
115
96
98
99
100
101
97
116
118
119
120
121
117
125
126
134
4K-WORD
Top Parameter
sharp
L R S 1 8 2 8
18
8. Absolute Maximum Ratings
Notes:
1. The maximum applicable voltage on any pins with respect to GND.
2. Except F-V
PP
.
3. -1.0V undershoot is allowed when the pulse width is less than 5 nsec.
4. V
IN
should not be over V
CC
+0.4V.
9. Recommended DC Operating Conditions
(T
A
= -30C to +85C)
Notes:
1. V
CC
is the lower of F-V
CC
or S-V
CC
.
2. V
CC
is the higher of F-V
CC
or S-V
CC
.
10. Pin Capacitance
(1)
(T
A
= 25C, f = 1MHz)
Note:
1. Sampled but not 100% tested.
Symbol
Parameter
Notes
Ratings
Unit
V
CC
Supply voltage
1,2
-0.2
to
+3.9
V
V
IN
Input voltage
1,2,3,4
-0.5
to
V
CC
+0.4
V
T
A
Operating temperature
-30
to
+85
C
T
STG
Storage temperature
-55
to
+125
C
F-V
PP
F-V
PP
voltage
1,3
-0.2
to
+12.6
V
Symbol
Parameter
Notes
Min.
Typ.
Max.
Unit
F-V
CC
Supply Voltage
2.7
3.0
3.3
V
S-V
CC
Supply Voltage
2.7
3.1
V
V
PP
F-V
PP
Voltage (Write Operation)
1.65
3.3
V
F-V
PP
Voltage (Read Operation)
0
3.3
V
V
IH
Input Voltage
V
CC
-0.4
(2)
V
CC
+0.3
(1)
V
V
IL
Input Voltage
-0.3
0.4
V
Symbol
Parameter
Notes
Min.
Typ.
Max.
Unit
Condition
C
IN
Input capacitance
20
pF
V
IN
= 0V
C
I/O
I/O capacitance
30
pF
V
I/O
= 0V
sharp
L R S 1 8 2 8
19
11. DC Electrical Characteristics
(1, 12)
DC Electrical Characteristics
(T
A
= -30C to +85C, F-V
CC
= 2.7V to 3.3V, S-V
CC
= 2.7V to 3.1V)
Symbol
Parameter
Notes
Min.
Typ.
Max.
Unit
Test Conditions
I
LI
Input Leakage Current
2.5
A
V
IN
= V
CC
or GND
I
LO
Output Leakage Current
2.5
A
V
OUT
= V
CC
or GND
I
CCS
F-V
CC
Standby Current
2,14
8
40
A
F-V
CC
= F-V
CC
Max.,
F-CE = F-RST = F-V
CC
0.2V,
F-WP = F-V
CC
or GND
I
CCAS
F-V
CC
Automatic Power Savings
Current
2,5,10
8
40
A
F-V
CC
= F-V
CC
Max.,
F-CE = GND 0.2V,
F-WP = F-V
CC
or GND
I
CCD
F-V
CC
Reset Power-Down Current
2
8
40
A
F-RST = GND 0.2V
I
OUT
(F-RY/BY) = 0mA
I
CCR
Average F-V
CC
Read Current
Normal Mode
2,10,13
16
26
mA
F-V
CC
= F-V
CC
Max.,
F-CE = V
IL
, F-OE = V
IH
, f = 5MHz
I
OUT
= 0mA
Average F-V
CC
Read Current
Page Mode
8 Word Read
2,10,13
6
11
mA
I
CCW
F-V
CC
(Page Buffer) Program Current 2,6,11,13
21
61
mA
F-V
PP
= V
PPH
I
CCE
F-V
CC
Block Erase, Full Chip
Erase Current
2,6,11,13
11
31
mA
F-V
PP
= V
PPH
I
CCWS
I
CCES
F-V
CC
(Page Buffer) Program or
Block Erase Suspend Current
2,3,13
10
200
A
F-CE = V
IH
I
PPS
I
PPR
F-V
PP
Standby or Read Current
2,7,13
4
10
A
F-V
PP
F-V
CC
I
PPW
F-V
PP
(Page Buffer) Program Current
2,6,7,11,13
2
5
A
F-V
PP
= V
PPH
I
PPE
F-V
PP
Block Erase, Full Chip
Erase Current
2,6,7,11,13
2
5
A
F-V
PP
= V
PPH
I
PPWS
F-V
PP
(Page Buffer) Program
Suspend Current
2,7,13
2
5
A
F-V
PP
= V
PPH
I
PPES
F-V
PP
Block Erase Suspend Current
2,7,13
2
5
A
F-V
PP
= V
PPH
sharp
L R S 1 8 2 8
20
DC Electrical Characteristics (Continue)
(T
A
= -30C to +85C, F-V
CC
= 2.7V to 3.3V, S-V
CC
= 2.7V to 3.1V)
Notes:
1. V
CC
includes both F-V
CC
and S-V
CC
.
2. All currents are in RMS unless otherwise noted. Typical values are the reference values at V
CC
= 3.0V and T
A
= +25 C
unless V
CC
is specified.
3. I
CCWS
and I
CCES
are specified with the device de-selected. If read or (page buffer) program while in block erase suspend
mode, the device's current draw is the sum of I
CCWS
or I
CCES
and I
CCR
or I
CCW
, respectively.
4. Block erase, full chip erase, (page buffer) program are inhibited when V
PP
V
PPLK
, and not guaranteed outside the
specified voltage.
5. The Automatic Power Savings (APS) feature automatically places the device in power save mode after read cycle
completion. Standard address access timings (t
AVQV
) provide new data when addresses are changed.
6. Sampled, not 100% tested.
7. F-V
PP
is not used for power supply pin. With F-V
PP
V
PPLK
, block erase, full chip erase, (page buffer) program cannot be
executed and should not be attempted.
Applying 12V 0.3V to F-V
PP
provides fast erasing or fast programming mode. In this mode, F-V
PP
is power supply pin
and supplies the memory cell current for block erasing and (page buffer) programming. Use similar power supply trace
widths and layout considerations given to the V
CC
power bus.
Applying 12V 0.3V to F-V
PP
during erase/program can only be done for a maximum of 1000 cycles on each block.
F-V
PP
may be connected to 12V 0.3V for a total of 80 hours maximum.
8. Memory cell data is held. (S-CE
2
= "V
IH
")
9. Memory cell data is not held. (S-CE
2
= "V
IL
")
10. Never hold F
1
-CE low and F
2
-CE low at the same timing.
11. F
1
and F
2
should not be operated at the same timing to Block erase, full chip erase, (page buffer) program.
12. The current value about Flash memory expresses the consumption current per one chip. The consumption current of the
whole Flash memory becomes the value which added of F
1
and F
2
.
13. The operating current in dual work is the sum of the operating current (read, erase, program) in each plane.
14. Includes F-RY/BY.
Symbol
Parameter
Notes
Min.
Typ.
Max.
Unit
Test Conditions
I
SB
S-V
CC
Standby Current
8
100
A
S-CE
1
, S-CE
2
S-V
CC
- 0.2V
I
SLP
S-V
CC
Sleep Mode Current
9
30
A
S-CE
1
S-V
CC
- 0.2V, S-CE
2
0.2V
I
CC1
S-V
CC
Operation Current
50
mA
t
CYCLE
= Min., I
I/O
= 0mA, S-CE
1
= V
IL
V
IL
Input Low Voltage
6
-0.3
0.4
V
V
IH
Input High Voltage
6
V
CC
-0.4
V
CC
+0.3
V
V
OL
Output Low Voltage
6,14
0.2V
CC
V
I
OL
= 0.5mA
V
OH
Output High Voltage
6
0.8V
CC
V
I
OH
= -0.5mA
V
PPLK
F-V
PP
Lockout during Normal
Operations
4,6,7
0.4
V
V
PPH
F-V
PP
during Block Erase, Full Chip
Erase,(PageBuffer) Program
7
1.65
3
3.3
V
V
LKO
F-V
CC
Lockout Voltage
1.5
V
sharp
L R S 1 8 2 8
21
12. AC Electrical Characteristics for Flash Memory
12.1 AC Test Conditions
12.2 Read Cycle
(T
A
= -30C to +85C, F-V
CC
= 2.7V to 3.3V)
Notes:
1. Sampled, not 100% tested.
2. F-OE may be delayed up to t
ELQV
t
GLQV
after the falling edge of F-CE without impact to t
ELQV
.
Input pulse level
0 V to 2.7 V
Input rise and fall time
5 ns
Input and Output timing Ref. level
1.35 V
Output load
1TTL + C
L
(50pF)
Symbol
Parameter
Notes
Min.
Max.
Unit
t
AVAV
Read Cycle Time
65
ns
t
AVQV
Address to Output Delay
65
ns
t
ELQV
F-CE to Output Delay
2
65
ns
t
APA
Page Address Access Time
25
ns
t
GLQV
F-OE to Output Delay
2
20
ns
t
PHQV
F-RST High to Output Delay
150
ns
t
EHQZ
, t
GHQZ
F-CE or F-OE to Output in High-Z, Whichever Occurs First
1
20
ns
t
ELQX
F-CE to Output in Low-Z
1
0
ns
t
GLQX
F-OE to Output in Low-Z
1
0
ns
t
OH
Output Hold from First Occurring Address, F-CE or F-OE change
1
0
ns
sharp
L R S 1 8 2 8
22
12.3 Write Cycle (F-WE / F-CE Controlled)
(1,2,9)
(T
A
= -30C to +85C, F-V
CC
= 2.7V to 3.3V)
Notes:
1. The timing characteristics for reading the status register during block erase, full chip erase, (page buffer) program
operations are the same as during read-only operations. See the AC Characteristics for read cycle.
2. A write operation can be initiated and terminated with either F-CE or F-WE.
3. Sampled, not 100% tested.
4. Write pulse width (t
WP
) is defined from the falling edge of F-CE or F-WE (whichever goes low last) to the rising edge of
F-CE or F-WE (whichever goes high first). Hence, t
WP
=t
WLWH
=t
ELEH
=t
WLEH
=t
ELWH
.
5. Write pulse width high (t
WPH
) is defined from the rising edge of F-CE or F-WE (whichever goes high first) to the falling
edge of F-CE or F-WE (whichever goes low last). Hence, t
WPH
=t
WHWL
=t
EHEL
=t
WHEL
=t
EHWL
.
6. F-V
PP
should be held at F-V
PP
=V
PPH
until determination of block erase, (page buffer) program success (SR.1/3/4/5=0)
and held at F-V
PP
=V
PPH
until determination of full chip erase success (SR.1/3/5=0).
7. t
WHR0
(t
EHR0
) after the Read Query or Read Identifier Codes command=t
AVQV
+100ns.
8. See 5.1 Command Definitions for valid address and data for block erase, full chip erase, (page buffer) program or lock bit
configuration.
9. F
1
and F
2
should not be operated at the same timing to Block erase, full chip erase, (page buffer) program .
Symbol
Parameter
Notes
Min.
Max.
Unit
t
AVAV
Write Cycle Time
65
ns
t
PHWL
(t
PHEL
)
F-RST High Recovery to F-WE (F-CE) Going Low
3
150
ns
t
ELWL
(t
WLEL
)
F-CE (F-WE) Setup to F-WE (F-CE) Going Low
4
0
ns
t
WLWH
(t
ELEH
)
F-WE (F-CE) Pulse Width
4
50
ns
t
DVWH
(t
DVEH
) Data Setup to F-WE (F-CE) Going High
8
40
ns
t
AVWH
(t
AVEH
)
Address Setup to F-WE (F-CE) Going High
8
50
ns
t
WHEH
(t
EHWH
) F-CE (F-WE) Hold from F-WE (F-CE) High
0
ns
t
WHDX
(t
EHDX
) Data Hold from F-WE (F-CE) High
0
ns
t
WHAX
(t
EHAX
) Address Hold from F-WE (F-CE) High
0
ns
t
WHWL
(t
EHEL
)
F-WE (F-CE) Pulse Width High
5
15
ns
t
SHWH
(t
SHEH
)
F-WP High Setup to F-WE (F-CE) Going High
3
0
ns
t
VVWH
(t
VVEH
) F-V
PP
Setup to F-WE (F-CE) Going High
3
200
ns
t
WHGL
(t
EHGL
)
Write Recovery before Read
30
ns
t
QVSL
F-WP High Hold from Valid SRD, F-RY/BY High-Z
3, 6
0
ns
t
QVVL
F-V
PP
Hold from Valid SRD, F-RY/BY High-Z
3, 6
0
ns
t
WHR0
(t
EHR0
)
F-WE (F-CE) High to SR.7 Going "0"
3, 7
t
AVQV
+50
ns
t
WHRL
(t
EHRL
)
F-WE (F-CE) High to F-RY/BY Going Low
3
100
ns
sharp
L R S 1 8 2 8
23
12.4 Block Erase, Full Chip Erase, (Page Buffer) Program Performance
(3)
(T
A
= -30C to +85C, F-V
CC
= 2.7V to 3.3V)
Notes:
1. Typical values measured at F-V
CC
=3.0V, F-V
PP
=3.0V, and T
A
=+25 C. Assumes corresponding lock bits are not set.
Subject to change based on device characterization.
2. Excludes external system-level overhead.
3. Sampled, but not 100% tested.
4. A latency time is required from writing suspend command (F-WE or F-CE going high) until SR.7 going "1"or F-RY/BY
going High-Z.
5. If the interval time from a Block Erase Resume command to a subsequent Block Erase Suspend command is shorter than
t
ERES
and its sequence is repeated, the block erase operation may not be finished.
Symbol
Parameter
Notes
Page Buffer
Command
is Used or
not Used
F-V
PP
=V
PPH
(In System)
Unit
Min.
Typ.
(1)
Max.
(2)
t
WPB
4K-Word Parameter Block
Program Time
2
Not Used
0.05
0.3
s
2
Used
0.03
0.12
s
t
WMB
32K-Word Main Block
Program Time
2
Not Used
0.38
2.4
s
2
Used
0.24
1
s
t
WHQV1
/
t
EHQV1
Word Program Time
2
Not Used
11
200
s
2
Used
7
100
s
t
WHQV2
/
t
EHQV2
4K-Word Parameter Block
Erase Time
2
-
0.3
4
s
t
WHQV3
/
t
EHQV3
32K-Word Main Block
Erase Time
2
-
0.6
5
s
Full Chip Erase Time
2
80
700
s
t
WHRH1
/
t
EHRH1
(Page Buffer) Program Suspend
Latency Time to Read
4
-
5
10
s
t
WHRH2
/
t
EHRH2
Block Erase Suspend
Latency Time to Read
4
-
5
20
s
t
ERES
Latency Time from Block Erase
Resume Command to Block
Erase Suspend Command
5
-
500
s
sharp
L R S 1 8 2 8
24
12.5 Flash Memory AC Characteristics Timing Chart
AC Waveform for Single Asynchronous Read Operations from Status Register, Identifier Codes or Query Code
t
AVQV
t
EHQZ
t
GHQZ
t
ELQV
t
PHQV
t
GLQV
t
OH
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
IH
V
IL
(P)
(D/Q)
(W)
(G)
(E)
(A)
A
21-0
DQ
15-0
F-CE
F-OE
F-WE
F-RST
High-Z
t
ELQX
VALID
OUTPUT
VALID
ADDRESS
t
GLQX
t
AVAV
sharp
L R S 1 8 2 8
25
AC Waveform for Asynchronous 4-Word Page Mode Read Operations from Main Blocks or Parameter Blocks
t
AVQV
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
t
AVAV
t
ELQV
t
EHQZ
t
GHQZ
t
OH
t
APA
t
GLQV
t
PHQV
High-Z
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
IH
V
IL
(P)
(D/Q)
(W)
(G)
(E)
(A)
A
21-3
V
IH
V
IL
(A)
A
2-0
DQ
15-0
F-CE
F-OE
F-WE
F-RST
t
GLQX
t
ELQX
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
sharp
L R S 1 8 2 8
26
AC Waveform for Asynchronous 8-Word Page Mode Read Operations from Main Blocks or Parameter Blocks
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
t
AVQV
t
ELQV
t
EHQZ
t
GHQZ
t
OH
t
APA
t
GLQV
t
PHQV
t
GLQX
t
ELQX
VALID
ADDRESS
t
AVAV
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
High Z
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
IH
V
IL
(P)
(D/Q)
(W)
(G)
(E)
(A)
A
21-3
V
IH
V
IL
(A)
A
2-0
DQ
15-0
F-CE
F-OE
F-WE
F-RST
sharp
L R S 1 8 2 8
27
AC Waveform for Write Operations(F-WE / F-CE Controlled)
t
AVAV
t
AVWH
(t
AVEH
)
t
WHAX
(t
EHAX
)
t
ELWL
(t
WLEL
)
t
PHWL
(t
PHEL
)
t
WLWH
t
WHWL
(t
EHEL
)
t
WHDX
(t
EHDX
)
t
DVWH
(t
DVEH
)
t
SHWH
(t
SHEH
)
t
VVWH
(t
VVEH
)
t
WHQV1,2,3
(t
EHQV1,2,3
)
t
QVSL
t
QVVL
t
WHEH
(t
EHWH
)
t
WHGL
(t
EHGL
)
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
(D/Q)
(W)
(G)
(E)
(A)
NOTES 5, 6
NOTES 5, 6
A
21-0
DQ
15-0
(V)
F-V
PP
V
IH
V
PPH1,2
V
PPLK
V
IL
V
IL
(P)
F-RST
F-CE
F-OE
F-WE
V
IH
V
IL
(S)
F-WP
(t
ELEH
)
NOTE 1
NOTE 2
NOTE 3
NOTE 4NOTE 5
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
DATA IN
DATA IN
VALID
SRD
Notes:
1. F-V
CC
power-up and standby.
2. Write each first cycle command.
3. Write each second cycle command or valid address and data.
4. Automated erase or program delay.
5. Read status register data.
6. For read operation, F-OE and F-CE must be driven active, and F-WE de-asserted.
(
1
)
(
0
)
(R)
(SR.7)
t
WHR0
(t
EHR0
)
F-RY/BY
High-Z
V
OL
t
WHRL
(t
EHRL
)
V
PPH
sharp
L R S 1 8 2 8
28
12.6 Reset Operations
(T
A
= -30C to +85C, F-V
CC
= 2.7V to 3.3V)
Notes:
1. A reset time, t
PHQV
, is required from the later of SR.7 (F-RY/BY) going "1" (High-Z) or F-RST going high until outputs
are valid. See the AC Characteristics - read cycle for t
PHQV
.
2. t
PLPH
is <100ns the device may still reset but this is not guaranteed.
3. Sampled, not 100% tested.
4. If F-RST asserted while a block erase, full chip erase or (page buffer) program operation is not executing, the reset will
complete within 100ns.
5. When the device power-up, holding F-RST low minimum 100ns is required after F-V
CC
has been in predefined range and
also has been in stable there.
AC Waveform for Reset Operation
Symbol
Parameter
Notes
Min.
Max.
Unit
t
PLPH
F-RST Low to Reset during Read
(F-RST should be low during power-up.)
1, 2, 3
100
ns
t
PLRH
F-RST Low to Reset during Erase or Program
1, 3, 4
22
s
t
VPH
F-V
CC
2.7V to F-RST High
1, 3, 5
100
ns
t
VHQV
F-V
CC
2.7V to Output Delay
3
1
ms
ABORT
COMPLETE
t
PLPH
t
PLPH
t
VPH
t
PLRH
t
PHQV
t
PHQV
(A) Reset during Read Array Mode
(B) Reset during Erase or Program Mode
(C) F-RST rising timing
F-RST
F-RST
V
IL
V
IH
V
IL
V
IH
F-V
CC
GND
2.7V
F-RST
V
IL
V
IH
SR.7=
1
V
OH
V
OL
(D/Q)
DQ
15-0
VALID
OUTPUT
High-Z
(P)
(P)
(P)
V
OH
V
OL
(D/Q)
DQ
15-0
VALID
OUTPUT
High-Z
V
OH
V
OL
(D/Q)
DQ
15-0
VALID
OUTPUT
High-Z
t
PHQV
t
VHQV
sharp
L R S 1 8 2 8
29
13. AC Electrical Characteristics for Smartcombo RAM
13.1 AC Test Conditions
Notes:
1. Including scope and socket capacitance.
2. AC characteristics directed with the note should be measured with the output load shown in below.
Input Pulse Level
0.2V
CC
to 0.8V
CC
Input Rise and Fall Time
5 ns
Input and Output Timing Ref. Level
1/2 V
CC
Output Load
1TTL +C
L
(50pF)
(1, 2)
DQ (Output)
Zo = 50
1/2 V
CC
C
L
50
sharp
L R S 1 8 2 8
30
13.2 Read Cycle
(T
A
= -30C to +85C, V
CC
= 2.7V to 3.1V)
Notes:
1. t
BHAH
is specified after both S-LB and S-UB are High.
2. t
CLOL
and t
OP
(Max.) are applied while S-CE
1
is being hold at low level.
Symbol
Parameter
Notes
Min.
Max.
Unit
t
RC
Read Cycle Time
65
ns
t
AA
Address Access Time
65
ns
t
ACE
Chip Enable Access Time
65
ns
t
OE
Output Enable to Output Valid
45
ns
t
BE
Byte Enable Access Time
65
ns
t
OH
Output Hold from Address Change
5
ns
t
CLZ
S-CE
1
Low to Output Active
10
ns
t
OLZ
S-OE Low to Output Active
5
ns
t
BLZ
S-UB or S-LB Low to Output Active
5
ns
t
CHZ
S-CE
1
High to Output in High-Z
25
ns
t
OHZ
S-OE High to Output in High-Z
25
ns
t
BHZ
S-UB or S-LB High to Output in High-Z
25
ns
t
ASO
Address Setup to S-OE Low
0
ns
t
OHAH
S-OE High Level to Address Hold
-5
ns
t
CHAH
S-CE
1
High Level to Address Hold
0
ns
t
BHAH
S-LB, S-UB High Level to Address Hold
1
0
ns
t
CLOL
S-CE
1
Low Level to S-OE Low Level
2
0
10,000
ns
t
OLCH
S-OE Low Level to S-CE
1
High Level
45
ns
t
CP
S-CE
1
High Level Pulse Width
10
ns
t
BP
S-LB, S-UB High Level Pulse Width
10
ns
t
OP
S-OE High Level Pulse Width
2
2
10,000
ns
sharp
L R S 1 8 2 8
31
13.3 Write Cycle
(T
A
= -30C to +85C, V
CC
= 2.7V to 3.1V)
Notes:
1. t
BHAH
is specified after both S-LB and S-UB are High.
2. t
OES
and t
OEH
(Max.) are applied while S-CE
1
is being hold at low level.
Symbol
Parameter
Notes
Min.
Max.
Unit
t
WC
Write Cycle Time
65
ns
t
CW
Chip Enable to End of Write
55
ns
t
AW
Address Valid to End of Write
55
ns
t
BW
Byte Select Time
55
ns
t
WP
Write Pulse Width
50
ns
t
WR
Write Recovery Time
0
ns
t
CP
S-CE
1
High Level Pulse Width
10
ns
t
BP
S-LB, S-UB High Level Pulse Width
10
ns
t
WHP
S-WE High Pulse Width
10
ns
t
WHZ
S-WE Low to Output in High-Z
25
ns
t
OW
S-WE High to Output Active
15
ns
t
AS
Address Setup Time
0
ns
t
OHAH
S-OE High Level to Address Hold
-5
ns
t
CHAH
S-CE
1
High Level to Address Hold
0
ns
t
BHAH
S-LB, S-UB High Level to Address Hold
1
0
ns
t
DW
Input Data Setup Time
30
ns
t
DH
Input Data Hold Time
0
ns
t
OES
S-OE High Level to S-WE Set
2
0
10,000
ns
t
OEH
S-WE High Level to S-OE Set
2
10
10,000
ns
sharp
L R S 1 8 2 8
32
13.4 Initialization
(T
A
= -30C to +85C, V
CC
= 2.7V to 3.1V)
Note:
1. When giving compatibility with the other type of Smartcombo RAM, 200s must be changed to 300s.
13.5 Sleep Mode Entry / Exit
(T
A
= -30C to +85C, V
CC
= 2.7V to 3.1V)
Symbol
Parameter
Notes
Min.
Max.
Unit
t
VHMH
Power Application to S-CE
2
Low Level Hold
50
s
t
CHMH
S-CE
1
High Level to S-CE
2
High Level
10
ns
t
MHCL
Following Power Application
S-CE
2
High Level Hold to S-CE
1
Low Level
1
200
s
Symbol
Parameter
Notes
Min.
Max.
Unit
t
CHML
Sleep Mode Entry
S-CE
1
High Level to S-CE
2
Low Level
0
ns
t
MHCL
Sleep Mode Exit to Normal Operation
S-CE
2
High Level to S-CE
1
Low Level
200
s
sharp
L R S 1 8 2 8
33
13.6 Initialization
Initialize the power application using the following sequence to stabilize internal circuits.
(1) Following power application, make S-CE
2
high level after fixing S-CE
2
to low level for the period of t
VHMH
.
Make S-CE
1
high level before making S-CE
2
high level.
(2) S-CE
1
and S-CE
2
are fixed to high level for the period of t
MHCL
.
Normal operation is possible after the completion of initialization.
Initialization
Normal Operation
t
CHMH
t
VHMH
t
MHCL
V
CC
(Min.)
V
IH
V
IL
V
IL
V
IH
S-CE
2
S-CE
1
V
CC
Notes:
1. Make S-CE
2
low level when starting the power supply.
2.
t
VHMH
is specified from when the power supply voltage reaches the prescribed minimum value (V
CC
Min.).
sharp
L R S 1 8 2 8
34
Standby Mode State Machine
Power On
Initial State
Active
Standby Mode
S-CE
1
= V
IL
,
S-CE
2
= V
IH
S-CE
1
= V
IL
S-CE
1
= V
IH
,
S-CE
2
= V
IH
Sleep mode
S-CE
1
= V
IH
or V
IL
, S-CE
2
= V
IL
Initialization
S-CE
1
= V
IH
or V
IL
,
S-CE
2
= V
IL
S-CE
2
= V
IH
sharp
L R S 1 8 2 8
35
13.7 Mode Register Settings
The sleep mode can be set using the mode register. Since the initial value of the mode register at power application is
undefined, be sure to set the mode register after initialization at power application.
13.8 Mode Register Setting Method
The mode register setting mode can be entered by successively writing two specific data after two continuous reads of
the highest address (1FFFFFH). The mode register setting is a continuous four-cycle operation (two read cycles and two
write cycles).
Commands are written to the command register. The command register is used to latch the addresses and data required
for executing commands, and it does not have an exclusive memory area.
For the timing chart and flow chart, refer to Mode Register Setting Timing Chart (P.46), Mode Register Setting Flow
Chart (P.47).
Following table shows the commands and command sequences.
Command Sequence
4th Bus Cycle (Write cycle)
13.9 Cautions for Setting Mode Register
Since, for the mode register setting, the internal counter status is judged by toggling S-CE
1
and S-OE, toggle S-CE
1
at
every cycle during entry (read cycle twice, write cycle twice), and toggle S-OE like S-CE
1
at the first and second read
cycles.
If incorrect addresses or data are written, or if addresses or data are written in the incorrect order, the setting of the mode
register are not performed correctly.
When the highest address (1FFFFFH) is read consecutively three or more times, the mode register setting entries are
cancelled.
Once the sleep mode has been set in the mode register, these settings are retained until they are set again, while applying
the power supply. However, the mode register setting will become undefined if the power is turned off, so set the mode
register again after power application.
For the timing chart and flow chart, refer to Mode Register Setting Timing Chart (P.46), Mode Register Setting Flow
Chart (P.47).
Command Sequence
1st Bus Cycle
(Read Cycle)
2nd Bus Cycle
(Read Cycle)
3rd Bus Cycle
(Write Cycle)
4th Bus Cycle
(Write Cycle)
Address
Data
Address
Data
Address
Data
Address
Data
Sleep Mode
1FFFFFH
-
1FFFFFH
-
1FFFFFH
00H
1FFFFFH
07H
DQ
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Mode Register Setting
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
sharp
L R S 1 8 2 8
36
13.10 Smartcombo RAM AC Characteristics Timing Chart
Read Cycle Timing Chart 1 (S-CE
1
Controlled)
V
IH
V
IL
Address
V
IH
V
IL
S-CE
1
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
S-OE
t
RC
S-UB
S-LB
t
ACE
t
ACE
t
CLZ
t
CHZ
t
CHAH
t
CHAH
t
CLZ
t
CHZ
t
CP
t
CP
t
RC
D
OUT
High - Z
High - Z
ADDRESS
STABLE
ADDRESS
STABLE
Note:
1. In read cycle, S-CE
2
and S-WE should be fixed to high level.
VALID
OUTPUT
VALID
OUTPUT
sharp
L R S 1 8 2 8
37
Read Cycle Timing Chart 2 (S-OE Controlled)
V
IH
V
IL
Address
V
IH
V
IL
S-CE
1
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
S-OE
t
RC
S-UB
S-LB
t
RC
t
AA
t
AA
t
OE
t
ASO
t
ASO
t
OE
t
ASO
t
OLZ
t
OHZ
t
OHAH
t
OHAH
t
BHAH
t
BHAH
t
OLZ
t
OHZ
t
OP
t
OP
D
OUT
High - Z
High - Z
VALID
OUTPUT
VALID
OUTPUT
ADDRESS
STABLE
ADDRESS
STABLE
Note:
1. In read cycle, S-CE
2
and S-WE should be fixed to high level.
sharp
L R S 1 8 2 8
38
Read Cycle Timing Chart 3 (S-CE
1
/ S-OE Controlled)
V
IH
V
IL
Address
V
IH
V
IL
S-CE
1
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
S-OE
t
RC
S-UB
S-LB
t
RC
t
ACE
t
CLZ
t
CHZ
t
OHAH
t
OE
t
CLOL
t
OE
t
ASO
t
OLZ
t
OLZ
t
OHZ
t
OHAH
t
BHAH
t
AA
t
CHAH
t
BHAH
D
OUT
VALID
OUTPUT
VALID
OUTPUT
High - Z
High - Z
ADDRESS
STABLE
ADDRESS
STABLE
t
OHZ
Note:
1. In read cycle, S-CE
2
and S-WE should be fixed to high level.
sharp
L R S 1 8 2 8
39
Read Cycle Timing Chart 4 (Address Controlled)
V
IH
V
IL
Address
V
IH
V
IL
S-CE
1
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
S-OE
t
RC
S-UB
S-LB
t
RC
t
AA
t
AA
t
OH
t
OH
t
OH
D
OUT
VALID
OUTPUT
VALID
OUTPUT
ADDRESS
STABLE
ADDRESS
STABLE
Notes:
1. In read cycle,S-CE
2
and S-WE should be fixed to high level.
2. When the minimum read cycle time is less than t
RC
,the address access time (t
AA
) is not guaranteed.
sharp
L R S 1 8 2 8
40
Read Cycle Timing Chart 5 (S-LB / S-UB Controlled)
V
IH
V
IL
Address
V
IH
V
IL
S-CE
1
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
S-OE
t
RC
S-UB
S-LB
t
BLZ
t
BE
t
BHZ
t
BHAH
t
BP
D
OUT
VALID
OUTPUT
VALID
OUTPUT
t
RC
t
BLZ
t
BE
t
BHZ
t
BHAH
t
BP
High - Z
ADDRESS
STABLE
ADDRESS
STABLE
Note:
1. In read cycle, S-CE
2
and S-WE should be fixed to high level.
sharp
L R S 1 8 2 8
41
Write Cycle Timing Chart 1 (S-CE
1
Controlled)
V
IH
V
IL
Address
V
IH
V
IL
S-CE
1
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
S-WE
t
WC
S-UB
S-LB
V
IH
V
IL
S-OE
t
CW
t
WR
t
AS
t
WC
t
CW
t
WR
t
AS
t
AS
t
DW
t
DH
t
DW
t
DH
t
CP
t
CP
D
IN
ADDRESS STABLE
ADDRESS STABLE
VALID
INPUT
VALID
INPUT
High - Z
High - Z
Notes:
1. During address transition, at least one of S-CE
1
, S-WE or S-LB, S-UB pins should be inactivated.
2. Do not input data to the DQ pins while they are in the output state.
3. Inwrite cycle, S-CE
2
and S-OE should be fixed to high level.
4. Write operation is done during the overlap time of a low level S-CE
1
, S-WE, S-LB and/or S-UB.
sharp
L R S 1 8 2 8
42
Write Cycle Timing Chart 2 (S-WE Controlled)
V
IH
V
IL
Address
V
IH
V
IL
S-CE
1
V
IH
V
IL
V
IH
V
IL
S-WE
t
WC
S-UB
S-LB
V
IH
V
IL
S-OE
t
CW
t
OES
t
OEH
t
CW
t
CHAH
t
BHAH
t
OHAH
t
ASO
t
BHAH
t
WP
t
AS
t
WC
t
WP
t
AS
t
CP
t
CP
t
WHP
ADDRESS STABLE
ADDRESS STABLE
t
CHAH
t
WR
t
WR
Notes:
1. During address transition,at least one of S-CE
1
,S-WE or S-LB,S-UB pins should be inactivated.
2. Do not input data to the DQ pins while they are in the output state.
3. In write cycle,S-CE
2
and S-OE should be fixed to high level.
4. Write operation is done during the overlap time of a low level S-CE
1
,S-WE,S-LB and/or S-UB.
V
IH
V
IL
t
DW
t
DH
t
DW
t
DH
D
IN
High - Z
High - Z
VALID INPUT
VALID INPUT
V
OH
V
OL
t
WHZ
t
OW
D
OUT
High - Z
sharp
L R S 1 8 2 8
43
Write Cycle Timing Chart 3 (S-WE Controlled)
V
IH
V
IL
Address
V
IH
V
IL
S-CE
1
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
S-WE
t
WC
S-UB
S-LB
t
AW
t
AW
t
WP
t
WR
t
AS
t
WC
t
WP
t
WR
t
AS
t
DW
t
DH
t
DW
t
DH
t
WHP
D
IN
ADDRESS STABLE
ADDRESS STABLE
V
IH
V
IL
S-OE
High - Z
High - Z
t
OES
t
OEH
t
OHAH
t
ASO
t
BHAH
t
BHAH
VALID INPUT
VALID INPUT
V
OH
V
OL
t
WHZ
t
OW
D
OUT
High - Z
Notes:
1. During address transition, at least one of S-CE
1
, S-WE or S-LB, S-UB pins should be inactivated.
2. Do not input data to the DQ pins while they are in the output state.
3. Inwrite cycle, S-CE
2
and S-OE should be fixed to high level.
4. Write operation is done during the overlap time of a low level S-CE
1
, S-WE, S-LB and/or S-UB.
sharp
L R S 1 8 2 8
44
Write Cycle Timing Chart 4 (S-LB / S-UB Controlled)
V
IH
V
IL
Address
V
IH
V
IL
S-CE
1
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
S-WE
t
WC
S-UB
S-LB
t
BW
t
WR
t
AS
t
WC
t
BW
t
WR
t
AS
t
DW
t
DH
t
DW
t
DH
t
BP
t
BP
D
IN
ADDRESS STABLE
ADDRESS STABLE
VALID
INPUT
VALID
INPUT
High - Z
High - Z
V
IH
V
IL
S-OE
t
OES
t
OEH
t
OHAH
t
ASO
Notes:
1. During address transition, at least one of S-CE
1
, S-WE or S-LB, S-UB pins should be inactivated.
2. Do not input data to the DQ pins while they are in the output state.
3. Inwrite cycle, S-CE
2
and S-OE should be fixed to high level.
4. Write operation is done during the overlap time of a low level S-CE
1
, S-WE, S-LB and/or S-UB.
sharp
L R S 1 8 2 8
45
Write Cycle Timing Chart 5 (S-LB / S-UB Independent Controlled)
V
IH
V
IL
Address
V
IH
V
IL
S-CE
1
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
S-UB
t
WC
V
IH
V
IL
V
IH
V
IL
S-LB
S-WE
t
BW
t
WR
t
AS
t
WC
t
BW
t
WR
t
AS
t
BP
t
DW
t
DH
t
DW
t
DH
D
IN
(DQ
0
to DQ
7
)
D
IN
(DQ
8
to DQ
15
)
ADDRESS STABLE
ADDRESS STABLE
VALID
INPUT
VALID
INPUT
High - Z
High - Z
V
IH
V
IL
S-OE
t
OES
t
OEH
t
OHAH
t
ASO
Notes:
1. Duringaddress transition, at least one of S-CE
1
, S-WE or S-LB, S-UB pins should be inactivated.
2. Do not input data to the DQ pins while they are in the output state.
3. In write cycle, S-CE
2
and S-OE should be fixed to high level.
4. Write operation is done duringthe overlap time of a low level S-CE
1
, S-WE, S-LB and/or S-UB.
sharp
L R S 1 8 2 8
46
Mode Register Setting Timing Chart
V
IH
V
IL
Address
V
IH
V
IL
S-CE
1
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
S-OE
t
RC
S-UB
S-LB
S-WE
Mode Register Setting
t
RC
t
WC
t
WC
t
WP
t
WR
t
WP
t
WR
t
DW
t
DH
D
IN
1FFFFFH
1FFFFFH
xxxxH
xxxxH
1FFFFFH
1FFFFFH
t
DW
t
DH
sharp
L R S 1 8 2 8
47
Mode Register Setting Flow Chart
Start
No
No
No
No
No
No
Address = 1FFFFFH
Read with toggled the S-CE
1
, S-OE
Address = 1FFFFFH
Read with toggled the S-CE
1
, S-OE
Address = 1FFFFFH
Write
Data = 00H?
Fail
Data = 07H?
Address = 1FFFFFH
Write
Mode register setting exit
End
sharp
L R S 1 8 2 8
48
Sleep Mode Entry / Exit Timing Chart
V
IH
V
IL
S-CE
1
V
IH
V
IL
S-CE
2
t
CHML
t
MHCL
Sleep Mode
Standby Mode
sharp
L R S 1 8 2 8
49
14. Notes
This product is a stacked CSP package that a 64M (x16) bit Flash Memory, a 64M (x16) bit Flash Memory and a 32M (x16) bit
Smartcombo RAM are assembled into.
- Supply Power
Maximum difference (between F-V
CC
and S-V
CC
) of the voltage is less than 0.3V.
- Power Supply and Chip Enable of Flash Memory and Smartcombo RAM
Two or more chips among Flash memory (F
1
, F
2
) and Smartcombo RAM should not be active simultaneously.
If the two memories are active together, possibly they may not operate normally by interference noises or data collision
on DQ bus.
Both F-V
CC
and S-V
CC
are needed to be applied by the recommended supply voltage at the same time except
Smartcombo RAM standby mode.
- Power Up Sequence
When turning on Flash memory power supply, keep F-RST low. After F-V
CC
reaches over 2.7V, keep F-RST low for
more than 100 nsec.
- Device Decoupling
This is a 3 chips stacked CSP package. When one of the chips is active, others are in standby mode. Therefor, these
power supplies should be designed very carefully. A careful decoupling of power supplies is necessary between
Smartcombo RAM and Flash Memory. Note peak current caused by transition of control signals (F
1,2
-CE, S-CE
1
,
S-CE
2
).
sharp
L R S 1 8 2 8
50
15. Flash Memory Data Protection
Noises having a level exceeding the limit specified in the specification may be generated under specific operating conditions on
some systems. Such noises, when induced onto F-WE signal or power supply, may be interpreted as false commands and causes
undesired memory updating. To protect the data stored in the flash memory against unwanted writing, systems operating with the
flash memory should have the following write protect designs, as appropriate:
The below describes data protection method.
1. Protection of data in each block
ny locked block by setting its block lock bit is protected against the data alternation. When F-WP is low, any locked-down
block by setting its block lock-down bit is protected from lock status changes.
By using this function, areas can be defined, for example, program area (locked blocks), and data area (unlocked blocks).
For detailed block locking scheme, see Chapter 5.Command Definitions for Flash Memory.
2. Protection of data with F-V
PP
control
When the level of F-V
PP
is lower than V
PPLK
(F-V
PP
lockout voltage), write functions to all blocks are disabled. All
blocks are locked and the data in the blocks are completely protected.
3. Protection of data with F-RST
Especially during power transitions such as power-up and power-down, the flash memory enters reset mode by bringing
F-RST to low, which inhibits write operation to all blocks.
For detailed description on F-RST control, see Chapter 12.6 AC Electrical Characteristics for Flash Memory, Reset
Operations.
Protection against noises on F-WE signal
To prevent the recognition of false commands as write commands, system designer should consider the method for
reducing noises on F-WE signal.
sharp
L R S 1 8 2 8
51
16. Design Considerations
1. Power Supply Decoupling
To avoid a bad effect to the system by flash memory and Smartcombo RAM power switching characteristics, each
device should have a 0.1 F ceramic capacitor connected between F-V
CC
and GND, between F-V
PP
and GND and
between S-V
CC
and GND.
Low inductance capacitors should be placed as close as possible to package leads.
2. F-V
PP
Trace on Printed Circuit Boards
Updating the memory contents of flash memories that reside in the target system requires that the printed circuit board
designer pay attention to the F-V
PP
Power Supply trace. Use similar trace widths and layout considerations given to the
F-V
CC
power bus.
3. The Inhibition of Overwrite Operation
Please do not execute reprograming "0" for the bit which has already been programed "0". Overwrite operation may
generate unerasable bit.
In case of reprograming "0" to the data which has been programed "1".
Program "0" for the bit in which you want to change data from "1" to "0".
Program "1" for the bit which has already been programed "0".
For example, changing data from "1011110110111101" to "1010110110111100"
requires "1110111111111110" programing.
4. Power Supply
Block erase, full chip erase, (page buffer) program with an invalid F-V
PP
(See Chapter 11. DC Electrical
Characteristics) produce spurious results and should not be attempted.
Device operations at invalid F-V
CC
voltage (See Chapter 11. DC Electrical Characteristics) produce spurious results
and should not be attempted.
17. Related Document Information
(1)
Note:
1. International customers should contact their local SHARP or distribution sales offices.
Document No.
Document Name
FUM00701
LH28F320BF, LH28F640BF, LH28F128BF Series Appendix
sharp
Rev. 1.10
i
A-1 RECOMMENDED OPERATING CONDITIONS
A-1.1 At Device Power-Up
AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up.
If the timing in the figure is ignored, the device may not operate correctly.
Figure A-1. AC Timing at Device Power-Up
For the AC specifications t
VR
, t
R
, t
F
in the figure, refer to the next page. See the "AC Electrical Characteristics for Flash
Memory" described in specifications for the supply voltage range, the operating temperature and the AC specifications not
shown in the next page.
t
VPH
GND
V
CC
(min)
V
IL
V
IH
t
PHQV
GND
V
CCWH1/2
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
OH
V
OL
High-Z
Valid
Output
t
VR
t
F
t
ELQV
t
F
t
GLQV
Valid
t
R
or
t
F
Address
V
IL
V
IH
t
AVQV
t
R
or
t
F
t
R
t
R
*1 To prevent the unwanted writes, system designers should consider the design, which applies F-V
CCW
(F-V
PP
)
to 0V during read operations and V
CCWH1/2
(V
PPH1/2
) during write or erase operations.
See the application note AP-007-SW-Efor details.
(V
PPH1/2
)
F-V
CC
F-RP
(P)
F-V
CCW
*1
(V)
F-CE
(E)
F-WE
(W)
F-OE
(G)
F-WP
(S)
(D/Q)
DATA
(A)
ADDRESS
(F-V
PP
)
(F-RST)
(F-BE)
sharp
Rev. 1.10
ii
A-1.1.1 Rise and Fall Time
NOTES:
1. Sampled, not 100% tested.
2. This specification is applied for not only the device power-up but also the normal operations.
Symbol
Parameter
Notes
Min.
Max.
Unit
t
VR
F-V
CC
Rise Time
1
0.5
30000
s/V
t
R
Input Signal Rise Time
1, 2
1
s/V
t
F
Input Signal Fall Time
1, 2
1
s/V
sharp
Rev. 1.10
iii
A-1.2 Glitch Noises
Do not input the glitch noises which are below V
IH
(Min.) or above V
IL
(Max.) on address, data, reset, and control signals,
as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a).
Figure A-2. Waveform for Glitch Noises
See the "DC Electrical Characteristics" described in specifications for V
IH
(Min.) and V
IL
(Max.).
(a) Acceptable Glitch Noises
Input Signal
V
IH
(Min.)
Input Signal
V
IH
(Min.)
Input Signal
V
IL
(Max.)
Input Signal
V
IL
(Max.)
(b)
NOT
Acceptable Glitch Noises
sharp
Rev. 1.10
iv
A-2 RELATED DOCUMENT INFORMATION
(1)
NOTE:
1. International customers should contact their local SHARP or distribution sales office.
Document No.
Document Name
AP-001-SD-E
Flash Memory Family Software Drivers
AP-006-PT-E
Data Protection Method of SHARP Flash Memory
AP-007-SW-E
RP#, V
PP
Electric Potential Switching Circuit
sharp
i
B-1 POWER UP SEQUENCE OF Smartcombo RAM
When turning on Smartcombo RAM power supply, the following sequence is needed.
B-1.1 Sequence of Smartcombo RAM Power Supply
(1) Supply power.
(2) Keep S-CE
2
low longer than or equal to 50s. (See NOTES *1)
(3) Keep S-CE
1
and S-CE
2
high longer than or equal to 200s. (See NOTES *2 )
(4) End of Initialization.
By executing above (1) to (4), the initialization of chip inside and the power occurred inside become stable.
<Example of the actual connection>
NOTES:
*1) Connect System Reset signal to S-CE
2
and hold S-CE
2
low longer than or equal to 50s.
*2) By adding "200s Wait Routine" (S-CE
1
and S-CE
2
high) in the software, delay the first access to Smartcombo RAM
longer than or equal to 200s.
When giving compatibility with the other type of Smartcombo RAM, 200s must be changed to 300s.
V
CC
S-CE
2
S-CE
1
F-RST
System Reset
from CPU
Combination
Memory
Add "200s
(*2)
wait routine" by software
before the first Smartcombo RAM access.
Need 10ns (Min.)
1st Access to Smartcombo RAM
V
CC
(Min.)
V
IH
V
IH
V
IH
V
IL
S-CE
2
S-CE
1
V
CC
(*1)
(*2)
Need 50s (Min.)
Need 200s (Min.)
sharp
SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
Suggested applications (if any) are for standard use; See Important Restrictions for limitations on special applications. See Limited
Warranty for SHARP's product warranty. The Limited Warranty is in lieu, and exclusive of, all other warranties, express or implied.
ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND
FITNESS FOR A PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED. In no event will SHARP be liable, or in any way responsible,
for any incidental or consequential economic or property damage.
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