www.docs.chipfind.ru
In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in
catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.
1
DESCRIPTION
The LZ2416J is a 1/4-type (4.5 mm) solid-state
image sensor that consists of PN photo-diodes and
CCDs (charge-coupled devices) driven by dual-
power-supply . With approximately 270 000 pixels
(542 horizontal x 492 vertical), the sensor provides a
stable high-resolution B/W normal or mirror image.
FEATURES
Number of effective pixels : 512 (H) x 492 (V)
Number of optical black pixels
Horizontal : 2 front and 28 rear
Pixel pitch : 7.2 m (H) x 5.6 m (V)
Low fixed-pattern noise and lag
No burn-in and no image distortion
Blooming suppression structure
Built-in output amplifier
Built-in pulse mix circuit
Variable electronic shutter (1/60 to 1/10 000 s)
Normal or mirror image output available from
common output pin
Compatible with EIA standard
Package :
14-pin half-pitch WDIP [Plastic]
(WDIP014-P-0400A)
Row space : 10.16 mm
PIN CONNECTIONS
PRECAUTIONS
The exit pupil position of lens should be more
than 20 mm from the top surface of the CCD.
Refer to "PRECAUTIONS FOR CCD AREA
SENSORS" for details.
LZ2416J
Dual-power-supply (5 V/12 V) Operation
1/4-type B/W CCD Area Sensor with 270 k Pixels
LZ2416J
1
RS
2
GND
3
OS
4
OD
5
H2B
6
H2
7
H1B
14
13
12
11
10
9
8
OFD
TG
V2
V1
V4
V3
H1
14-PIN HALF-PITCH WDIP
TOP VIEW
(WDIP014-P-0400A)
LZ2416J
2
PIN DESCRIPTION
SYMBOL
PIN NAME
OD
Output transistor drain
OS
Output signals
RS
Reset transistor clock
V1
,
V2
,
V3
,
V4
Vertical shift register clock
H1
,
H2
,
H1B
,
H2B
Horizontal shift register clock
OFD
Overflow drain
GND
Ground
Transfer gate clock
TG
1
NOTE
NOTE :
1.
V1
-
V4
: Input the clock through a 0.1 F capacitor.
ABSOLUTE MAXIMUM RATINGS
(T
A
= +25 C)
PARAMETER
SYMBOL
RATING
UNIT
Output transistor drain voltage
V
OD
0 to +15
V
Overflow drain voltage
V
RS
0.3 to +15
V
Reset gate clock voltage
V
V
0 to +7.5
V
Vertical shift register clock voltage
V
H
0.3 to +7.5
V
Horizontal shift register clock voltage
V
TG
0.3 to +15
V
Transfer gate clock voltage
V
OFD
0 to +30
V
Storage temperature
T
STG
40 to +85
C
Ambient operating temperature
T
OPR
20 to +70
C
LZ2416J
3
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTE
Ambient operating temperature
T
OPR
25.0
C
Output transistor drain voltage
V
OD
12.0
12.5
13.0
V
Ground
GND
0.0
V
Horizontal shift
register clock
LOW level
V
H1L
, V
H2L
V
H1BL
, V
H2BL
0.05
0.0
0.05
V
HIGH level
V
H1H
, V
H2H
V
H1BH
, V
H2BH
4.7
5.0
5.5
V
Reset gate clock
LOW level
V
RSL
0.0
Vertical shift register clock frequency
f
V1
, f
V2
f
V3
, f
V4
15.73
kHz
Horizontal shift register clock frequency
f
H1
, f
H2
f
H1B
, f
H2B
9.53
MHz
Reset gate clock frequency
f
RS
9.53
MHz
NOTES :
1. When DC voltage is applied, shutter speed is 1/60-second.
2. When pulse is applied, shutter speed is less than 1/60-second.
3.
* To apply power, first connect GND and then turn on V
OD
and then turn on other powers and pulses. Do not connect the
device to or disconnect it from the plug socket while power is being applied.
1
V
12.0
2.7
V
OFD
Overflow drain
voltage
V
0.05
0.0
0.05
V
TGL
Transfer gate
clock
LOW level
HIGH level
V
TGH
12.0
12.5
13.0
V
p-p level
Vertical shift
register clock
V
V1
, V
V2
V
V3
, V
V4
4.7
5.0
5.5
V
When DC is applied
V
OD
9.0
V
3
ns
18.0
13.0
8.0
tw
1
, tw
2
Horizontal shift register clock phase
H1
,
H2
H1B
,
H2B
: Normal image output mode
H1B
,
H2B
: Mirror image output mode
tw
1
tw
2
When pulse is applied p-p level
V
OFD
12.0
12.5
13.0
V
2
V
9.5
V
OD
4.5
V
RSH
HIGH level
LZ2416J
4
CHARACTERISTICS
(Drive method : Field accumulation)
(T
A
= +25 C, Operating conditions : The typical values specified in "RECOMMENDED OPERATING CONDITIONS".
Color temperature of light source : 3 200 K, IR cut-off filter (CM-500, 1 mmt) is used.)
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTE
Standard output voltage
V
O
150
mV
2
Photo response non-uniformity
PRNU
15
%
3
Saturation output voltage
V
SAT
500
mV
4
Dark output voltage
V
DARK
0.5
mV
1, 5
Dark signal non-uniformity
DSNU
0.5
mV
1, 6
Sensitivity
R
450
mV
7
Smear ratio
SMR
84
dB
8
Image lag
AI
1.0
%
9
Blooming suppression ratio
ABL
1 000
10
Output transistor drain current
I
OD
4.0
8.0
mA
Output impedance
R
O
400
$
NOTES :
V
OFD
should be adjusted to the minimum voltage such
that ABL satisfy the specification, or to the value
displayed on the device.
1. T
A
= +60 C
2. The average output voltage under uniform illumination.
The standard exposure conditions are defined as when
Vo is 150 mV.
3. The image area is divided into 10 x 10 segments under
the standard exposure conditions. Each segment's
voltage is the average output voltage of all pixels within
the segment. PRNU is defined by (Vmax Vmin)/Vo,
where Vmax and Vmin are the maximum and minimum
values of each segment's voltage respectively.
4. The image area is divided into 10 x 10 segments. Each
segment's voltage is the average output voltage of all
pixels within the segment. V
SAT
is the minimum
segment's voltage under 10 times exposure of the
standard exposure conditions.
5. The average output voltage under non-exposure
conditions.
6. The image area is divided into 10 x 10 segments under
non-exposure conditions. DSNU is defined by (Vdmax
Vdmin), where Vdmax and Vdmin are the maximum and
minimum values of each segment's voltage respectively.
7. The average output voltage when a 1 000 lux light
source with a 90% reflector is imaged by a lens of F4,
f50 mm.
8. The sensor is exposed only in the central area of V/10
square with a lens at F4, where V is the vertical image
size. SMR is defined by the ratio of the output voltage
detected during the vertical blanking period to the
maximum output voltage in the V/10 square.
9. The sensor is exposed at the exposure level
corresponding to the standard conditions. AI is defined
by the ratio of the output voltage measured at the 1st
field during the non-exposure period to the standard
output voltage.
10. The sensor is exposed only in the central area of V/10
square, where V is the vertical image size. ABL is
defined by the ratio of the exposure at the standard
conditions to the exposure at a point where blooming is
observed.
LZ2416J
5
PIXEL STRUCTURE
TIMING CHART
512 (H) x 492 (V)
1 pin
OPTICAL BLACK
(2 PIXELS)
OPTICAL BLACK
(28 PIXELS)
484
+
485
486
+
487
488
+
489
492
490
+
491
1
+
2
3
+
4
5
+
6
7
+
8
9
+
10
11
+
12
OS
TG
V4
V3
V2
V1
VD
HD
(ODD FIELD)
VERTICAL TRANSFER TIMING <NORMAL OUTPUT>
483
+
484
485
+
486
487
+
488
489
+
490
491
+
492
2
+
3
1
4
+
5
6
+
7
8
+
9
10
+
11
OS
TG
V4
V3
V2
V1
VD
HD
(EVEN FIELD)
525 1
10
17
19
263
272
279
282
LZ2416J
6
OS
RS
H2
H1
HD
OB (28)
OB (2)
OFD
V4
V3
V2
V1
HORIZONTAL TRANSFER TIMING <NORMAL OUTPUT>
606, 1
84.5
60
24
24
49
39
54
29
34
62
72
PRE SCAN (4)
... 512
59
64
V4
TG
V3
V2
V1
HD
(ODD FIELD)
(EVEN FIELD)
READOUT TIMING <NORMAL OUTPUT>
V4
TG
V3
V2
V1
HD
1
24
60
29
39
54
64
34
59
49
60
1
29
39
24
60
54
64
34
59
49
60
338
242
25.36 s (242 bits)
25.36 s (242 bits)
63.5 s (606 bits)
63.5 s (606 bits)
338
242
10.06 s (96 bits)
606, 1
606, 1
10.06 s (96 bits)
OUTPUT (512) 1
LZ2416J
7
482
+
483
484
+
485
486
+
487
490
+
491
492
488
+
489
1
+
2
3
+
4
5
+
6
7
+
8
9
+
10
OS
TG
V4
V3
V2
V1
VD
HD
(ODD FIELD)
VERTICAL TRANSFER TIMING <MIRROR OUTPUT>
481
+
482
483
+
484
485
+
486
487
+
488
489
+
490
491
+
492
2
+
3
1
4
+
5
6
+
7
8
+
9
OS
TG
V4
V3
V2
V1
VD
HD
(EVEN FIELD)
525 1
10
17
19
263
272
279
282
OS
RS
H2
H1
HD
OUTPUT (512) 512
OFD
V4
V3
V2
V1
HORIZONTAL TRANSFER TIMING <MIRROR OUTPUT>
606, 1
58.5
60
4
4
29
19
34
9
14
42
52
PRE SCAN (4)
1
39
OB (2)
OB (28)
44
LZ2416J
8
V4
TG
V3
V2
V1
HD
(ODD FIELD)
(EVEN FIELD)
READOUT TIMING <MIRROR OUTPUT>
V4
TG
V3
V2
V1
HD
1
4
60
29
39
34
44
14
19
9
60
1
9
19
4
60
34
44
14
39
29
60
318
222
23.27 s (222 bits)
23.27 s (222 bits)
63.5 s (606 bits)
318
222
10.06 s (96 bits)
606, 1
606, 1
10.06 s (96 bits)
63.5 s (606 bits)
LZ2416J
9
SYSTEM CONFIGURATION EXAMPLE
H1
V1
V4
RS
GND
V3
OFD
H1B
H2
H2B
OD
OS
TG
V2
CCD
OUT
2SC4627
2SC4716
1 k$
10 $
1 M$
68 $
1000 pF
390 $
20 k$
22 k$
2.2 k$
0.1 F
0.1 F
0.1 F
0.1 F
0.1 F
8
9
10
11
12
13
(*1)
14
7
6
5
4
3
2
1
LZ2416J
V
OD
RS
V
CC
OFD
TGX
H2
H1B
H1
H2B
V4
V1
V3
V2
(*1)
V1
-
V4
: Input the clock through a
0.1 F capacitor.
Example of drive circuit with LR38580 driver IC.
PACKAGES FOR CCD AND CMOS DEVICES
10
( : Lid's size)
10.00
0.10
0.50
0.50
0.50
0.50
10.00
0.10
0.25
0.10
9.00
0.10
()
10.16
5.00
0.075
5.00
0.075
CCD
1
7
8
14
0.03
0.03
1.39
0.05
1.96
0.05
9.00
0.10
()
Package
Glass Lid
CCD
Rotation error of die : = 1.0
MAX.
Center of effective imaging area
and center of package
Cross section A-A'
3.50
0.30
1.27
0.25
2.55
0.10
0.30
TYP.
0.46
TYP.
P-1.27
TYP.
5.02
MAX.
3.35
0.10
A'
A
0.80
0.05
()
M
0.25
+0.5
0
PACKAGE
(Unit : mm)
14 WDIP (WDIP014-P-0400A)
PRECAUTIONS FOR CCD AREA SENSORS
1. Package Breakage
In order to prevent the package from being broken,
observe the following instructions :
1) The CCD is a precise optical component and
the package material is ceramic or plastic.
Therefore,
Take care not to drop the device when
mounting, handling, or transporting.
Avoid giving a shock to the package.
Especially when leads are fixed to the socket
or the circuit board, small shock could break
the package more easily than when the
package isn't fixed.
2) When applying force for mounting the device or
any other purposes, fix the leads between a
joint and a stand-off, so that no stress will be
given to the jointed part of the lead. In addition,
when applying force, do it at a point below the
stand-off part.
(In the case of ceramic packages)
The leads of the package are fixed with low
melting point glass, so stress added to a
lead could cause a crack in the low melting
point glass in the jointed part of the lead.
(In the case of plastic packages)
The leads of the package are fixed with
package body (plastic), so stress added to a
lead could cause a crack in the package
body (plastic) in the jointed part of the lead.
3) When mounting the package on the housing,
be sure that the package is not bent.
If a bent package is forced into place
between a hard plate or the like, the pack-
age may be broken.
4) If any damage or breakage occurs on the sur-
face of the glass cap, its characteristics could
deteriorate.
Therefore,
Do not hit the glass cap.
Do not give a shock large enough to cause
distortion.
Do not scrub or scratch the glass surface.
Even a soft cloth or applicator, if dry, could
cause dust to scratch the glass.
2. Electrostatic Damage
As compared with general MOS-LSI, CCD has
lower ESD. Therefore, take the following anti-static
measures when handling the CCD :
1) Always discharge static electricity by grounding
the human body and the instrument to be used.
To ground the human body, provide resistance
of about 1 M$ between the human body and
the ground to be on the safe side.
2) When directly handling the device with the
fingers, hold the part without leads and do not
touch any lead.
Glass cap
Package
Lead
Fixed
Stand-off
Fixed
Lead
Stand-off
Low melting point glass
11
PRECAUTIONS FOR CCD AREA SENSORS
3) To avoid generating static electricity,
a. do not scrub the glass surface with cloth or
plastic.
b. do not attach any tape or labels.
c. do not clean the glass surface with dust-
cleaning tape.
4) When storing or transporting the device, put it in
a container of conductive material.
3. Dust and Contamination
Dust or contamination on the glass surface could
deteriorate the output characteristics or cause a
scar. In order to minimize dust or contamination on
the glass surface, take the following precautions :
1) Handle the CCD in a clean environment such
as a cleaned booth. (The cleanliness level
should be, if possible, class 1 000 at least.)
2) Do not touch the glass surface with the fingers.
If dust or contamination gets on the glass
surface, the following cleaning method is
recommended :
Dust from static electricity should be blown
off with an ionized air blower. For anti-
electrostatic measures, however, ground all
the leads on the device before blowing off
the dust.
The contamination on the glass surface
should be
PDF 
ZIP