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Электронный компонент: LZ87010

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P
RELIMINARY
P
RODUCT
I
NFORMATION
APPLICATIONS:
Motor Control
Test and Measurement
Instrumentation
SHARP's New Line
of MCUs and
System-On-Chips
LZ87010 8-bit Flash
Microcontroller
FEATURES
8-Bit, 8051 Enhanced CPU Core:
Two-clock Machine Cycle
(6 Performance Boost over Standard 8051 CPU Core)
Two-wire Debug Interface with Breakpoint and Trace
20 MHz - 40 MHz Operating Frequency at 3.3 V
Equivalent to 240 MHz (MAX.) Standard 8051
Flexible Internal Clocking Architecture
64KB Built-In Flash Memory
Flash Memory In-circuit Serially Programmable
External Program Memory Expansion Capability
Supports Reads and Writes
4KB Internal MOVX SRAM
256 Bytes Scratchpad RAM
Six 16-bit Multifunction Timer/Counters
Two General Purpose
Two with Capture/Compare/PWM Capa bility
Two with Compare/PWM Capability
Serial Interfaces
Two UART/SIO
Baud Rate Converter for UART 1
One I
2
C
A/D Converter
Eight Channel, 12-Bit Resolution
D/A Converter
Two Channel, 8-bit Resolution
Waveform Generator Capability
Sixteen High Current Output Pins
12 mA (MAX.) Each
Up to 56 GPIO
Watchdog Timer
Low Power Modes: Active, Power Down, Idle
3.3 V Power Supply
-40C to +85C Operating Temperature
100-Pin LQFP Package
DESCRIPTION
The LZ87010 is an 8-bit, 8051-based microcontrol ler that adds
64KB of integrated Flash memory, two UART/SIOs, I
2
C, and several
mul tifunction timers. It also incorporates an 8-channel 12-bit A/D
converter, two separate 8-bit D/A converters, and low power
modes of operation.
The 8051 Enhanced Core provides a performance boost, six times
that of a standard 8051 core operating at the same frequency and
has built-in 2-wire debug support. It is software-compatible with
8031/8051 series parts.
The LZ87010 operates from 20 MHz - 40 MHz over the industrial
temperature range of -40C to +85C.
SHARP's LZ87010 design provides low power, exceptional
performance, good fl exibility, and great value in an 8-bit processor.
SYSTEM APPLICATION EXAMPLE
I
2
C
EEPROM
CODE
EXPANSION
UART
A/D
UART
LZ87010
RS-422
TRANSCEIVER
MOTOR
DRIVER
MOTOR
REMOTE
SENSOR
ARRAY
SENSOR
ARRAY
A/D
GPIO D/A
LZ87010-2
SMA01011E
Copyright 2001, SHARP Microelectronics of the Americas. All rights reserved. All tradenames are the registered property of their respective owners.
P
RELIMINARY
P
RODUCT
I
NFORMATION
Product Information: 1-800-642-0261
World Wide Website: http://www.sharpsma.com
Specifi cations are subject to change without notice. Suggested applications (if any) are for standard use; See Important Restrictions for limitations on special applications.
See Limited Warranty for SHARP's product warranty. The Limited Warranty is in lieu, and exclusive of, all other warranties, express or implied. ALL EXPRESS AND IMPLIED
WARRANTIES, INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND FITNESS FOR A PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED.
In no event will SHARP be liable, or in any way responsible, for any incidental or consequential economic or property damage.
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LZ87010 BLOCK DIAGRAM
LZ87010-63
PORT 0,
INTERRUPTS
PORT 1 [7:6],
EXTERNAL
MEMORY R/W
PORT 1 [5:0],
TIMER 3
PORT 5,
EXTERNAL
MEMORY DATA
PORT 8,
EXTERNAL
MEMORY
ADDRESS
PORT 9
PORT 6 [7:4],
TIMER 5
PORT 6 [3:0],
TIMER 4
PORT 2,
EXTERNAL
MEMORY
ADDRESS
PROGRAM
MEMORY
64KB FLASH
8051-
COMPATIBLE
CPU
DEBUG
INTERFACE
MOVX
DATA RAM
4,096 BYTES
INTERNAL
DATA RAM
256 BYTES
DAC1
WAVETABLE
128 BYTES
CLOCKING
RESET, WATCHDOG
TIMER
DIGITAL 3.3 V POWER
DIGITAL 2.5 V POWER
ANALOG 3.3 V POWER
REGULATOR ENABLE
DIGITAL GROUND
ANALOG GROUND
DAC1
ADC
12 BITS
PORT 3 [5:4],
WAVEFORM
GENERATOR
CLOCK
PORT 3 [7:6],
I
2
C
PORT 3 [3:2],
UART1
PORT 3 [1:0],
UART0
PORT 7 [7:6],
TIMERS 1 and 0
PORT 7 [5:0],
TIMER 2
P3[3], RXD1
P3[2], TXD1
P3[5], WFGIN0
P3[4], WFGIN1
P3[7], SDA
P3[6], SCL
P3[1], TXD0
P3[0], RXD0
P0[7:0], INT[7:0]
P1[7], nPSEN
P1[6], nPSWR
P1[5], CTCMP3B
P1[4], CTCMP3A
P1[3], CTCAP3B
P1[2], CTCAP3A
P1[1]
P1[0], CTIN3
P2[7:0], XMA[15:8]
P6[7], CTCMP5B
P6[6], CTCMP5A
P6[5]
P6[4], CTIN5
P6[3], CTCMP4B
P6[2], CTCMP4A
P6[1]
P6[0], CTIN4
XTAL2
XTAL1
XTAL_SUB2
XTAL_SUB1
SDI_CLK
SDI_DATA
VDD
VDD_CORE
VDDA
ENDC
VSS
VSSA
RESET
P7[7], CTIN1
P7[6], CTIN0
P7[5], CTCMP2B
P7[4], CTCMP2A
P7[3], CTCAP2B
P7[2], CTCAP2A
P7[1]
P7[0], CTIN2
DA0
DA1
AN[7:0]
DAVREF
ADVREF
P5[7:0], XMD[7:0]
P8[7:0], XMA[7:0]
P9[7:0]
DAC0
WAVETABLE
128 BYTES
DAC0