Semiconductor Group
1
09.94
q
High Performance 16-bit CPU with 4-Stage Pipeline
q
100 ns Instruction Cycle Time at 20 MHz CPU Clock
q
500 ns Multiplication (16
16 bit), 1
s Division (32 / 16 bit)
q
Enhanced Boolean Bit Manipulation Facilities
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Register-Based Design with Multiple Variable Register Banks
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Single-Cycle Context Switching Support
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Up to 256 KBytes Linear Address Space for Code and Data
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1 KByte On-Chip RAM
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32 KBytes On-Chip ROM (SAB 83C166 only)
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Programmable External Bus Characteristics for Different Address Ranges
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8-Bit or 16-Bit External Data Bus
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Multiplexed or Demultiplexed External Address/Data Buses
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Hold and Hold-Acknowledge Bus Arbitration Support
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512 Bytes On-Chip Special Function Register Area
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Idle and Power Down Modes
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8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event
Controller (PEC)
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16-Priority-Level Interrupt System
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10-Channel 10-bit A/D Converter with 9.7
s Conversion Time
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16-Channel Capture/Compare Unit
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Two Multi-Functional General Purpose Timer Units with 5 Timers
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Two Serial Channels (USARTs)
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Programmable Watchdog Timer
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Up to 76 General Purpose I/O Lines
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Supported by a Wealth of Development Tools like C-Compilers, Macro-Assembler Packages,
Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers,
Programming Boards
q
On-Chip Bootstrap Loader
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100-Pin Plastic MQFP Package (EIAJ)
C16x-Family of
High-Performance CMOS 16-Bit Microcontrollers
Preliminary
SAB 80C166/83C166 16-Bit Microcontroller
SAB 80C166/83C166
SAB 80C166/83C166
Semiconductor Group
2
Introduction
The SAB 80C166 is the first representative of the Siemens SAB 80C166 family of full featured
single-chip CMOS microcontrollers. It combines high CPU performance (up to 10 million
instructions per second) with high peripheral functionality and enhanced IO-capabilities.
Figure 1
Logic Symbol
Ordering Information
Note: The ordering codes (Q67120-D...) for the Mask-ROM versions are defined for each product
after verification of the respective ROM code.
Type
Ordering Code
Package
Function
SAB 83C166-5M
Q67121-D...
P-MQFP-100-2 16-bit microcontroller, 0 C to +70 C,
1 KByte RAM and 32 KByte ROM
SAB 83C166-5M-T3 Q67121-D...
P-MQFP-100-2 16-bit microcontroller, -40 C to +85 C,
1 KByte RAM and 32 KByte ROM
SAB 80C166-M
Q67121-C848
P-MQFP-100-2 16-bit microcontroller, 0 C to +70 C
1 KByte RAM
SAB 80C166-M-T3
Q67121-C900
P-MQFP-100-2 16-bit microcontroller, -40 C to +85 C
1 KByte RAM
SAB
80C166
SAB 80C166/83C166
Semiconductor Group
4
Pin Definitions and Functions
Symbol
Pin
Number
Input
Output
Function
P4.0
P4.1
16-17
16
17
I/O
O
O
Port 4 is a 2-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-impedance
state.
In case of an external bus configuration, Port 4 can be used to
output the segment address lines:
P4.0
A16
Least Significant Segment Addr. Line
P4.1
A17
Most Significant Segment Addr. Line
XTAL1
XTAL2
20
19
I
O
XTAL1:
Input to the oscillator amplifier and input to the
internal clock generator
XTAL2:
Output of the oscillator amplifier circuit.
To clock the device from an external source, drive XTAL1, while
leaving XTAL2 unconnected. Minimum and maximum high/low
and rise/fall times specified in the AC Characteristics must be
observed.
BUSACT,
EBC1,
EBC0
22
23
24
I
I
I
External Bus Configuration selection inputs. These pins are
sampled during reset and select either the single chip mode or
one of the four external bus configurations:
BUSACT EBC1
EBC0
Mode/Bus Configuration
0
0
0
8-bit demultiplexed bus
0
0
1
8-bit multiplexed bus
0
1
0
16-bit multiplexed bus
0
1
1
16-bit demultiplexed bus
1
0
0
Single chip mode
1
0
1
Reserved.
1
1
0
Reserved.
1
1
1
Reserved.
ROMless versions must have pin BUSACT tied to `0'.
RSTIN
27
I
Reset Input with Schmitt-Trigger characteristics. A low level at
this pin for a specified duration while the oscillator is running
resets the SAB 80C166. An internal pullup resistor permits
power-on reset using only a capacitor connected to
V
SS
.
RSTOUT
28
O
Internal Reset Indication Output. This pin is set to a low level
when the part is executing either a hardware-, a software- or a
watchdog timer reset. RSTOUT remains low until the EINIT
(end of initialization) instruction is executed.
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