C161RI
Revision History:

1998-05-01 Preliminary

Previous Releases:

1998-01 Advance Information
1997-12 Advance Information

Page

Subjects

XTAL pin numbers (MQFP) corrected.

DDMIN

corrected, special threshold parameters added (

ILS

IHS

, HYS).

35, 37

Specification of

IDO

improved.

ADCTC value in converter timing example timing corrected.

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Edition 1998-05-01

Published by Siemens AG,
Bereich Halbleiter, Marketing-
Kommunikation, Balanstraße 73,
81541 München

Siemens AG 1998.

As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes
and circuits implemented within components or assemblies.
The information describes the type of component and shall not be considered as assured characteristics.

Terms of delivery and rights to change design reserved.
For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies
and Representatives worldwide (see address list).

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Semiconductor Group

1998-05-01

High Performance 16-bit CPU with 4-Stage Pipeline

125 ns Instruction Cycle Time at 16 MHz CPU Clock

625 ns Multiplication (16

16 bits), 1.25

s Division (32 / 16 bit)

Enhanced Boolean Bit Manipulation Facilities

Additional Instructions to Support HLL and Operating Systems

Single-Cycle Context Switching Support

Clock Generation via Prescaler or via Direct Clock Input

Up to 8 MBytes Linear Address Space for Code and Data

1 KByte On-Chip Internal RAM (IRAM)

2 KBytes On-Chip Extension RAM (XRAM)

Programmable External Bus Characteristics for Different Address Ranges

8-Bit or 16-Bit External Data Bus

Multiplexed or Demultiplexed External Address/Data Bus

5 Programmable Chip-Select Signals

1024 Bytes On-Chip Special Function Register Area

8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event
Controller (PEC)

16-Priority-Level Interrupt System, 11 External Interrupts

4-Channel 8-bit A/D Converter, conversion time down to 7.625

2 Multi-Functional General Purpose Timer Units with five 16-bit Timers

Synchronous/Asynchronous Serial Channel (USART)

High-Speed Synchronous Serial Channel

C Bus Interface (10-bit Addressing, 400 KHz) with 2 Channels (multiplexed)

Up to 76 General Purpose I/O Lines

Programmable Watchdog Timer

On-Chip Real Time Clock

Idle and Power Down Modes with Flexible Power Management

Ambient temperature range 40 to 85

Supported by a Large Range of Development Tools like C-Compilers, Macro-Assembler
Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer
Disassemblers, Programming Boards

On-Chip Bootstraploader

100-Pin MQFP / TQFP Package

This document describes the SAB-C161RI-LM, the SAB-C161RI-LF, the SAF-C161RI-LM and the
SAB-C161RI-LF.
For simplicity all versions are referred to by the term C161RI throughout this document.

C166-Family of
High-Performance CMOS 16-Bit Microcontrollers

Preliminary

C161RI 16-Bit Microcontroller

C161RI

Semiconductor Group

1998-05-01

C161RI

Introduction

The C161RI is a new derivative of the Siemens C166 Family of 16-bit single-chip CMOS
microcontrollers. It combines high CPU performance (up to 8 million instructions per second) with
high peripheral functionality and enhanced IO-capabilities. The C161RI derivative is especially
suited for cost sensitive applications.

Figure 1
Logic Symbol

Ordering Information

The ordering code for Siemens microcontrollers provides an exact reference to the required
product. This ordering code identifies:

the derivative itself, i.e. its function set

the specified temperature range

the package

the type of delivery.

For the available ordering codes for the C161RI please refer to the
"Product Information Microcontrollers", which summarizes all available microcontroller variants.

Note: The ordering codes for the Mask-ROM versions are defined for each product after

verification of the respective ROM code.

C161RI

XTAL2

XTAL1

RSTIN

NMI

RSTOUT

ALE
RD
WR/WRL

PORT0

16 bit

PORT1

16 bit

Port 2

8 bit

Port 3

15 bit

Port 4

7 bit

Port 6

8 bit

Port 5

6 bit

AREF

AGND

Semiconductor Group

1998-05-01

C161RI

Pin Configuration MQFP Package
(top view)

Figure 2

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

C161RI

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

NMI
RSTOUT
RSTIN
V

P1H.7/A15
P1H.6/A14
P1H.5/A13
P1H.4/A12
P1H.3/A11
P1H.2/A10
P1H.1/A9
P1H.0/A8
V

P1L.7/A7
P1L.6/A6
P1L.5/A5
P1L.4/A4
P1L.3/A3
P1L.2/A2
P1L.1/A1
P1L.0/A0
P0H.7/AD15
P0H.6/AD14
P0H.5/AD13
P0H.4/AD12
P0H.3/AD11
P0H.2/AD10
P0H.1/AD9

P5.2/AN2
P5.3/AN3

P5.14/T4EUD
P5.15/T2EUD

XTAL1
XTAL2

P3.0/SCL0

P3.1/SDA0

P3.2/CAPIN

P3.3/T3OUT
P3.4/T3EUD

P3.5/T4IN
P3.6/T3IN
P3.7/T2IN

P3.8/MRST
P3.9/MTSR

P3.10/TxD0

P3.11/RxD0

P3.12/BHE/WRH

P3.13/SCLK

P3.15/CLKOUT

P4.0/A16
P4.1/A17
P4.2/A18
P4.3/A19
P4.4/A20

ARE

P2.

15/

EX7I

P2.

14/

EX6I

P2.

13/

EX5I

P2.

12/

EX4I

P2.

11/

EX3I

P2.

10/

EX2I

P2.

/
EX1I

P2.

/
EX0I

P4.

ADY

ALE

P0H

.
0/

Semiconductor Group

1998-05-01

C161RI

Pin Configuration TQFP Package
(top view)

Figure 3

P5.

P2.

15/

P2.

14/

P2.

13/

P2.

12/

P2.

11/

P2.

10/

P2.

X1I

P2.

X0I

P6.

DA2

P6.

CL1

P6.

DA1

P6.

RST

I
N

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

100

C161RI

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

P1H.7/A15
P1H.6/A14
P1H.5/A13
P1H.4/A12
P1H.3/A11
P1H.2/A10
P1H.1/A9
P1H.0/A8
V

P1L.7/A7
P1L.6/A6
P1L.5/A5
P1L.4/A4
P1L.3/A3
P1L.2/A2
P1L.1/A1
P1L.0/A0
P0H.7/AD15
P0H.6/AD14
P0H.5/AD13
P0H.4/AD12
P0H.3/AD11

P5.14/T4EUD
P5.15/T2EUD

XTAL1
XTAL2

P3.0/SCL0

P3.1/SDA0

P3.2/CAPIN

P3.3/T3OUT
P3.4/T3EUD

P3.5/T4IN
P3.6/T3IN
P3.7/T2IN

P3.8/MRST
P3.9/MTSR

P3.10/TxD0

P3.11/RxD0

P3.12/BHE/WRH

P3.13/SCLK

P3.15/CLKOUT

P4.0/A16
P4.1/A17

.2/

.3/

.4/

.5/

.6/

ALE

P0L.

.
0

/
AD

.
1

/
AD

.
2

/
AD

Semiconductor Group

1998-05-01

C161RI

Pin Definitions and Functions

Symbol

Pin No.
TQFP

Pin No.
MQFP

Input
Outp

Function

P5.0
P5.3,
P5.14
P5.15

97
100,
1
2

99
2,
3
4

I
I
I
I

Port 5 is a 6-bit input-only port with Schmitt-Trigger
characteristics. The pins of Port 5 also serve as the (up to 4)
analog input channels for the A/D converter, where P5.x
equals ANx (Analog input channel x, x=0...3).
The following pins of Port 5 also serve as timer inputs:
P5.14

T4EUD

GPT1 Timer T4 Ext.Up/Down Ctrl.Input

P5.15

T2EUD

GPT1 Timer T5 Ext.Up/Down Ctrl.Input

XTAL1

XTAL2

XTAL1:

Input to the oscillator amplifier and input to the
internal clock generator

XTAL2:

Output of the oscillator amplifier circuit.

To clock the device from an external source, drive XTAL1,
while leaving XTAL2 unconnected. Minimum and maximum
high/low and rise/fall times specified in the AC
Characteristics must be observed.

P3.0
P3.13,
P3.15

7
20,
21

7
8
9
10
11
12

13
14

15
16
17
18
19

20
21

9
22,
23

9
10
11
12
13
14

15
16

17
18
19
20
21

22
23

I/O
I/O
I/O

I/O
I/O
I
O
I
I

I
I

I/O
I/O
O
I/O
O
O
I/O
O

Port 3 is a 15-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-
impedance state.
The following Port 3 pins also serve for alternate functions:
P3.0

SCL0

C Bus Clock Line 0

P3.1

SDA0

C Bus Data Line 0

P3.2

CAPIN

GPT2 Register CAPREL Capture Input

P3.3

T3OUT

GPT1 Timer T3 Toggle Latch Output

P3.4

T3EUD

GPT1 Timer T3 Ext.Up/Dwn Ctrl.Input

P3.5

T4IN

GPT1 Timer T4 Input for
Count/Gate/Reload/Capture

P3.6

T3IN

GPT1 Timer T3 Count/Gate Input

P3.7

T2IN

GPT1 Timer T2 Input for
Count/Gate/Reload/Capture

P3.8

MRST

SSC Master-Rec./Slave-Transmit I/O

P3.9

MTSR

SSC Master-Transmit/Slave-Rec. O/I

P3.10

ASC0 Clock/Data Output (Asyn./Syn.)

P3.11

ASC0 Data Input (Asyn.) or I/O (Syn.)

P3.12

BHE

Ext. Memory High Byte Enable Signal,

WRH

Ext. Memory High Byte Write Strobe

P3.13

SCLK

SSC Master Clock Outp./Slave Cl. Inp.

P3.15

CLKOUT

System Clock Output (=CPU Clock)

Note:

Pins P3.0 and P3.1 are open drain outputs only.

Semiconductor Group

1998-05-01

C161RI

P4.0
P4.6

24
30

24
...
30

26 -
32

26
...
32

I/O
I/O

O
...
O

Port 4 is a 7-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-
impedance state.
In case of an external bus configuration, Port 4 can be used
to output the segment address lines:
P4.0

A16

Least Significant Segment Addr. Line

...

P4.6

A22

Most Significant Segment Addr. Line

External Memory Read Strobe. RD is activated for every
external instruction or data read access.

WR/WRL 32

External Memory Write Strobe. In WR-mode this pin is
activated for every external data write access. In WRL-mode
this pin is activated for low byte data write accesses on a 16-
bit bus, and for every data write access on an 8-bit bus. See
WRCFG in register SYSCON for mode selection.

READY

Ready Input. When the Ready function is enabled, a high
level at this pin during an external memory access will force
the insertion of memory cycle time waitstates until the pin
returns to a low level.

ALE

Address Latch Enable Output. Can be used for latching the
address into external memory or an address latch in the
multiplexed bus modes.

External Access Enable pin. A low level at this pin during and
after Reset forces the C161RI to begin instruction execution
out of external memory. A high level forces execution out of
the internal ROM. The C161RI must have this pin tied to `0'.
Note: This pin is expected to be used to accept the

programming voltage for OTP versions of the C161RI.

Pin Definitions and Functions (cont'd)

Symbol

Pin No.
TQFP

Pin No.
MQFP

Input
Outp

Function

Semiconductor Group

1998-05-01

C161RI

PORT0:
P0L.0
P0L.7,
P0H.0 -
P0H.7

38
45,
48
55

40
47,
50
57

I/O

PORT0 consists of the two 8-bit bidirectional I/O ports P0L
and P0H. It is bit-wise programmable for input or output via
direction bits. For a pin configured as input, the output driver
is put into high-impedance state.
In case of external bus configurations, PORT0 serves as the
address (A) and address/data (AD) bus in multiplexed bus
modes and as the data (D) bus in demultiplexed bus modes.
Demultiplexed bus modes:
Data Path Width:

8-bit

16-bit

P0L.0 P0L.7:

D0 D7

D0 - D7

P0H.0 P0H.7:

I/O

D8 - D15

Multiplexed bus modes:
Data Path Width:

8-bit

16-bit

P0L.0 P0L.7:

AD0 AD7

AD0 - AD7

P0H.0 P0H.7:

A8 - A15

AD8 - AD15

PORT1:
P1L.0
P1L.7,
P1H.0 -
P1H.7

56
63,
66
73

58 -
65,
68 -
75

I/O

PORT1 consists of the two 8-bit bidirectional I/O ports P1L
and P1H. It is bit-wise programmable for input or output via
direction bits. For a pin configured as input, the output driver
is put into high-impedance state. PORT1 is used as the 16-
bit address bus (A) in demultiplexed bus modes and also
after switching from a demultiplexed bus mode to a
multiplexed bus mode.

RSTIN

Reset Input with Schmitt-Trigger characteristics. A low level
at this pin for a specified duration while the oscillator is
running resets the C161RI. An internal pullup resistor permits
power-on reset using only a capacitor connected to

In bidirectional reset mode (enabled by setting bit BDRSTEN
in register SYSCON) the RSTIN line is internally pulled low
for the duration of the internal reset sequence upon a
software reset, a WDT reset and a hardware reset.

RSTOUT 77

Internal Reset Indication Output. This pin is set to a low level
when the part is executing either a hardware-, a software- or
a watchdog timer reset. RSTOUT remains low until the EINIT
(end of initialization) instruction is executed.

NMI

Non-Maskable Interrupt Input. A high to low transition at this
pin causes the CPU to vector to the NMI trap routine. When
the PWRDN (power down) instruction is executed, the NMI
pin must be low in order to force the C161RI to go into power
down mode. If NMI is high, when PWRDN is executed, the
part will continue to run in normal mode.
If not used, pin NMI should be pulled high externally.

Pin Definitions and Functions (cont'd)

Symbol

Pin No.
TQFP

Pin No.
MQFP

Input
Outp

Function

Semiconductor Group

1998-05-01

C161RI

The following behavior differences must be observed when the bidirectional reset is active:

Bit BDRSTEN in register SYSCON cannot be changed after EINIT.

After a reset bit BDRSTEN is cleared.

The reset indication flags always indicate a long hardware reset.

The PORT0 configuration is treated like on a hardware reset. Especially the bootstrap loader
may be activated when P0L.4 is low.

Pin RSTIN may only be connected to external reset devices with an open drain output driver.

A short hardware reset is extended to the duration of the internal reset sequence.

P6.0
P6.7

79
86

79
...
83
84
85
86

81
88

81
...
85
86
87
88

I/O
I/O

O
...
O
I/O
I/O
I/O

Port 6 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-
impedance state.
The Port 6 pins also serve for alternate functions:
P6.0

CS0

Chip Select 0 Output

...

P6.4

CS4

Chip Select 4 Output

P6.5

SDA1

C Bus Data Line 1

P6.6

SCL1

C Bus Clock Line 1

P6.7

SDA2

C Bus Data Line 2

Note:

Pins P6.5-P6.7 are open drain outputs only.

P2.8
P2.15

87
94

87
...
94

89
96

89
...
96

I/O
I/O

I
...
I

Port 2 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-
impedance state.
The following Port 2 pins also serve for alternate functions:
P2.8

EX0IN

Fast External Interrupt 0 Input

...

P2.15

EX7IN

Fast External Interrupt 7 Input

AREF

Reference voltage for the A/D converter.

AGND

Reference ground for the A/D converter.

6, 23,
37, 47,
65, 75

8, 25,
39, 49,
67, 77

Digital Supply Voltage:
+ 5 V during normal operation and idle mode.

2.5 V during power down mode

3, 22,
36, 46,
64, 74

5, 24,
38, 48,
66, 76

Digital Ground.

Pin Definitions and Functions (cont'd)

Symbol

Pin No.
TQFP

Pin No.
MQFP

Input
Outp

Function

Semiconductor Group

1998-05-01

C161RI

Functional Description

The C161RI is a low cost downgrade of the high performance microcontroller C167CR with OTP or
internal ROM, reduced peripheral functionality and a high performance Capture Compare Unit with
an additional functionality.

The architecture of the C161RI combines advantages of both RISC and CISC processors and of
advanced peripheral subsystems in a very well-balanced way. The following block diagram gives an
overview of the different on-chip components and of the advanced, high bandwidth internal bus
structure of the C161RI.

Note: All time specifications refer to a CPU clock of 16 MHz

(see definition in the AC Characteristics section).

Figure 4
Block Diagram

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Semiconductor Group

1998-05-01

C161RI

Memory Organization

The memory space of the C161RI is configured in a Von Neumann architecture which means that
code memory, data memory, registers and I/O ports are organized within the same linear address
space which includes 16 MBytes. The entire memory space can be accessed bytewise or
wordwise. Particular portions of the on-chip memory have additionally been made directly
bitaddressable.

1 KByte of on-chip Internal RAM is provided as a storage for user defined variables, for the system
stack, general purpose register banks and even for code. A register bank can consist of up to 16
wordwide (R0 to R15) and/or bytewide (RL0, RH0, ..., RL7, RH7) so-called General Purpose
Registers (GPRs).

1024 bytes (2

512 bytes) of the address space are reserved for the Special Function Register

areas (SFR space and ESFR space). SFRs are wordwide registers which are used for controlling
and monitoring functions of the different on-chip units. Unused SFR addresses are reserved for
future members of the C166 family.

In order to meet the needs of designs where more memory is required than is provided on chip, up
to 8 MBytes of external RAM and/or ROM can be connected to the microcontroller.

Semiconductor Group

1998-05-01

C161RI

External Bus Controller

All of the external memory accesses are performed by a particular on-chip External Bus Controller
(EBC). It can be programmed either to Single Chip Mode when no external memory is required, or
to one of four different external memory access modes, which are as follows:

16-/18-/20-/23-bit Addresses, 16-bit Data, Demultiplexed

16-/18-/20-/23-bit Addresses, 16-bit Data, Multiplexed

16-/18-/20-/23-bit Addresses, 8-bit Data, Multiplexed

16-/18-/20-/23-bit Addresses, 8-bit Data, Demultiplexed

In the demultiplexed bus modes, addresses are output on PORT1 and data is input/output on
PORT0 or P0L, respectively. In the multiplexed bus modes both addresses and data use PORT0 for
input/output.

Important timing characteristics of the external bus interface (Memory Cycle Time, Memory
Tri-State Time, Length of ALE and Read Write Delay) have been made programmable to allow the
user the adaption of a wide range of different types of memories and external peripherals.
In addition, up to 4 independent address windows may be defined (via register pairs ADDRSELx /
BUSCONx) which allow to access different resources with different bus characteristics. These
address windows are arranged hierarchically where BUSCON4 overrides BUSCON3 and
BUSCON2 overrides BUSCON1. All accesses to locations not covered by these 4 address windows
are controlled by BUSCON0.
Up to 5 external CS signals (4 windows plus default) can be generated in order to save external glue
logic. Access to very slow memories is supported via a particular `Ready' function.

For applications which require less than 8 MBytes of external memory space, this address space
can be restricted to 1 MByte, 256 KByte or to 64 KByte. In this case Port 4 outputs four, two or no
address lines at all. It outputs all 7 address lines, if an address space of 8 MBytes is used.

Semiconductor Group

1998-05-01

C161RI

Central Processing Unit (CPU)

The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit
(ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divide
unit, a bit-mask generator and a barrel shifter.

Based on these hardware provisions, most of the C161RI's instructions can be executed in just one
machine cycle which requires 125 ns at 16 MHz CPU clock. For example, shift and rotate
instructions are always processed during one machine cycle independent of the number of bits to
be shifted. All multiple-cycle instructions have been optimized so that they can be executed very fast
as well: branches in 2 cycles, a 16

16 bit multiplication in 5 cycles and a 32-/16 bit division in

10 cycles. Another pipeline optimization, the so-called `Jump Cache', allows reducing the execution
time of repeatedly performed jumps in a loop from 2 cycles to 1 cycle.

Figure 5
CPU Block Diagram

MCB02147

CPU

STKOV

STKUN

Instr. Reg.

Instr. Ptr.

Exec. Unit

4-Stage

Pipeline

MDH

MDL

PSW

SYSCON

Context Ptr.

Mul/Div-HW

R15

General

Purpose

Registers

Bit-Mask Gen

Barrel - Shifter

ALU

(16-bit)

Data Page Ptr.

Code Seg. Ptr.

Internal

RAM

R15

ROM

BUSCON 0
BUSCON 1
BUSCON 2
BUSCON 3
BUSCON 4

ADDRSEL 4

ADDRSEL 3

ADDRSEL 2

ADDRSEL 1

Semiconductor Group

1998-05-01

C161RI

The CPU disposes of an actual register context consisting of up to 16 wordwide GPRs which are
physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the
base address of the active register bank to be accessed by the CPU at a time. The number of
register banks is only restricted by the available internal RAM space. For easy parameter passing,
a register bank may overlap others.

A system stack of up to 1024 bytes is provided as a storage for temporary data. The system stack
is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP)
register. Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack
pointer value upon each stack access for the detection of a stack overflow or underflow.

The high performance offered by the hardware implementation of the CPU can efficiently be utilized
by a programmer via the highly efficient C161RI instruction set which includes the following
instruction classes:

Arithmetic Instructions
Logical Instructions
Boolean Bit Manipulation Instructions
Compare and Loop Control Instructions
Shift and Rotate Instructions
Prioritize Instruction
Data Movement Instructions
System Stack Instructions
Jump and Call Instructions
Return Instructions
System Control Instructions
Miscellaneous Instructions

The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes and words.
A variety of direct, indirect or immediate addressing modes are provided to specify the required
operands.

Semiconductor Group

1998-05-01

C161RI

Interrupt System

With an interrupt response time within a range from just 315 ns to 750 ns (in case of internal
program execution), the C161RI is capable of reacting very fast to the occurrence of non-
deterministic events.

The architecture of the C161RI supports several mechanisms for fast and flexible response to
service requests that can be generated from various sources internal or external to the
microcontroller. Any of these interrupt requests can be programmed to being serviced by the
Interrupt Controller or by the Peripheral Event Controller (PEC).

In contrast to a standard interrupt service where the current program execution is suspended and
a branch to the interrupt vector table is performed, just one cycle is `stolen' from the current CPU
activity to perform a PEC service. A PEC service implies a single byte or word data transfer between
any two memory locations with an additional increment of either the PEC source or the destination
pointer. An individual PEC transfer counter is implicity decremented for each PEC service except
when performing in the continuous transfer mode. When this counter reaches zero, a standard
interrupt is performed to the corresponding source related vector location. PEC services are very
well suited, for example, for supporting the transmission or reception of blocks of data. The C161RI
has 8 PEC channels each of which offers such fast interrupt-driven data transfer capabilities.

A separate control register which contains an interrupt request flag, an interrupt enable flag and an
interrupt priority bitfield exists for each of the possible interrupt sources. Via its related register, each
source can be programmed to one of sixteen interrupt priority levels. Once having been accepted
by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For
the standard interrupt processing, each of the possible interrupt sources has a dedicated vector
location.

Fast external interrupt inputs are provided to service external interrupts with high precision
requirements. These fast interrupt inputs feature programmable edge detection (rising edge, falling
edge or both edges).

Software interrupts are supported by means of the `TRAP' instruction in combination with an
individual trap (interrupt) number.

Semiconductor Group

1998-05-01

C161RI

The following table shows all of the possible C161RI interrupt sources and the corresponding
hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers:

Source of Interrupt or
PEC Service Request

Request
Flag

Enable
Flag

Interrupt
Vector

Vector
Location

Trap
Number

External Interrupt 0

CC8IR

CC8IE

CC8INT

00'0060

External Interrupt 1

CC9IR

CC9IE

CC9INT

00'0064

External Interrupt 2

CC10IR

CC10IE

CC10INT

00'0068

External Interrupt 3

CC11IR

CC11IE

CC11INT

00'006C

External Interrupt 4

CC12IR

CC12IE

CC12INT

00'0070

External Interrupt 5

CC13IR

CC13IE

CC13INT

00'0074

External Interrupt 6

CC14IR

CC14IE

CC14INT

00'0078

External Interrupt 7

CC15IR

CC15IE

CC15INT

00'007C

GPT1 Timer 2

T2IR

T2IE

T2INT

00'0088

GPT1 Timer 3

T3IR

T3IE

T3INT

00'008C

GPT1 Timer 4

T4IR

T4IE

T4INT

00'0090

GPT2 Timer 5

T5IR

T5IE

T5INT

00'0094

GPT2 Timer 6

T6IR

T6IE

T6INT

00'0098

GPT2 CAPREL Register

CRIR

CRIE

CRINT

00'009C

A/D Conversion Complete ADCIR

ADCIE

ADCINT

00'00A0

A/D Overrun Error

ADEIR

ADEIE

ADEINT

00'00A4

ASC0 Transmit

S0TIR

S0TIE

S0TINT

00'00A8

ASC0 Transmit Buffer

S0TBIR

S0TBIE

S0TBINT

00'011C

ASC0 Receive

S0RIR

S0RIE

S0RINT

00'00AC

ASC0 Error

S0EIR

S0EIE

S0EINT

00'00B0

SSC Transmit

SCTIR

SCTIE

SCTINT

00'00B4

SSC Receive

SCRIR

SCRIE

SCRINT

00'00B8

SSC Error

SCEIR

SCEIE

SCEINT

00'00BC

C Data Transfer Event

XP0IR

XP0IE

XP0INT

00'0100

C Protocol Event

XP1IR

XP1IE

XP1INT

00'0104

X-Peripheral Node 2

XP2IR

XP2IE

XP2INT

00'0108

PLL Unlock / RTC

XP3IR

XP3IE

XP3INT

00'010C

Semiconductor Group

1998-05-01

C161RI

The C161RI also provides an excellent mechanism to identify and to process exceptions or error
conditions that arise during run-time, so-called `Hardware Traps'. Hardware traps cause immediate
non-maskable system reaction which is similar to a standard interrupt service (branching to a
dedicated vector table location). The occurence of a hardware trap is additionally signified by an
individual bit in the trap flag register (TFR). Except when another higher prioritized trap service is in
progress, a hardware trap will interrupt any actual program execution. In turn, hardware trap
services can normally not be interrupted by standard or PEC interrupts.

The following table shows all of the possible exceptions or error conditions that can arise during run-
time:

Exception Condition

Trap
Flag

Trap
Vector

Vector
Location

Trap
Number

Trap
Priority

Reset Functions:

Hardware Reset
Software Reset
Watchdog Timer Overflow

RESET
RESET
RESET

00'0000

III
III
III

Class A Hardware Traps:

Non-Maskable Interrupt
Stack Overflow
Stack Underflow

NMI
STKOF
STKUF

NMITRAP
STOTRAP
STUTRAP

00'0008

00'0010

00'0018

II
II
II

Class B Hardware Traps:

Undefined Opcode
Protected Instruction
Fault
Illegal Word Operand
Access
Illegal Instruction Access
Illegal External Bus
Access

UNDOPC
PRTFLT

ILLOPA

ILLINA
ILLBUS

BTRAP
BTRAP

BTRAP

BTRAP
BTRAP

00'0028

I
I

Reserved

[2C

] [0B

]

Software Traps

TRAP Instruction

Any
[00'0000

00'01FC

]

in steps
of 4

Any
[00

]

Current
CPU
Priority

Semiconductor Group

1998-05-01

C161RI

General Purpose Timer (GPT) Unit

The GPT unit represents a very flexible multifunctional timer/counter structure which may be used
for many different time related tasks such as event timing and counting, pulse width and duty cycle
measurements, pulse generation, or pulse multiplication.

The GPT unit incorporates five 16-bit timers which are organized in two separate modules, GPT1
and GPT2. Each timer in each module may operate independently in a number of different modes,
or may be concatenated with another timer of the same module.

Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for one of four
basic modes of operation, which are Timer, Gated Timer, Counter, and Incremental Interface Mode.
In Timer Mode, the input clock for a timer is derived from the CPU clock, divided by a programmable
prescaler, while Counter Mode allows a timer to be clocked in reference to external events.
Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the operation of
a timer is controlled by the `gate' level on an external input pin. For these purposes, each timer has
one associated port pin (TxIN) which serves as gate or clock input. The maximum resolution of the
timers in module GPT1 is 500 ns (@ 16 MHz CPU clock).

The count direction (up/down) for each timer is programmable by software or may additionally be
altered dynamically by an external signal on a port pin (TxEUD) to facilitate e.g. position tracking.

In Incremental Interface Mode the GPT1 timers (T2, T3, T4) can be directly connected to the
incremental position sensor signals A and B via their respective inputs TxIN and TxEUD. Direction
and count signals are internally derived from these two input signals, so the contents of the
respective timer Tx corresponds to the sensor position. The third position sensor signal TOP0 can
be connected to an interrupt input.

Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer over-flow/
underflow. The state of this latch may be output on a port pin (T3OUT) e.g. for time out monitoring
of external hardware components, or may be used internally to clock timers T2 and T4 for
measuring long time periods with high resolution.

In addition to their basic operating modes, timers T2 and T4 may be configured as reload or capture
registers for timer T3. When used as capture or reload registers, timers T2 and T4 are stopped. The
contents of timer T3 are captured into T2 or T4 in response to a signal at their associated input pins
(TxIN). Timer T3 is reloaded with the contents of T2 or T4 triggered either by an external signal or
by a selectable state transition of its toggle latch T3OTL. When both T2 and T4 are configured to
alternately reload T3 on opposite state transitions of T3OTL with the low and high times of a PWM
signal, this signal can be constantly generated without software intervention.

With its maximum resolution of 250 ns (@ 16 MHz), the GPT2 module provides precise event
control and time measurement. It includes two timers (T5, T6) and a capture/reload register
(CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock via
a programmable prescaler. The count direction (up/down) for each timer is programmable by
software. Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6,
which changes its state on each timer overflow/underflow.

The state of this latch may be used to clock timer T5. The overflows/underflows of timer T6 can
additionally be used to cause a reload from the CAPREL register. The CAPREL register may
capture the contents of timer T5 based on an external signal transition on the corresponding port pin

Semiconductor Group

1998-05-01

C161RI

(CAPIN), and timer T5 may optionally be cleared after the capture procedure. This allows absolute
time differences to be measured or pulse multiplication to be performed without software overhead.

The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of GPT1 timer
T3's inputs T3IN and/or T3EUD. This is especially advantageous when T3 operates in Incremental
Interface Mode.

Figure 6
Block Diagram of GPT1

MCB02141

GPT1 Timer T2

Mode

Control

Interrupt
Request

T2IN

n = 3...10

CPU Clock

Reload

Capture

T2EUD

Mode

Control

CPU Clock

n = 3...10

T3IN

GPT1 Timer T3

T3OTL

Request

Interrupt

Control

Mode

Reload

Capture

CPU Clock

n = 3...10

T4IN

Request

Interrupt

GPT1 Timer T4

T4EUD

T3EUD

Toggle FF

U/D

Semiconductor Group

1998-05-01

C161RI

Figure 7
Block Diagram of GPT2

Watchdog Timer

The Watchdog Timer represents one of the fail-safe mechanisms which have been implemented to
prevent the controller from malfunctioning for longer periods of time.

The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time
interval until the EINIT (end of initialization) instruction has been executed. Thus, the chip's start-up
procedure is always monitored. The software has to be designed to service the Watchdog Timer
before it overflows. If, due to hardware or software related failures, the software fails to do so, the
Watchdog Timer overflows and generates an internal hardware reset and pulls the RSTOUT pin low
in order to allow external hardware components to be reset.

The Watchdog Timer is a 16-bit timer, clocked with the system clock divided either by 2 or by 128.
The high byte of the Watchdog Timer register can be set to a prespecified reload value (stored in
WDTREL) in order to allow further variation of the monitored time interval. Each time it is serviced
by the application software, the high byte of the Watchdog Timer is reloaded. Thus, time intervals
between 31

s and 525 ms can be monitored (@ 16 MHz). The default Watchdog Timer interval

after reset is 8.2 ms (@ 16 MHz).

GPT2 Timer T5

n=2...9

Mode

Control

GPT2 Timer T6

Mode

Control

GPT2 CAPREL

T6OTL

Interrupt
Request

CPU

Interrupt
Request

n=2...9

CPU

Clock

Interrupt
Request

CAPIN

Clear

Capture

Semiconductor Group

1998-05-01

C161RI

Real Time Clock

The Real Time Clock (RTC) module of the C161RI consists of a chain of 3 divider blocks, a fixed
8-bit divider, the reloadable 16-bit timer T14 and the 32-bit RTC timer (accessible via registers
RTCH and RTCL). The RTC module is directly clocked with the on-chip oscillator frequency divided
by 32 via a separate clock driver and is therefore independent from the selected clock generation
mode of the C161RI. All timers count up.

The RTC module can be used for different purposes:

System clock to determine the current time and date

Cyclic time based interrupt

48-bit timer for long term measurements

Figure 7-1
RTC Block Diagram

Note: The registers associated with the RTC are not effected by a reset in order to maintain the

correct system time even when intermediate resets are executed.

RTCL

T14

T14REL

8:1

RTC

Reload

Interrupt
Request

Semiconductor Group

1998-05-01

C161RI

A/D Converter

For analog signal measurement, an 8-bit A/D converter with 4 multiplexed input channels and a
sample and hold circuit has been integrated on-chip. It uses the method of successive
approximation. The sample time (for loading the capacitors) and the conversion time is
programmable and can so be adjusted to the external circuitry.

Overrun error detection is provided for the conversion result register (ADDAT): an interrupt request
will be generated when the result of a previous conversion has not been read from the result register
at the time the next conversion is complete.

For applications which require less than 4 analog input channels, the remaining channel inputs can
be used as digital input port pins.

The A/D converter of the C161RI supports two different conversion modes. In the standard Single
Channel conversion mode, the analog level on a specified channel is sampled once and converted
to a digital result. In the Single Channel Continuous mode, the analog level on a specified channel
is repeatedly sampled and converted without software intervention.

The 8-bit result can be left-aligned or right-aligned within a 10-bit result area.

The Peripheral Event Controller (PEC) may be used to automatically store the conversion results
into a table in memory for later evaluation, without requiring the overhead of entering and exiting
interrupt routines for each data transfer.

C Module

The integrated

C Bus Module handles the transmission and reception of frames over the two-line

C bus in accordance with the

C Bus specification. The on-chip

C Module can receive and

transmit data using 7-bit or 10-bit addressing and it can operate in slave mode, in master mode or
in multi-master mode.

Several physical interfaces (port pins) can be established under software control. Data can be
transferred at speeds up to 400 Kbit/sec.

Two interrupt nodes dedicated to the

C module allow efficient interrupt service and also support

operation via PEC transfers.

Note: The port pins associated with the

C interfaces feature open drain drivers only, as required

by the

C specification.

Semiconductor Group

1998-05-01

C161RI

Serial Channels

Serial communication with other microcontrollers, processors, terminals or external peripheral
components is provided by two serial interfaces with different functionality, an Asynchronous/
Synchronous Serial Channel (ASC0) and a High-Speed Synchronous Serial Channel (SSC).

The ASC0 is upward compatible with the serial ports of the Siemens 8-bit microcontroller families
and supports full-duplex asynchronous communication at up to 500 KBaud and half-duplex
synchronous communication at up to 2 MBaud @ 16 MHz CPU clock.
A dedicated baud rate generator allows to set up all standard baud rates without oscillator tuning.
For transmission, reception and error handling 4 separate interrupt vectors are provided. In
asynchronous mode, 8- or 9-bit data frames are transmitted or received, preceded by a start bit and
terminated by one or two stop bits. For multiprocessor communication, a mechanism to distinguish
address from data bytes has been included (8-bit data plus wake up bit mode).
In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a shift clock
which is generated by the ASC0. The ASC0 always shifts the LSB first. A loop back option is
available for testing purposes.
A number of optional hardware error detection capabilities has been included to increase the
reliability of data transfers. A parity bit can automatically be generated on transmission or be
checked on reception. Framing error detection allows to recognize data frames with missing stop
bits. An overrun error will be generated, if the last character received has not been read out of the
receive buffer register at the time the reception of a new character is complete.

The SSC supports full-duplex synchronous communication at up to 4 Mbaud @ 16 MHz CPU clock.
It may be configured so it interfaces with serially linked peripheral components. A dedicated baud
rate generator allows to set up all standard baud rates without oscillator tuning. For transmission,
reception and error handling 3 separate interrupt vectors are provided.
The SSC transmits or receives characters of 2...16 bits length synchronously to a shift clock which
can be generated by the SSC (master mode) or by an external master (slave mode). The SSC can
start shifting with the LSB or with the MSB and allows the selection of shifting and latching clock
edges as well as the clock polarity.
A number of optional hardware error detection capabilities has been included to increase the
reliability of data transfers. Transmit and receive error supervise the correct handling of the data
buffer. Phase and baudrate error detect incorrect serial data.

Semiconductor Group

1998-05-01

C161RI

Parallel Ports

The C161RI provides up to 76 IO lines which are organized into six input/output ports and one input
port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise)
programmable as inputs or outputs via direction registers. The I/O ports are true bidirectional ports
which are switched to high impedance state when configured as inputs. The output drivers of three
IO ports can be configured (pin by pin) for push/pull operation or open-drain operation via control
registers. The other IO ports operate in push/pull mode, except for the

C interface pins which are

open drain pins only. During the internal reset, all port pins are configured as inputs.

All port lines have programmable alternate input or output functions associated with them.
PORT0 and PORT1 may be used as address and data lines when accessing external memory,
while Port 4 outputs the additional segment address bits A22/19/17...A16 in systems where
segmentation is enabled to access more than 64 KBytes of memory.

Port 3 includes alternate functions of timers, serial interfaces, the optional bus control signal BHE
and the system clock output (CLKOUT).
Port 5 is used for the analog input channels to the A/D converter or timer control signals.

Port 6 provides the optional chip select signals and interface lines for the

C module.

All port lines that are not used for these alternate functions may be used as general purpose IO
lines.

Semiconductor Group

1998-05-01

C161RI

Instruction Set Summary

The table below lists the instructions of the C161RI in a condensed way.
The various addressing modes that can be used with a specific instruction, the operation of the
instructions, parameters for conditional execution of instructions, and the opcodes for each
instruction can be found in the "C166 Family Instruction Set Manual".

This document also provides a detailed description of each instruction.

Instruction Set Summary

Mnemonic

Description

Bytes

ADD(B)

Add word (byte) operands

2 / 4

ADDC(B)

Add word (byte) operands with Carry

2 / 4

SUB(B)

Subtract word (byte) operands

2 / 4

SUBC(B)

Subtract word (byte) operands with Carry

2 / 4

MUL(U)

(Un)Signed multiply direct GPR by direct GPR (16-16-bit)

DIV(U)

(Un)Signed divide register MDL by direct GPR (16-/16-bit)

DIVL(U)

(Un)Signed long divide reg. MD by direct GPR (32-/16-bit)

CPL(B)

Complement direct word (byte) GPR

NEG(B)

Negate direct word (byte) GPR

AND(B)

Bitwise AND, (word/byte operands)

2 / 4

OR(B)

Bitwise OR, (word/byte operands)

2 / 4

XOR(B)

Bitwise XOR, (word/byte operands)

2 / 4

BCLR

Clear direct bit

BSET

Set direct bit

BMOV(N)

Move (negated) direct bit to direct bit

BAND, BOR, BXOR

AND/OR/XOR direct bit with direct bit

BCMP

Compare direct bit to direct bit

BFLDH/L

Bitwise modify masked high/low byte of bit-addressable
direct word memory with immediate data

CMP(B)

Compare word (byte) operands

2 / 4

CMPD1/2

Compare word data to GPR and decrement GPR by 1/2

2 / 4

CMPI1/2

Compare word data to GPR and increment GPR by 1/2

2 / 4

PRIOR

Determine number of shift cycles to normalize direct
word GPR and store result in direct word GPR

SHL / SHR

Shift left/right direct word GPR

ROL / ROR

Rotate left/right direct word GPR

ASHR

Arithmetic (sign bit) shift right direct word GPR

Semiconductor Group

1998-05-01

C161RI

MOV(B)

Move word (byte) data

2 / 4

MOVBS

Move byte operand to word operand with sign extension

2 / 4

MOVBZ

Move byte operand to word operand. with zero extension

2 / 4

JMPA, JMPI, JMPR

Jump absolute/indirect/relative if condition is met

JMPS

Jump absolute to a code segment

J(N)B

Jump relative if direct bit is (not) set

JBC

Jump relative and clear bit if direct bit is set

JNBS

Jump relative and set bit if direct bit is not set

CALLA, CALLI, CALLR

Call absolute/indirect/relative subroutine if condition is met

CALLS

Call absolute subroutine in any code segment

PCALL

Push direct word register onto system stack and call
absolute subroutine

TRAP

Call interrupt service routine via immediate trap number

PUSH, POP

Push/pop direct word register onto/from system stack

SCXT

Push direct word register onto system stack and update
register with word operand

RET

Return from intra-segment subroutine

RETS

Return from inter-segment subroutine

RETP

Return from intra-segment subroutine and pop direct
word register from system stack

RETI

Return from interrupt service subroutine

SRST

Software Reset

IDLE

Enter Idle Mode

PWRDN

Enter Power Down Mode
(supposes NMI-pin being low)

SRVWDT

Service Watchdog Timer

DISWDT

Disable Watchdog Timer

EINIT

Signify End-of-Initialization on RSTOUT-pin

ATOMIC

Begin ATOMIC sequence

EXTR

Begin EXTended Register sequence

EXTP(R)

Begin EXTended Page (and Register) sequence

2 / 4

EXTS(R)

Begin EXTended Segment (and Register) sequence

2 / 4

NOP

Null operation

Instruction Set Summary (cont'd)

Mnemonic

Description

Bytes

Semiconductor Group

1998-05-01

C161RI

Special Function Registers Overview

The following table lists all SFRs which are implemented in the C161RI in alphabetical order.
Bit-addressable SFRs are marked with the letter "b" in column "Name". SFRs within the Extended
SFR-Space (ESFRs) are marked with the letter "E" in column "Physical Address". Registers within
on-chip X-Peripherals (

C) are marked with the letter "X" in column "Physical Address".

An SFR can be specified via its individual mnemonic name. Depending on the selected addressing
mode, an SFR can be accessed via its physical address (using the Data Page Pointers), or via its
short 8-bit address (without using the Data Page Pointers).

Name

Physical
Address

8-Bit
Address

Description

Reset
Value

ADCIC

b FF98

A/D Converter End of Conversion Interrupt
Control Register

0000

ADCON

b FFA0

A/D Converter Control Register

0000

ADDAT

FEA0

A/D Converter Result Register

0000

ADDRSEL1

FE18

Address Select Register 1

0000

ADDRSEL2

FE1A

Address Select Register 2

0000

ADDRSEL3

FE1C

Address Select Register 3

0000

ADDRSEL4

FE1E

Address Select Register 4

0000

ADEIC

b FF9A

A/D Converter Overrun Error Interrupt Control
Register

0000

BUSCON0 b FF0C

Bus Configuration Register 0

0000

BUSCON1 b FF14

Bus Configuration Register 1

0000

BUSCON2 b FF16

Bus Configuration Register 2

0000

BUSCON3 b FF18

Bus Configuration Register 3

0000

BUSCON4 b FF1A

Bus Configuration Register 4

0000

CAPREL

FE4A

GPT2 Capture/Reload Register

0000

CC8IC

b FF88

External Interrupt 0 Control Register

0000

CC9IC

b FF8A

External Interrupt 1 Control Register

0000

CC10IC

b FF8C

External Interrupt 2 Control Register

0000

CC11IC

b FF8E

External Interrupt 3 Control Register

0000

CC12IC

b FF90

External Interrupt 4 Control Register

0000

CC13IC

b FF92

External Interrupt 5 Control Register

0000

CC14IC

b FF94

External Interrupt 6 Control Register

0000

CC15IC

b FF96

External Interrupt 7 Control Register

0000

FE10

CPU Context Pointer Register

FC00

Semiconductor Group

1998-05-01

C161RI

CRIC

b FF6A

GPT2 CAPREL Interrupt Control Register

0000

CSP

FE08

CPU Code Segment Pointer Register
(8 bits, not directly writeable)

0000

DP0L

b F100

E 80

P0L Direction Control Register

DP0H

b F102

E 81

P0H Direction Control Register

DP1L

b F104

E 82

P1L Direction Control Register

DP1H

b F106

E 83

P1H Direction Control Register

DP2

b FFC2

Port 2 Direction Control Register

0000

DP3

b FFC6

Port 3 Direction Control Register

0000

DP4

b FFCA

Port 4 Direction Control Register

DP6

b FFCE

Port 6 Direction Control Register

DPP0

FE00

CPU Data Page Pointer 0 Register (10 bits)

0000

DPP1

FE02

CPU Data Page Pointer 1 Register (10 bits)

0001

DPP2

FE04

CPU Data Page Pointer 2 Register (10 bits)

0002

DPP3

FE06

CPU Data Page Pointer 3 Register (10 bits)

0003

EXICON

b F1C0

E E0

External Interrupt Control Register

0000

ICADR

ED06

X ---

C Address Register

0XXX

ICCFG

ED00

X ---

C Configuration Register

XX00

ICCON

ED02

X ---

C Control Register

0000

ICRTB

ED08

X ---

C Receive/Transmit Buffer

ICST

ED04

X ---

C Status Register

0000

IDCHIP

F07C

E 3E

Identifier

09XX

IDMANUF

F07E

E 3F

Identifier

1820

IDMEM

F07A

E 3D

Identifier

0000

IDPROG

F078

E 3C

Identifier

0000

ISNC

b F1DE

E EF

Interrupt Subnode Control Register

0000

MDC

b FF0E

CPU Multiply Divide Control Register

0000

MDH

FE0C

CPU Multiply Divide Register High Word

0000

MDL

FE0E

CPU Multiply Divide Register Low Word

0000

ODP2

b F1C2

E E1

Port 2 Open Drain Control Register

0000

ODP3

b F1C6

E E3

Port 3 Open Drain Control Register

0000

ODP6

b F1CE

E E7

Port 6 Open Drain Control Register

ONES

b FF1E

Constant Value 1's Register (read only)

FFFF

Name

Physical
Address

8-Bit
Address

Description

Reset
Value

Semiconductor Group

1998-05-01

C161RI

P0L

b FF00

Port 0 Low Register (Lower half of PORT0)

P0H

b FF02

Port 0 High Register (Upper half of PORT0)

P1L

b FF04

Port 1 Low Register (Lower half of PORT1)

P1H

b FF06

Port 1 High Register (Upper half of PORT1)

b FFC0

Port 2 Register

0000

b FFC4

Port 3 Register

0000

b FFC8

Port 4 Register (7 bits)

b FFA2

Port 5 Register (read only)

XXXX

P5DIDIS

b FFA4

Port 5 Digital Input Disable Register

0000

b FFCC

Port 6 Register (8 bits)

PECC0

FEC0

PEC Channel 0 Control Register

0000

PECC1

FEC2

PEC Channel 1 Control Register

0000

PECC2

FEC4

PEC Channel 2 Control Register

0000

PECC3

FEC6

PEC Channel 3 Control Register

0000

PECC4

FEC8

PEC Channel 4 Control Register

0000

PECC5

FECA

PEC Channel 5 Control Register

0000

PECC6

FECC

PEC Channel 6 Control Register

0000

PECC7

FECE

PEC Channel 7 Control Register

0000

PSW

b FF10

CPU Program Status Word

0000

RP0H

b F108

E 84

System Startup Configuration Register (Rd. only)

RTCH

F0D6

E 6B

RTC High Register

RTCL

F0D4

E 6A

RTC Low Register

S0BG

FEB4

Serial Channel 0 Baud Rate Generator Reload
Register

0000

S0CON

b FFB0

Serial Channel 0 Control Register

0000

S0EIC

b FF70

Serial Channel 0 Error Interrupt Control Register

0000

S0RBUF

FEB2

Serial Channel 0 Receive Buffer Register
(read only)

XXXX

S0RIC

b FF6E

Serial Channel 0 Receive Interrupt Control
Register

0000

S0TBIC

b F19C

E CE

Serial Channel 0 Transmit Buffer Interrupt Control
Register

0000

S0TBUF

FEB0

Serial Channel 0 Transmit Buffer Register

0000

Name

Physical
Address

8-Bit
Address

Description

Reset
Value

Semiconductor Group

1998-05-01

C161RI

S0TIC

b FF6C

Serial Channel 0 Transmit Interrupt Control
Register

0000

FE12

CPU System Stack Pointer Register

FC00

SSCBR

F0B4

E 5A

SSC Baudrate Register

0000

SSCCON

b FFB2

SSC Control Register

0000

SSCEIC

b FF76

SSC Error Interrupt Control Register

0000

SSCRB

F0B2

E 59

SSC Receive Buffer (read only)

XXXX

SSCRIC

b FF74

SSC Receive Interrupt Control Register

0000

SSCTB

F0B0

E 58

SSC Transmit Buffer (write only)

0000

SSCTIC

b FF72

SSC Transmit Interrupt Control Register

0000

STKOV

FE14

CPU Stack Overflow Pointer Register

FA00

STKUN

FE16

CPU Stack Underflow Pointer Register

FC00

SYSCON

b FF12

CPU System Configuration Register

0XX0

SYSCON2 b F1D0

E E8

CPU System Configuration Register 2

0000

SYSCON3 b F1D4

E EA

CPU System Configuration Register 3

0000

T14

F0D2

E 69

RTC Timer 14 Register

T14REL

F0D0

E 68

RTC Timer 14 Reload Register

FE40

GPT1 Timer 2 Register

0000

T2CON

b FF40

GPT1 Timer 2 Control Register

0000

T2IC

b FF60

GPT1 Timer 2 Interrupt Control Register

0000

FE42

GPT1 Timer 3 Register

0000

T3CON

b FF42

GPT1 Timer 3 Control Register

0000

T3IC

b FF62

GPT1 Timer 3 Interrupt Control Register

0000

FE44

GPT1 Timer 4 Register

0000

T4CON

b FF44

GPT1 Timer 4 Control Register

0000

T4IC

b FF64

GPT1 Timer 4 Interrupt Control Register

0000

FE46

GPT2 Timer 5 Register

0000

T5CON

b FF46

GPT2 Timer 5 Control Register

0000

T5IC

b FF66

GPT2 Timer 5 Interrupt Control Register

0000

FE48

GPT2 Timer 6 Register

0000

T6CON

b FF48

GPT2 Timer 6 Control Register

0000

T6IC

b FF68

GPT2 Timer 6 Interrupt Control Register

0000

TFR

b FFAC

Trap Flag Register

0000

Name

Physical
Address

8-Bit
Address

Description

Reset
Value

Semiconductor Group

1998-05-01

C161RI

The system configuration is selected during reset.

The reset value depends on the indicated reset source.

WDT

FEAE

Watchdog Timer Register (read only)

0000

WDTCON b FFAE

Watchdog Timer Control Register

00XX

XP0IC

b F186

E C3

C Data Interrupt Control Register

0000

XP1IC

b F18E

E C7

C Protocol Interrupt Control Register

0000

XP2IC

b F196

E CB

X-Peripheral 2 Interrupt Control Register

0000

XP3IC

b F19E

E CF

RTC Interrupt Control Register

0000

ZEROS

b FF1C

Constant Value 0's Register (read only)

0000

Name

Physical
Address

8-Bit
Address

Description

Reset
Value

Semiconductor Group

1998-05-01

C161RI

Absolute Maximum Ratings

Ambient temperature under bias (

SAB-C161RI ...................................................................................................................0 to + 70

SAF-C161RI .............................................................................................................. 40 to + 85

Storage temperature (

)........................................................................................ 65 to + 150

Voltage on

pins with respect to ground (

) ..................................................... 0.5 to + 6.5 V

Voltage on any pin with respect to ground (

) ................................................. 0.5 to

+ 0.5 V

Input current on any pin during overload condition .................................................. 10 to + 10 mA
Absolute sum of all input currents during overload condition ..............................................|100 mA|
Power dissipation..................................................................................................................... 1.5 W

Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent

damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
During absolute maximum rating overload conditions (

) the voltage on

pins with respect to ground (

) must not exceed the values defined by the absolute

maximum ratings.

Parameter Interpretation

The parameters listed in the following partly represent the characteristics of the C161RI and partly
its demands on the system. To aid in interpreting the parameters right, when evaluating them for a
design, they are marked in column "Symbol":

CC (Controller Characteristics):
The logic of the C161RI will provide signals with the respective timing characteristics.

SR (System Requirement):
The external system must provide signals with the respective timing characteristics to the C161RI.

Semiconductor Group

1998-05-01

C161RI

DC Characteristics

= 4.5 - 5.5 V;

= 0 V;

CPU

= 20 MHz

= 0 to + 70

for SAB-C161RI

= 40 to + 85

C for SAF-C161RI

Parameter

Symbol

Limit Values

Unit

Test Condition

min.

max.

Input low voltage
(P3.0, P3.1, P6.5, P6.6, P6.7)

IL1

0.5

0.3

Input low voltage
(TTL)

0.5

0.2

0.1

Input low voltage
(Special Threshold)

ILS

0.5

2.0

Input high voltage RSTIN

IH1

0.6

+ 0.5

Input high voltage XTAL1,
P3.0, P3.1, P6.5, P6.6, P6.7

IH2

0.7

+ 0.5

Input high voltage
(TTL)

0.2

+ 0.9

+ 0.5

Input high voltage
(Special Threshold)

IHS

0.8

0.2

+ 0.5

Input Hysteresis
(Special Threshold)

HYS

400

Output low voltage
(PORT0, PORT1, Port 4, ALE, RD,
WR, BHE, CLKOUT, RSTOUT)

0.45

= 2.4 mA

Output low voltage
(P3.0, P3.1, P6.5, P6.6, P6.7)

OL2

0.4

OL2

= 3 mA

Output low voltage
(all other outputs)

OL1

0.45

OL1

= 1.6 mA

Output high voltage
(PORT0, PORT1, Port 4, ALE, RD,
WR, BHE, CLKOUT, RSTOUT)

0.9

2.4

= 500

= 2.4 mA

Output high voltage

(all other outputs)

OH1

0.9

2.4

V
V

= 250

= 1.6 mA

Input leakage current (Port 5)

OZ1

200

0.45 V <

Input leakage current (all other)

OZ2

500

0.45 V <

Overload current

5) 8)

RSTIN pullup resistor

RST

250

Read/Write inactive current

RWH

OUT

= 2.4 V

Read/Write active current

RWL

500

OUT

OLmax

Semiconductor Group

1998-05-01

C161RI

ALE inactive current

ALEL

OUT

OLmax

ALE active current

ALEH

500

OUT

= 2.4 V

Port 6 inactive current

P6H

OUT

= 2.4 V

Port 6 active current

P6L

500

OUT

OL1max

PORT0 configuration current

P0H

IHmin

P0L

100

ILmax

XTAL1 input current

0 V <

Pin capacitance

(digital inputs/outputs)

= 1 MHz

= 25

Power supply current (active)
with all peripherals active

7 +
3

CPU

RSTIN =

IL2

CPU

in [MHz]

Idle mode supply current
with all peripherals active

IDX

3 +
1.1

CPU

RSTIN =

IH1

CPU

in [MHz]

Idle mode supply current
with all peripherals deactivated,
PLL off, SDD factor = 32

IDO

500 +
50

OSC

RSTIN =

IH1

OSC

in [MHz]

Power-down mode supply current
with RTC running

PDR

100 +
25

OSC

= 5.5 V

OSC

in [MHz]

Power-down mode supply current
with RTC disabled

PDO

= 5.5 V

Parameter

Symbol

Limit Values

Unit

Test Condition

min.

max.

Semiconductor Group

1998-05-01

C161RI

Notes

This specification is not valid for outputs which are switched to open drain mode. In this case the respective
output will float and the voltage results from the external circuitry.

The maximum current may be drawn while the respective signal line remains inactive.

The minimum current must be drawn in order to drive the respective signal line active.

This specification is only valid during Reset, or during Adapt-mode.

Not 100% tested, guaranteed by design characterization.

The supply current is a function of the operating frequency. This dependency is illustrated in the figure below.
These parameters are tested at

DDmax

and 20 MHz CPU clock with all outputs disconnected and all inputs at

The oscillator also contributes to the total supply current. The given values refer to the worst case, i.e.

PDRmax

For lower oscillator frequencies the respective supply current can be reduced accordingly.

This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to
0.1 V or at

0.1 V to

REF

= 0 V, all outputs (including pins configured as outputs) disconnected.

Overload conditions under operating conditions occur if the voltage on the respective pin exceeds the specified
operating range (i.e.

+ 0.5 V or

- 0.5 V). The absolute sum of input overload currents on

all port pins may not exceed 50 mA. The supply voltage (

and

) must remain within the specified limits.

This parameter is determined mainly by the current consumed by the oscillator. This current, however, is
influenced by the external oscillator circuitry (crystal, capacitors). The values given for

PDR

refer to a typical

circuitry and may change in case of a not optimized external oscillator circuitry.
A typical value for

PDR

at room temperature and

CPU

= 16 MHz is 300

Semiconductor Group

1998-05-01

C161RI

AC Characteristics
Definition of Internal Timing

The internal operation of the C161RI is controlled by the internal CPU clock

CPU

. Both edges of the

CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations.

The specification of the external timing (AC Characteristics) therefore depends on the time between
two consecutive edges of the CPU clock, called "TCL" (see figure below).

Figure 10
Generation Mechanisms for the CPU Clock

The CPU clock signal can be generated via different mechanisms. The duration of TCLs and their
variation (and also the derived external timing) depends on the used mechanism to generate

CPU

This influence must be regarded when calculating the timings for the C161RI.

The used mechanism to generate the CPU clock is selected during reset via the logic levels on pins
P0.15-13 (P0H.7-5).

TCL TCL

CPU

XTAL

Direct Clock Drive

TCL

CPU

XTAL

Prescaler Operation

Semiconductor Group

1998-05-01

C161RI

The table below associates the combinations of these three bits with the respective clock generation
mode.

The maximum frequency depends on the duty cycle of the external clock signal.

Prescaler Operation

When pins P0.15-13 (P0H.7-5) equal `001' during reset the CPU clock is derived from the internal
oscillator (input clock signal) by a 2:1 prescaler.
The frequency of

CPU

is half the frequency of

XTAL

and the high and low time of

CPU

(i.e. the duration

of an individual TCL) is defined by the period of the input clock

XTAL

The timings listed in the AC Characteristics that refer to TCLs therefore can be calculated using the
period of

XTAL

for any TCL.

Direct Drive

When pins P0.15-13 (P0H.7-5) equal `011' during reset the on-chip phase locked loop is disabled
and the CPU clock is directly driven from the internal oscillator with the input clock signal.
The frequency of

CPU

directly follows the frequency of

XTAL

so the high and low time of

CPU

(i.e. the

duration of an individual TCL) is defined by the duty cycle of the input clock

XTAL

The timings listed below that refer to TCLs therefore must be calculated using the minimum TCL
that is possible under the respective circumstances. This minimum value can be calculated via the
following formula:

TCL

min

= 1/

XTAL

min

(DC = duty cycle)

For two consecutive TCLs the deviation caused by the duty cycle of

XTAL

is compensated so the

duration of 2TCL is always 1/

XTAL

. The minimum value TCL

min

therefore has to be used only once

for timings that require an odd number of TCLs (1,3,...). Timings that require an even number of
TCLs (2,4,...) may use the formula 2TCL = 1/

XTAL

Note: The address float timings in Multiplexed bus mode (

and

) use the maximum duration of

TCL (TCL

max

= 1/

XTAL

max

) instead of TCL

min

C161RI Clock Generation Modes

P0.15-13

(P0H.7-5)

CPU Frequency

CPU

XTAL

Notes

Reserved

Default configuration without pull-downs

Reserved

XTAL

Direct drive

Reserved

XTAL

/ 2

CPU clock via prescaler

Reserved

Semiconductor Group

1998-05-01

C161RI

AC Characteristics
External Clock Drive XTAL1

= 4.5 - 5.5 V;

= 0 V

= 0 to + 70

for SAB-C161RI

= 40 to + 85

C for SAF-C161RI

The clock input signal must reach the defined levels

and

IH2

The specified minimum low and high times allow a duty cycle range of 40...60% at 16 MHz.

Figure 11
External Clock Drive XTAL1

Parameter

Symbol

Direct Drive 1:1

Prescaler 2:1

Unit

min.

max.

min.

max.

Oscillator period

OSC

8000

4000

High time

Low time

Rise time

Fall time

MCT02534

IH2

0.5

OSC

Semiconductor Group

1998-05-01

C161RI

A/D Converter Characteristics

= 4.5 - 5.5 V;

= 0 V

= 0 to + 70

for SAB-C161RI

= 40 to + 85

C for SAF-C161RI

4.0 V

AREF

+ 0.1 V;

- 0.1 V

AGND

+ 0.2 V

The conversion time of the C161RI's A/D Converter is programmable. The table below should be
used to calculate the above timings.
The limit values for

must not be exceeded when selecting ADCTC.

Converter Timing Example:

Assumptions:

CPU

= 16 MHz (i.e.

CPU

= 62.5 ns), ADCTC = `01'.

Basic clock

CPU

/ 4 = 4 MHz, i.e.

= 250 ns.

Sample time

6 = 1500 ns.

Conversion time

= 30

+ 2

CPU

= (7500 + 125) ns = 7.625

Parameter

Symbol

Limit Values

Unit

Test Condition

min.

max.

Analog input voltage range

AIN

AGND

AREF

Basic clock frequency

0.5

MHz

Sample time

= 1 /

Conversion time

+ 2

CPU

= 1 /

CPU

Total unadjusted error

TUE CC

LSB

Internal resistance of reference
voltage source

AREF

/ 125

- 0.25

in [ns]

Internal resistance of analog
source

ASRC

/ 750

- 0.25

in [ns]

ADC input capacitance

AIN

ADCON.15|14
(ADCTC)

A/D Converter Basic Clock

CPU

/ 2

CPU

/ 4

CPU

/ 8

CPU

/ 16

Semiconductor Group

1998-05-01

C161RI

Notes

AIN

may exceed

AGND

AREF

up to the absolute maximum ratings. However, the conversion result in these

cases will be X000

or X3FF

, respectively.

The limit values for

must not be exceeded when selecting the CPU frequency and the ADCTC setting.

This parameter includes the sample time

, the time for determining the digital result and the time to load the

result register with the conversion result.
Values for the basic clock

depend on programming and can be taken from the table above.

This parameter depends on the ADC control logic. It is not a real maximum value, but rather a fixum.

TUE is tested at

AREF

= 5.0 V,

AGND

= 0 V,

= 4.9 V. It is guaranteed by design for all other voltages within

the defined voltage range.
The specified TUE is guaranteed only if an overload condition (see

specification) occurs on maximum 2 not

selected analog input pins and the absolute sum of input overload currents on all analog input pins does not
exceed 10 mA.

During the conversion the ADC's capacitance must be repeatedly charged or discharged. The internal
resistance of the reference voltage source must allow the capacitance to reach its respective voltage level
within each conversion step. The maximum internal resistance results from the programmed conversion
timing.

Not 100% tested, guaranteed by design.

During the sample time the input capacitance

can be charged/discharged by the external source. The

internal resistance of the analog source must allow the capacitance to reach its final voltage level within

After the end of the sample time

, changes of the analog input voltage have no effect on the conversion result.

Values for the sample time

depend on programming and can be taken from the table above.

Semiconductor Group

1998-05-01

C161RI

Memory Cycle Variables

The timing tables below use three variables which are derived from the BUSCONx registers and
represent the special characteristics of the programmed memory cycle. The following table
describes, how these variables are to be computed.

AC Characteristics
Multiplexed Bus

= 4.5 - 5.5 V;

= 0 V

= 0 to + 70

for SAB-C161RI

= 40 to + 85

C for SAF-C161RI

= 100 pF

ALE cycle time = 6 TCL + 2

(186 ns at 16 MHz CPU clock without waitstates)

Description

Symbol

Values

ALE Extension

TCL

Memory Cycle Time Waitstates

2TCL

(15 - <MCTC>)

Memory Tristate Time

2TCL

(1 - <MTTC>)

Parameter

Symbol

Max. CPU Clock

= 16 MHz

Variable CPU Clock

1/2TCL = 1 to 16 MHz

Unit

min.

max.

min.

max.

ALE high time

21 +

TCL - 10 +

Address setup to ALE

15 +

TCL - 16 +

Address hold after ALE

21 +

TCL - 10 +

ALE falling edge to RD,
WR (with RW-delay)

21 +

TCL - 10 +

ALE falling edge to RD,
WR (no RW-delay)

10 +

Address float after RD,
WR (with RW-delay)

Address float after RD,
WR (no RW-delay)

TCL + 6

RD, WR low time
(with RW-delay)

53 +

2TCL - 10
+

RD, WR low time
(no RW-delay)

84 +

3TCL - 10
+

Semiconductor Group

1998-05-01

C161RI

RD to valid data in
(with RW-delay)

43 +

2TCL - 20
+

RD to valid data in
(no RW-delay)

74 +

3TCL - 20
+

ALE low to valid data in

74
+

3TCL - 20
+

Address to valid data in

95
+

4TCL - 30
+

Data hold after RD
rising edge

Data float after RD

49 +

2TCL - 14
+

Data valid to WR

43 +

2TCL - 20
+

Data hold after WR

49 +

2TCL - 14
+

ALE rising edge after RD,
WR

49 +

2TCL - 14
+

Address hold after RD,
WR

49 +

2TCL - 14
+

ALE falling edge to CS

4 -

10 -

4 -

10 -

CS low to Valid Data In

74
+

3TCL - 20
+

CS hold after RD, WR

80 +

3TCL - 14
+

ALE fall. edge to RdCS,
WrCS (with RW delay)

27 +

TCL - 4
+

ALE fall. edge to RdCS,
WrCS (no RW delay)

4 +

-4
+

Address float after RdCS,
WrCS (with RW delay)

Address float after RdCS,
WrCS (no RW delay)

TCL

RdCS to Valid Data In
(with RW delay)

39 +

2TCL - 24
+

Parameter

Symbol

Max. CPU Clock

= 16 MHz

Variable CPU Clock

1/2TCL = 1 to 16 MHz

Unit

min.

max.

min.

max.

Semiconductor Group

1998-05-01

C161RI

RdCS to Valid Data In
(no RW delay)

70 +

3TCL - 24
+

RdCS, WrCS Low Time
(with RW delay)

53 +

2TCL - 10
+

RdCS, WrCS Low Time
(no RW delay)

84 +

3TCL - 10
+

Data valid to WrCS

49 +

2TCL - 14
+

Data hold after RdCS

Data float after RdCS

43 +

2TCL - 20
+

Address hold after
RdCS, WrCS

43 +

2TCL - 20
+

Data hold after WrCS

43 +

2TCL - 20
+

Parameter

Symbol

Max. CPU Clock

= 16 MHz

Variable CPU Clock

1/2TCL = 1 to 16 MHz

Unit

min.

max.

min.

max.

Semiconductor Group

1998-05-01

C161RI

AC Characteristics
Demultiplexed Bus

= 4.5 - 5.5 V;

= 0 V

= 0 to + 70

for SAB-C161RI

= 40 to + 85

C for SAF-C161RI

= 100 pF

ALE cycle time = 4 TCL + 2

(125 ns at 16 MHz CPU clock without waitstates)

Parameter

Symbol

Max. CPU Clock

= 16 MHz

Variable CPU Clock

1/2TCL = 1 to 16 MHz

Unit

min.

max.

min.

max.

ALE high time

21 +

TCL - 10 +

Address setup to ALE

15 +

TCL - 16 +

ALE falling edge to RD,
WR (with RW-delay)

21 +

TCL - 10
+

ALE falling edge to RD,
WR (no RW-delay)

10 +

10
+

RD, WR low time
(with RW-delay)

53 +

2TCL - 10
+

RD, WR low time
(no RW-delay)

84 +

3TCL - 10
+

RD to valid data in
(with RW-delay)

43 +

2TCL - 20
+

RD to valid data in
(no RW-delay)

74 +

3TCL - 20
+

ALE low to valid data in

74
+

3TCL - 20
+

Address to valid data in

95
+

4TCL - 30
+

Data hold after RD
rising edge

Data float after RD rising
edge (with RW-delay

)

49 +
2

2TCL - 14
+

Data float after RD rising
edge (no RW-delay

)

21 +
2

TCL - 10
+

Data valid to WR

43 +

2TCL - 20
+

Data hold after WR

21 +

TCL - 10 +

ALE rising edge after RD,
WR

10 +

Semiconductor Group

1998-05-01

C161RI

RW-delay and

refer to the next following bus cycle.

It is guaranteed by design that read data are latched before the address changes.

Address hold after WR

0 +

ALE falling edge to CS

4 -

10 -

4 -

10 -

CS low to Valid Data In

74
+

3TCL - 20
+

CS hold after RD, WR

17 +

TCL - 14
+

ALE falling edge to RdCS,
WrCS (with RW-delay)

27 +

TCL - 4
+

ALE falling edge to RdCS,
WrCS (no RW-delay)

4 +

4
+

RdCS to Valid Data In
(with RW-delay)

39 +

2TCL - 24
+

RdCS to Valid Data In
(no RW-delay)

70 +

3TCL - 24
+

RdCS, WrCS Low Time
(with RW-delay)

53 +

2TCL - 10
+

RdCS, WrCS Low Time
(no RW-delay)

84 +

3TCL - 10
+

Data valid to WrCS

49 +

2TCL - 14
+

Data hold after RdCS

Data float after RdCS
(with RW-delay)

43 +

2TCL - 20
+

Data float after RdCS
(no RW-delay)

11 +

TCL - 20
+

Address hold after
RdCS, WrCS

10 +

10
+

Data hold after WrCS

17 +

TCL - 14
+

Parameter

Symbol

Max. CPU Clock

= 16 MHz

Variable CPU Clock

1/2TCL = 1 to 16 MHz

Unit

min.

max.

min.

max.

Semiconductor Group

1998-05-01

C161RI

AC Characteristics
CLKOUT and READY

= 4.5 - 5.5 V;

= 0 V

= 0 to + 70

for SAB-C161RI

= 40 to + 85

C for SAF-C161RI

= 100 pF

Notes

These timings are given for test purposes only, in order to assure recognition at a specific clock edge.

Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This
adds even more time for deactivating READY.
The 2t

and

refer to the next following bus cycle,

refers to the current bus cycle.

Parameter

Symbol

Max. CPU Clock

= 16 MHz

Variable CPU Clock

1/2TCL = 1 to 16 MHz

Unit

min.

max.

min.

max.

CLKOUT cycle time

2TCL

CLKOUT high time

TCL 6

CLKOUT low time

TCL 10

CLKOUT rise time

CLKOUT fall time

CLKOUT rising edge to
ALE falling edge

0 +

10 +

0 +

10 +

Synchronous READY
setup time to CLKOUT

Synchronous READY
hold time after CLKOUT

Asynchronous READY
low time

2TCL + 14

Asynchronous READY
setup time

Asynchronous READY
hold time

Async. READY hold time
after RD, WR high
(Demultiplexed Bus)

1
+ 2

TCL - 30
+

Semiconductor Group

1998-05-01

C161RI

Figure 16
CLKOUT and READY

Notes

Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS).

The leading edge of the respective command depends on RW-delay.

READY sampled HIGH at this sampling point generates a READY controlled waitstate,
READY sampled LOW at this sampling point terminates the currently running bus cycle.

READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or
WR).

If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT
(eg. because CLKOUT is not enabled), it must fulfill

in order to be safely synchronized. This is guaranteed,

if READY is removed in reponse to the command (see Note

Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may
be inserted here.
For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without
MTTC waitstate this delay is zero.

The next external bus cycle may start here.

CLKOUT

ALE

Sync

READY

Async

READY

waitstate

READY

MUX/Tristate

Running cycle

Command

RD, WR

see

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