Semiconductor Group

09.96

C509-L

8-Bit CMOS Microcontroller

Advance Information

C509-L

Full upward compatibility with SAB 80C517/80C517A and 8051/C501 microcontrollers

256 byte on-chip RAM

3K byte of on-chip XRAM

256 directly addressable bits

375 ns instruction cycle at 16-MHz oscillator frequency

On-chip emulation support logic (Enhanced Hooks Technology

)

External program and data memory expandable up to 64 Kbyte each

8-bit A/D converter with 15 multiplexed inputs and built-in self calibration

Two 16-bit timers/counters (8051 compatible)

Three 16-bit timers/counters (can be used in combination with the compare/capture unit)

Powerful compare/capture unit (CCU) with up to 29 high-speed or PWM output channels or 13
capture inputs

Arithmetic unit for division, multiplication, shift and normalize operations

Eight datapointers instead of one for indirect addressing of program and external data memory

(further features are on next page)

Figure 1
C509-L Functional Units

C509-L

Semiconductor Group

Features (continued) :

Extended watchdog facilities
15-bit programmable watchdog timer
Oscillator watchdog

Ten I/O ports
Eight bidirectional 8-bit I/O ports with selectable port structure

quasi-bidirectional port structure (8051 compatible)
bidirectional port structure with CMOS voltage levels

One 8-bit and one 7-bit input port for analog and digital input signals

Two full-duplex serial interfaces with own baud rate generators

Four priority level interrupt systems, 19 interrupt vectors

Three power saving modes
Slow-down mode
Idle mode
Power-down mode

Siemens high-performance ACMOS technology

M-QFP-100-2 rectangular quad flat package

Temperature Ranges :

SAB-C509-L

= 0 to 70

SAF-C509-L

= -40 to 85

The C509-L is a high-end microcontroller in the Siemens C500 8-bit microcontroller family. lt is
based on the well-known industry standard 8051 architecture; a great number of enhancements
and new peripheral features extend its capabilities to meet the extensive requirements of new
applications. Further, the C509-L is a superset of the Siemens SAB 80C517/80C517A 8-bit
microcontroller thus offering an easy upgrade path for SAB 80C517/80C517A users.

The high performance of the C509-L microcontroller is achieved by the C500-Core with a maximum
operating frequency of 16 MHz internal (and external) CPU clock. While maintaining all the features
of the SAB 80C517A, the C509-L is expanded by one I/O port, in its compare/capture capabilities,
by A/D converter functions, by additional 1 KByte of on-chip RAM (now 3 KByte XRAM) and by an
additional user-selectable CMOS port structure. The C509-L is mounted in a P-MQFP-100-2
package.

Note: Versions for extended temperature ranges 40 °C to 110 °C (SAH-C509-L) and 40 °C to

125 °C (SAK-C509-L) are available on request.

Ordering Information

Type Ordering

Code

Package

Description
(8-Bit CMOS microcontroller)

SAB-C509-LM

Q67120-C1045

P-MQFP-100-2

for external memory (16 MHz)

SAF-C509-LM

Q67120-C0983

P-MQFP-100-2

for external memory (16 MHz)
ext. temp. 40 °C to 85 °C

Semiconductor Group

09.96

C509-L

Table 1
Pin Definitions and Functions

Symbol

Pin Number

I/O*)

Function

P1.0 - P1.7

9-6, 1,
100-98

100
99
98

I/O

Port 1
is an 8-bit quasi-bidirectional I/O port with internal pullup
resistors. Port 1 pins that have 1's written to them are
pulled high by the internal pullup resistors, and in that
state can be used as inputs. As inputs, port 1 pins being
externally pulled low will source current (

, in the DC

characteristics) because of the internal pullup resistors.
Port 1 can also be switched into a bidirectional mode, in
which CMOS levels are provided. In this bidirectional
mode, each port 1 pin can be programmed individually
as input or output.
Port 1 also contains the interrupt, timer, clock, capture
and compare pins that are used by various options. The
output latch corresponding to a secondary function must
be programmed to a one (1) for that function to operate
(except when used for the compare functions).
The secondary functions are assigned to the pins of
port 1 as follows :
P1.0

INT3 CC0

Interrupt 3 input / compare 0 output /
capture 0 input

P1.1

INT4 CC1

Interrupt 4 input / compare 1 output /
capture 1 input

P1.2

INT5 CC2

Interrupt 5 input / compare 2 output /
capture 2 input

P1.3

INT6 CC3

Interrupt 6 input / compare 3 output /
capture 3 input

P1.4

INT2 CC4

Interrupt 2 input / compare 4 output /
capture 4 input

P1.5

T2EX

Timer 2 external reload trigger input

P1.6

CLKOUT

System clock output

P1.7

Counter 2 input

*) I = Input

O = Output

C509-L

Semiconductor Group

P9.0 - P9.7

74-77,
5-2

I/O

Port 9
is an 8-bit quasi-bidirectional I/O port with internal pullup
resistors. Port 9 pins that have 1's written to them are
pulled high by the internal pullup resistors, and in that
state can be used as inputs. As inputs, port 9 pins being
externally pulled low will source current (

, in the DC

characteristics) because of the internal pullup resistors.
Port 9 can also be switched into a bidirectional mode, in
which CMOS levels are provided. In this bidirectional
mode, each port 1 pin can be programmed individually
as input or output.
Port 9 also serves alternate compare functions. The out-
put latch corresponding to a secondary function must be
programmed to a one (1) for that function to operate.
The secondary functions are assigned to the pins of
port 9 as follows :
P9.0-P9.7 CC10-CC17

Compare/capture channel 0-7
output/input

XTAL2

XTAL2
is the input to the inverting oscillator amplifier and input
to the internal clock generator circuits.
When supplying the C509-L with an external clock
source, XTAL2 should be driven, while XTAL1 is left
unconnected. A duty cycle of 0.4 to 0.6 of the clock
signal is required. Minimum and maximum high and low
times as well as rise/fall times specified in the AC
characteristics must be observed.

XTAL1

XTAL1
Output of the inverting oscillator amplifier. This pin is
used for the oscillator operation with crystal or ceramic
resonartor

*) I = Input

O = Output

Table 1
Pin Definitions and Functions (cont'd)

Symbol

Pin Number

I/O*)

Function

Semiconductor Group

09.96

C509-L

P2.0 P2.7

14-21

I/O

Port 2
is a 8-bit I/O port. Port 2 emits the high-order address
byte during fetches from external program memory and
during accesses to external data memory that use 16-bit
addresses (MOVX @DPTR). In this application it uses
strong internal pullup resistors when issuing 1s. During
accesses to external data memory that use 8-bit
addresses (MOVX @Ri), port 2 issues the contents of the
P2 special function register.
P2.0 - P2.7

A8 - A15

Address lines 8 - 15

PSEN / RDF

Program Store Enable / Read FLASH
The PSEN output is a control signal that enables the
external program memory to the bus during external
code fetch operations. It is activated every third
oscillator period. PSEN is not activated during external
data memory accesses caused by MOVX instructions.
PSEN is not activated when instructions are executed
from the internal Boot ROM or from the XRAM.
In external programming mode RDF becomes active
when executing external data memory read (MOVX)
instructions.

ALE

Address Latch Enable
This output is used for latching the low byte of the
address into external memory during normal operation.
It is activated every third oscillator period except during
an external data memory access caused by MOVX
instructions.

External Access Enable
The status of this pin is latched at the end of a reset.
When held at low level, the C509-L fetches all
instructions from the external program memory. For the
C509-L this pin must be tied low.

PRGEN

External Flash-EPROM Program Enable
A low level at this pin disables the programming of an
external Flash-EPROM. To enable the programming of
an external Flash-EPROM, the pin PRGEN must be held
at high level and bit PRGEN1 in SFR SYSCON1 has to
be set. There is no internal pullup resistor connected to
this pin.

*) I = Input

O = Output

Table 1
Pin Definitions and Functions (cont'd)

Symbol

Pin Number

I/O*)

Function

C509-L

Semiconductor Group

P0.0 P0.7

26, 27,
30-35

I/O

Port 0
is an 8-bit open-drain bidirectional I/O port. Port 0 pins
that have 1s written to them float, and in that state can be
used as high-impendance inputs. Port 0 is also the
multiplexed low-order address and data bus during
accesses to external program or data memory. In this
operating mode it uses strong internal pullup resistors
when issuing 1 s.
P0.0 - P0.7

AD0-AD7

Address/data lines 0 - 7

HWPD

Hardware Power Down
A low level on this pin for the duration of one machine
cycle while the oscillator is running resets the C509-L.
A low level for a longer period will force the part to power
down mode with the pins floating. There is no internal
pullup resistor connected to this pin.

P5.0 - P5.7

44-37

I/O

Port 5
is an 8-bit quasi-bidirectional I/O port with internal pullup
resistors. Port 5 pins that have 1's written to them are
pulled high by the internal pullup resistors, and in that
state can be used as inputs. As inputs, port 5 pins being
externally pulled low will source current (

, in the DC

characteristics) because of the internal pullup resistors.
Port 5 can also be switched into a bidirectional mode, in
which CMOS levels are provided. In this bidirectional
mode, each port 5 pin can be programmed individually
as input or output.
Port 5 also serves as alternate function for "Concurrent
Compare" and "Set/Reset compare" functions. The
output latch corresponding to a secondary function must
be programmed to a one (1) for that function to operate.
The secondary functions are assigned to the pins of port
5 as follows :
P5.0 - P5.7

CCM0-CCM7

Concurrent Compare
or Set/Reset lines 0 - 7

*) I = Input

O = Output

Table 1
Pin Definitions and Functions (cont'd)

Symbol

Pin Number

I/O*)

Function

Semiconductor Group

09.96

C509-L

OWE

Oscillator Watchdog Enable
A high level on this pin enables the oscillator watchdog.
When left unconnected, this pin is pulled high by a weak
internal pullup resistor. The logic level at OWE should
not be changed during normal operation. When held at
low level the oscillator watchdog function is turned off.
During hardware power down the pullup resistor is
switched off.

P6.0 - P6.7

46-50,
54-56

46
47
48

I/O

Port 6
is an 8-bit quasi-bidirectional I/O port with internal pullup
resistors. Port 6 pins that have 1's written to them are
pulled high by the internal pullup resistors, and in that
state can be used as inputs. As inputs, port 6 pins being
externally pulled low will source current (

, in the DC

characteristics) because of the internal pullup resistors.
Port 6 can also be switched into a bidirectional mode, in
which CMOS levels are provided. In this bidirectional
mode, each port 6 pin can be programmed individually
as input or output.
Port 6 also contains the external A/D converter control
pin, the receive and transmission lines for the serial port
1, and the write-FLASH control signal. The output latch
corresponding to a secondary function must be
programmed to a one (1) for that function to operate.
The secondary functions are assigned to the pins of
port 6 as follows :
P6.0

ADST External A/D converter start pin

P6.1

Receiver data input of serial interface 1

P6.2

Transmitter data output of serial
interface 1

P6.3

WRF

The WRF (write Flash) signal is active
when the programming mode is
selected. In this mode WRF becomes
active when executing external data
memory write (MOVX) instructions.

*) I = Input

O = Output

Table 1
Pin Definitions and Functions (cont'd)

Symbol

Pin Number

I/O*)

Function

C509-L

Semiconductor Group

P8.0 - P8.6

57-60,
51-53

Port 8
is a 7-bit unidirectional input port. Port pins can be used
for digital input if voltage levels meet the specified input
high/low voltages, and for the higher 7-bit of the
multiplexed analog inputs of the A/D converter
simultaneously.
P8.0 - P8.6

AIN8 - AIN14

Analog input 8 - 14

Reset Output
This pin outputs the internally synchronized reset
request signal. This signal may be generated by an
external hardware reset, a watchdog timer reset or an
oscillator watchdog reset. The RO output is active low.

P4.0 P4.7

64-66,
68-72

I/O

Port 4
is an 8-bit quasi-bidirectional I/O port with internal pull-up
resistors. Port 4 pins that have 1's written to them are
pulled high by the internal pull-up resistors, and in that
state can be used as inputs. As inputs, port 4 pins being
externally pulled low will source current (

, in the DC

characteristics) because of the internal pull-up resistors.
Port 4 also erves as alternate compare functions. The
output latch corresponding to a secondary functionmust
be programmed to a one (1) for that function to operate.
The secondary functions are assigned to the pins of port
4 as follows :
P4.0 - P4.7

CM0 - CM7

Compare channel 0 - 7

PE / SWD

Power Saving Modes Enable / Start Watchdog Timer
A low level on this pin allows the software to enter the
power down mode, idle and slow down mode. If the low
level is also seen during reset, the watchdog timer
function is off on default.
Usage of the software controlled power saving modes is
blocked, when this pin is held on high level. A high level
during reset performs an automatic start of the watchdog
timer immediately after reset.
When left unconnected this pin is pulled high by a weak
internal pullup resistor. During hardware power down the
pullup resistor is switched off.

*) I = Input

O = Output

Table 1
Pin Definitions and Functions (cont'd)

Symbol

Pin Number

I/O*)

Function

Semiconductor Group

09.96

C509-L

RESET

RESET
A low level on this pin for the duration of one machine
cycle while the oscillator is running resets the C509-L. A
small internal pullup resistor permits power-on reset
using only a capacitor connected to

AREF

Reference voltage for the A/D converter

AGND

Reference ground for the A/D converter

P7.0 - P7.7

87-80

Port 7
Port 7 is an 8-bit unidirectional input port. Port pins can
be used for digital input if voltage levels meet the
specified input high/low voltages, and for the lower 8-bit
of the multiplexed analog inputs of the A/D converter
simultaneously.
P7.0 - P7.7

AIN0 - AIN7

Analog input 0 - 7

*) I = Input

O = Output

Table 1
Pin Definitions and Functions (cont'd)

Symbol

Pin Number

I/O*)

Function

C509-L

Semiconductor Group

P3.0 P3.7

90-97

92
93
94
95
96

I/O

Port 3
is an 8-bit quasi-bidirectional I/O port with internal pullup
resistors. Port 3 pins that have 1's written to them are
pulled high by the internal pullup resistors, and in that
state can be used as inputs. As inputs, port 3 pins being
externally pulled low will source current (

, in the DC

characteristics) because of the internal pullup resistors.
Port 3 also contains two external interrupt inputs, the
timer 0/1 inputs, the serial port 0 receive/transmit line
and the external memory strobe pins. The output latch
corresponding to a secondary function must be
programmed to a one (1) for that function to operate.
The secondary functions are assigned to the port pins of
port 3 as follows
P3.0

Receiver data input (asynchronous) or
data input/output (synchronous) of serial
interface 0

P3.1

Transmitter data output (asynchronous)
or clock output (synchronous) of the
serial interface 0

P3.2

INT0

Interrupt 0 input / timer 0 gate control

P3.3

INT1

Interrupt 1 input / timer 1 gate control

P3.4

Counter 0 input

P3.5

Counter 1 input

P3.6

The write control signal latches the data
byte from port 0 into the external data
memory

P3.7

RD /

The read control signal enables the
external data memory to port 0

PSENX PSENX (external program store enable)

enables the external code memory
when the external / internal XRAM
mode or external / internal programming
mode is selected.

10, 28, 62, 88

Circuit ground potential

11, 29, 63, 89

Supply terminal for all operating modes

*) I = Input

O = Output

Table 1
Pin Definitions and Functions (cont'd)

Symbol

Pin Number

I/O*)

Function

C509-L

Semiconductor Group

CPU

The C509-L is efficient both as a controller and as an arithmetic processor. It has extensive facilities
for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program
memory results from an instruction set consisting of 44 % one-byte, 41 % two-byte, and 15% three-
byte instructions. With a 6 MHz crystal, 58% of the instructions are executed in 1.0

(

12 MHz: 500

ns, 16 MHz : 375 ns).

Special Function Register PSW (Address D0H)

Reset Value : 00H

Bit

Function

Carry Flag
Used by arithmetic instruction.

Auxiliary Carry Flag
Used by instructions which execute BCD operations.

General Purpose Flag

RS1
RS0

Overflow Flag
Used by arithmetic instruction.

General Purpose Flag

Parity Flag
Set/cleared by hardware after each instruction to indicate an odd/even
number of "one" bits in the accumulator, i.e. even parity.

RS1

RS0

D0H

PSW

D7H

D6H

D5H

D4H

D3H

D2H

D1H

D0H

Bit No.

MSB

LSB

RS1

RS0

Function

Bank 0 selected, data address 00H-07H

Bank 1 selected, data address 08H-0FH

Bank 2 selected, data address 10H-17H

Bank 3 selected, data address 18H-1FH

Semiconductor Group

09.96

C509-L

Memory Organization

The C509-L CPU manipulates data and operands in the following five address spaces:

up to 64 Kbyte of external program memory
up to 64 Kbyte of external data memory
512 byte of internal Boot ROM (program memory)
256 bytes of internal data memory
3 Kbyte of external XRAM data memory
a 128 byte special function register area

Figure 5 illustrates the memory address spaces of the C509-L.

Figure 5
C509-L Memory Map

The C509-L can operate in four different operating modes (chipmodes) with different program and
data memory organizations :

Normal Mode
XRAM Mode
Bootstrap Mode
Programming Mode

Table 2 describes the program and data memory areas which are available in the different
chipmodes of the C509-L. It also shows the control bits of SFR SYSCON1, which are used for the
software selection of the chipmodes. Figures 6 to 9 shows the four chipmode configurations with
the code and data memory partitioning.

C509-L

Semiconductor Group

Programming Mode Configuration

The External Programming Mode is implemented for the in-circuit programming of external 5V-only
FLASH EPROMs. Similar as in the XRAM mode, the Boot ROM, the XRAM, and the external data
memory (SRAM) are mapped into the code memory area, while the external FLASH memory is
mapped into the external data memory area. Additionally to the XRAM mode, the FLASH memory
can also be written through external data memory accesses (MOVX instructions). External program
memory fetches from the SRAM are controlled by the P3.7/RD/PSENX pin. External data memory
read/write accesses from/to the ROM/EPROM are controlled by the PSEN/RDF and P6.3/WRF pin.

Figure 9
Locations of Code- and Data Memory in Programming Mode

Semiconductor Group

09.96

C509-L

The Bootstrap Loader

The C509-L includes a bootstrap mode, which is activated by setting the PRGEN pin at logic high
level at the rising edge of the RESET or the HWPD signal (bit PRGEN1=1). In this mode software
routines of the bootstrap loader, located at the addresses 0000H to 01FFH in the boot ROM will be
executed. Its purpose is to allow the easy and quick programming of the internal XRAM (F400H to
FFFFH) via serial interface while the MCU is in-circuit. This allows to transfer custom routines to the
XRAM, which will program an external 64 KByte FLASH memory. The serial routines of the
bootstrap loader may be replaced by own custom software or even can be blocked to prevent
unauthorized persons from reading out or writing to the external FLASH memory. Therefore the
bootstrap loader checks an external FLASH memory for existing custom software and executes it.

The bootstrap loader consists of three functional parts which represent the three phases as
described below.

Phase I : Check for existing custom software in the external FLASH memory and execute it.

Phase II : Establish a serial connection and automatically synchronize to the transfer speed (baud

rate) of the serial communication partner (host).

Phase III : Perform the serial communication to the host. The host controls the bootstrap loader by

sending header informations, which select one of four operating modes. These modes
are :

Mode 0 : Transfer a custom program from the host to the XRAM (F400H - FFFFH).

This mode returns to the beginning of phase III.

Mode 1 : Execute a custom program in the XRAM at any start address from F400H to

FFFFH.

Mode 2 : Check the contents of any area of the external FLASH memory by cal-

culating a checksum. This mode returns to the beginning of phase III.

Mode 3 : Execute a custom program in the FLASH memory at any start address

beyond 0200H (at addresses 0000H to 01FFH the boot-ROM is active).

The three phases of the bootstrap loader program and their connections are illustrated in figure 10.

Semiconductor Group

09.96

C509-L

Control of XRAM Access

The XRAM in the C509-L is a memory area that is logically located at the upper end of the external
memory space, but is integrated on the chip. Because the XRAM is used in the same way as
external data memory the same instruction types (MOVX) must be used for accessing the XRAM.
Two bits in SFR SYSCON, XMAP0 and XMAP1, control the accesses to the XRAM.

Special Function Register SYSCON (Address B1H)

Reset Value : 1010XX01B

Bit XMAP0 is hardware protected. If it is reset once (XRAM access enabled) it cannot be set by
software. Only a reset operation will set the XMAP0 bit again.

The XRAM can be accessed by read/write instructions (MOVX A,DPTR, MOVX @DPTR,A), which
use the 16-bit DPTR for indirect addressing. For accessing the XRAM, the effective address stored
in DPTR must be in the range of F700H to FFFFH.38
The XRAM can be also accessed by read/write instructions (MOVX A,@Ri, MOVX @Ri,A), which
use only an 8-bit address (indirect addressing with registers R0 or R1). Therefore, a special page
register XPAGE which provides the upper address information (A8-A15) during 8-bit XRAM
accesses.

The behaviour of Port 0 and P2 during a MOVX access depends on the control bits XMAP0 and
XMAP1 in register SYSCON and on the state of pin EA. Table 3 lists the various operating
conditions.

Bit

Function

XMAP1

XRAM visible access control
Control bit for RD/WR signals during XRAMaccesses. If addresses are
outside the XRAM address range or if XRAM is disabled, this bit has no
effect.
XMAP1 = 0 : The signals RD and WR are not activated during accesses to

the XRAM

XMAP1 = 1 : Ports 0, 2 and the signals RD and WR are activated during

accesses to XRAM. In this mode, address and data
information during XRAM/CAN Controller accesses are
visible externally.

XMAP0

Global XRAM access enable/disable control
XMAP0 = 0 : The access to XRAM is enabled.
XMAP0 = 1 : The access to XRAM is disabled (default after reset!).

All MOVX accesses are performed via the external bus.
Further, this bit is hardware protected.

RMAP

B1H

SYSCON

Bit No.

MSB

LSB

XMAP1

CLKP

PMOD

XMAP0

The functions of the shaded bits are not used for XRAM control.

C509-L

Semiconductor Group

Table 3
Behaviour of P0/P2 and RD/WR During MOVX Accesses

EA = 0

EA = 1

XMAP1, XMAP0

MOVX
@DPTR

DPTR
<
XRAM
address
range

a)P0/P2

Bus

b)RD/WR active
c)ext.memory
is used

a)P0/P2

Bus

b)RD/WR active
c)ext.memory
is used

a)P0/P2

Bus

b)RD/WR active
c)ext.memory
is used

a)P0/P2

Bus

b)RD/WR active
c)ext.memory
is used

a)P0/P2

Bus

b)RD/WR active
c)ext.memory
is used

a)P0/P2

Bus

b)RD/WR active
c)ext.memory
is used

DPTR

XRAM
address
range

a)P0/P2

Bus

(WR / RD Data)
b)RD/WR
inactive
c)XRAM is used

a)P0/P2

Bus

(WR / RD Data)
b)RD/WR active
c)XRAM is used

a)P0/P2

Bus

b)RD/WR active
c) ext.memory
is used

a)P0/P2

I/0

b)RD/WR
inactive
c)XRAM is used

a)P0/P2

Bus

(WR / RD Data)
b)RD/WR active
c)XRAM is used

a)P0/P2

Bus

b)RD/WR active
c) ext.memory
is used

MOVX
@ Ri

XPAGE
<
XRAM
addr.page
range

a)P0

Bus

b)RD/WR active
c)ext.memory
is used

a)P0

Bus

b)RD/WR active
c)ext.memory
is used

a)P0

Bus

b)RD/WR active
c)ext.memory
is used

a)P0

Bus

b)RD/WR active
c)ext.memory
is used

a)P0

Bus

b)RD/WR active
c)ext.memory
is used

a)P0

Bus

b)RD/WR active
c)ext.memory
is used

XPAGE

XRAM
addr.page
range

a)P0

Bus

(WR / RD Data)
P2

b)RD/WR
inactive
c)XRAM is used

a)P0

Bus

(WR / RD Data)
P2

b)RD/WR active

c)XRAM is used

a)P0

Bus

b)RD/WR active

c)ext.memory
is used

a)P2

P0/P2

b)RD/WR
inactive
c)XRAM is used

a)P0

Bus

(WR / RD Data)
P2

b)RD/WR active

c)XRAM is used

a)P0

Bus

b)RD/WR active

c)ext.memory
is used

modes compatible to 8051/C501 family

Semiconductor Group

09.96

C509-L

Enhanced Hooks Emulation Concept

The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative
way to control the execution of C500 MCUs and to gain extensive information on the internal
operation of the controllers. Emulation of on-chip ROM based programs is possible, too (not true for
the C509-L, because it lacks internal program memory).
Each production chip has built-in logic for the supprt of the Enhanced Hooks Emulation Concept.
Therefore, no costly bond-out chips are necessary for emulation. This also ensure that emulation
and production chips are identical.

The Enhanced Hooks Technology

, which requires embedded logic in the C500 allows the C500

together with an EH-IC to function similar to a bond-out chip. This simplifies the design and reduces
costs of an ICE-system. ICE-systems using an EH-IC and a compatible C500 are able to emulate
all operating modes of the different versions of the C500 microcontrollers. This includes emulation
of ROM, ROM with code rollover and ROMless modes of operation. It is also able to operate in
single step mode and to read the SFRs after a break.

Figure 15
Basic C500 MCU Enhanced Hooks Concept Configuration

Port 0, port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks
Emulation Concept to control the operation of the device during emulation and to transfer
informations about the programm execution and data transfer between the external emulation
hardware (ICE-system) and the C500 MCU.

C509-L

Semiconductor Group

Special Function Registers

All registers, except the program counter and the four general purpose register banks, reside in the
special function register area. Several special function registers of the C509-L (CC10-17, CT1REL,
CC1EN, CAFR) are located in the mapped special function register area. For accessing the mapped
special function register area, bit RMAP in special function register SYSCON must be set. All other
special function registers are located in the standard special function register area. As long as bit
RMAP is set, mapped special function registers can be accessed. This bit is not cleared by
hardware automatically.

Special Function Register SYSCON (Address B1H)

Reset Value : 1010XX01B

The 103 special function register (SFR) include pointers and registers that provide an interface
between the CPU and the other on-chip peripherals. The SFRs of the C509-L are listed in table 4
and table 5. In table 4 they are organized in groups which refer to the functional blocks of the C509-
L. Table 5 illustrates the contents of the SFRs in numeric order of their addresses. The most right
column of table 5 indicates if an SFR is accessed with a mapped procedure controlled by either
RMAP or PDIR.

Bit

Function

RMAP

Special function register map bit
RMAP = 0 : The access to the non-mapped (standard) special function

RMAP = 1 : The access to the mapped special function register area is

enabled.

RMAP

B1H

SYSCON

Bit No.

MSB

LSB

XMAP1

CLKP

PMOD

XMAP0

Semiconductor Group

09.96

C509-L

Table 4
Special Function Registers - Functional Blocks

Block

Symbol

Name

Address

Contents after
Reset

CPU

ACC
B
DPH
DPL
DPSEL
PSW
SP
SYSCON1

Accumulator
B-Register
Data Pointer, High Byte
Data Pointer, Low Byte
Data Pointer Select Register
Program Status Word
Stack Pointer
System Control Register 1

E0H

)

F0H

)

83H
82H
92H
D0H

)

81H
B2H

00H
00H
00H
00H
XXXXX000B

00H
07H
00XXXEE0B

3)6)

SFR
Mapping

SYSCON

System Control Register

B1H

1010XX01B

Interrupt
System

IEN0
CTCON

CT1CON

IEN1

IEN2

IEN3
IP0

IP1

IRCON0
IRCON1
IRCON2

EICC1

TCON

T2CON

Interrupt Enable Register 0
Compare Timer Control Register
Compare Timer 1 Control Register
Interrupt Enable Register 1
Interrupt Enable Register 2
Interrupt Enable Register 3
Interrupt Priority Register 0
Interrupt Priority Register 1
Interrupt Request Control Register 0
Interrupt Request Control Register 1
Interrupt Request Control Register 2
Interrupt Request Enable Register for CT1
Timer Control Register
Timer 2 Control Register

A8H

E1H
BCH
B8H

9AH
BEH
A9H
B9H
C0H

D1H
BFH
BFH
88H

C8H

00H
01000000B

X1XX0000B

00H
XX0000X0B

XXXX00XXB

00H
0X000000B

00H
00H
00H
FFH
00H
00H

XRAM

XPAGE
SYSCON

Page Address Register for XRAM
System Control Register

91H
B1H

00H
1010XX01B

A/D
Converter

ADCON0
ADCON1
ADDATH
ADDATL

A/D Converter Control Register 0
A/D Converter Control Register 1
A/D Converter Data Register, High Byte
A/D Converter Data Register, Low Byte

D8H

DCH
D9H
DAH

00H
01000000B

)

00H
00H

Bit-addressable special function registers

This special function register is listed repeatedly since some bits of it also belong to other functional blocks.

X means that the value is indeterminate or the location is reserved

"E" means that the value of the bit is defined by the logic level at pin PRGEN at the rising edge of the RESET
or HWPD signals

C509-L

Semiconductor Group

Compare /
Capture
Unit (CCU)
Timer 2

CCEN
CC4EN
CCH1
CCH2
CCH3
CCH4
CCL1
CCL2
CCL3
CCL4
CMEN

CMH0

CMH1

CMH2

CMH3

CMH4

CMH5

CMH6

CMH7

CML0

CML1

CML2

CML3

CML4

CML5

CML6

CML7

CC1EN

CC1H0

CC1H1

CC1H2

CC1H3

CC1H4

CC1H5

CC1H6

CC1H7

CC1L0

CC1L1

CC1L2

CC1L3

CC1L4

CC1L5

CC1L6

CC1L7

CMSEL

5 )

Compare/Capture Enable Register
Compare/Capture 4 Enable Register
Compare/Capture Register 1, High Byte
Compare/Capture Register 2, High Byte
Compare/Capture Register 3, High Byte
Compare/Capture Register 4, High Byte
Compare/Capture Register 1, Low Byte
Compare/Capture Register 2, Low Byte
Compare/Capture Register 3, Low Byte
Compare/Capture Register 4, Low Byte
Compare Enable Register
Compare Register 0, High Byte
Compare Register 1, High Byte
Compare Register 2, High Byte
Compare Register 3, High Byte
Compare Register 4, High Byte
Compare Register 5, High Byte
Compare Register 6, High Byte
Compare Register 7, High Byte
Compare Register 0, Low Byte
Compare Register 1, Low Byte
Compare Register 2, Low Byte
Compare Register 3, Low Byte
Compare Register 4, Low Byte
Compare Register 5, Low Byte
Compare Register 6, Low Byte
Compare Register 7, Low Byte
Compare/Capture Enable Register
Compare/Capture 1 Register 0, High Byte
Compare/Capture 1 Register 1, High Byte
Compare/Capture 1 Register 2, High Byte
Compare/Capture 1 Register 3, High Byte
Compare/Capture 1 Register 4, High Byte
Compare/Capture 1 Register 5, High Byte
Compare/Capture 1 Register 6, High Byte
Compare/Capture 1 Register 7, High Byte
Compare/Capture 1 Register 0, Low Byte
Compare/Capture 1 Register 1, Low Byte
Compare/Capture 1 Register 2, Low Byte
Compare/Capture 1 Register 3, Low Byte
Compare/Capture 1 Register 4, Low Byte
Compare/Capture 1 Register 5, Low Byte
Compare/Capture 1 Register 6, Low Byte
Compare/Capture 1 Register 7, Low Byte
Compare Input Select

C1H

C9H

C3H

C5H

C7H

CFH

C2H

C4H

C6H

CEH

F6H

D3H

D5H

D7H

E3H

E5H

E7H

F3H

F5H

D2H

D4H

D6H

E2H

E4H

E6H

F2H

F4H

F6H

D3H

D5H

D7H

E3H

E5H

E7H

F3H

F5H

D2H

D4H

D6H

E2H

E4H

E6H

F2H

F4H

F7H

00H

Table 4
Special Function Registers - Functional Blocks (cont'd)

Block

Symbol

Name

Address

Contents after
Reset

Semiconductor Group

09.96

C509-L

Compare /
Capture
Unit (CCU)
Timer 2
cont'd

CAFR

CRCH
CRCL
COMSETL
COMSETH
COMCLRL
COMCLRH
SETMSK
CLRMSK
CTCON

CTRELH

CTRELL

CT1RELH

CT1RELL

TH2
TL2
T2CON

CT1CON

PRSC

Capture 1, Falling/Rising Edge Register
Comp./Rel./Capt. Reg. High Byte
Comp./Rel./Capt. Reg. Low Byte
Compare Set Register, Low Byte
Compare Set Register, High Byte
Compare Clear Register, Low Byte
Compare Clear Register, High Byte
Compare Set Mask Register
Compare Clear Mask Register
Compare Timer Control Register
Compare Timer Rel. Reg., High Byte
Compare Timer Rel. Reg., Low Byte
Compare Timer 1 Rel. Reg., High Byte
Compare Timer 1 Rel. Reg., Low Byte
Timer 2, High Byte
Timer 2, Low Byte
Timer 2 Control Register
Compare Timer 1 Control Register
Prescaler Control Register

F7H
CBH
CAH
A1H
A2H
A3H
A4H
A5H
A6H
E1H
DFH
DEH
DFH
DEH
CDH
CCH
C8H

BCH
B4H

00H
00H
00H
00H
00H
00H
00H
00H
00H
01000000B

)

00H
00H
00H
00H
00H
00H
00H
X1XX0000B

11010101B

Serial
Channels

ADCON0

PCON

S0BUF
S0CON
S0RELL
S0RELH
S1BUF
S1CON
S1RELL
S1RELH

A/D Converter Control Register
Power Control Register
Serial Channel 0 Buffer Register
Serial Channel 0 Control Register
Serial Channel 0 Reload Reg., Low Byte
Serial Channel 0 Reload Reg., High Byte
Serial Channel 1 Buffer Register
Serial Channel 1 Control Register
Serial Channel 1 Reload Reg., Low Byte
Serial Channel 1 Reload Reg., High Byte

D8H

87H
99H
98H

AAH
BAH
9CH
9BH
9DH
BBH

00H
00H
XXH

)

00H
D9H
XXXXXX11B

XXH

)

01000000B

00H
XXXXXX11B

Watchdog

IEN0

IEN1

IP0

IP1

WDTREL
WDTL

WDTH

Interrupt Enable Register 0
Interrupt Enable Register 1
Interrupt Priority Register 0
Interrupt Priority Register 1
Watchdog Timer Reload Register
Watchdog Timer Register, Low Byte
Watchdog Timer Register, High Byte

A8H

B8H

A9H
B9H
86H
84H
85H

00H
00H
00H
0X000000B

)

00H
00H
00H

Bit-addressable special function registers

This special function register is listed repeatedly since some bits of it also belong to other functional blocks.

X means that the value is indeterminate or the location is reserved

Registers are only readable and cannot be written.

Table 4
Special Function Registers - Functional Blocks (cont'd)

Block

Symbol

Name

Address

Contents after
Reset

C509-L

Semiconductor Group

MUL/DIV
Unit

ARCON
MD0
MD1
MD2
MD3
MD4
MD5

Arithmetic Control Register
Multiplication/Division Register 0
Multiplication/Division Register 1
Multiplication/Division Register 2
Multiplication/Division Register 3
Multiplication/Division Register 4
Multiplication/Division Register 5

EFH
E9H
EAH
EBH
ECH
EDH
EEH

0XXXXXXXB

XXH

Timer 0 /
Timer 1

TCON
TH0
TH1
TL0
TL1
TMOD
PRSC

Timer Control Register
Timer 0, High Byte
Timer 1, High Byte
Timer 0, Low Byte
Timer 1, Low Byte
Timer Mode Register
Prescaler Control Register

88H

8CH
8DH
8AH
8BH
89H
B4H

00H
00H
00H
00H
00H
00H
11010101B

Ports

DIR0

DIR1

DIR2

DIR3

DIR4

DIR5

DIR6

P7
P8
P9

DIR9

Port 0
Direction Register Port 0
Port 1
Direction Register Port 1
Port 2
Direction Register Port 2
Port 3
Direction Register Port 3
Port 4
Direction Register Port 4
Port 5
Direction Register Port 5
Port 6
Direction Register Port 6
Port 7, Analog/Digital Input
Port 8, Analog/Digital Input
Port 9
Direction Register Port 9

80H

90H

A0H

B0H

E8H

F8H

FAH
FAH
DBH
DDH
F9H
F9H

FFH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
--
--
FFH
FFH

Power
Saving
Modes

PCON

Power Control Register

87H

00H

Bit-addressable special function registers

This special function register is listed repeatedly since some bits of it also belong to other functional blocks.

X means that the value is indeterminate and the location is reserved

Table 4
Special Function Registers - Functional Blocks (cont'd)

Block

Symbol

Name

Address

Contents after
Reset

Semiconductor Group

09.96

C509-L

Table 5
Contents of the SFRs, SFRs in numeric order of their addresses

Addr

Register

Content
after
Reset

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Mapped
by

PDIR=

DIR0

PDIR=1

DPL

DPH

WDTL

WDTH

WDTREL

WPSEL

PCON

SMOD

PDS

IDLS

GF1

GF0

PDE

IDLE

TCON

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

TMOD

GATE

C/T

GATE

C/T

TL0

TL1

TH0

TH1

CLK-
OUT

T2EX

INT2

INT6

INT5

INT4

INT3

PDIR=

DIR1

PDIR=1

XPAGE

DPSEL

XXXX.
X000

S0CON

SM0

SM1

SM20

REN0

TB80

RB80

TI0

RI0

S0BUF

IEN2

XX00.
00X0

ECR

ECS

ECT

ECMP

ES1

S1CON

0100.
0000

S1P

SM21

REN1

TB81

RB81

TI1

RI1

S1BUF

S1RELL

PDIR=0

DIR2

PDIR=1

COMSETL 00

1) X means that the value is indeterminate or the location is reserved.
2) SFRs with a comment in this column are mapped registers.

Shaded registers are bit-addressable special function registers.

C509-L

Semiconductor Group

COMSETH 00

COMCLRL 00

COMCLRH 00

SETMSK

CLRMSK

IEN0

EAL

WDT

ET2

ES0

ET1

EX1

ET0

EX0

IP0

OWDS WDTS

S0RELL

INT1

INT0

TxD0

RxD0

PDIR=0

DIR3

PDIR=1

SYSCON

1010.
XX01

CLKP

PMOD

RMAP

XMAP1 XMAP0

SYSCON1

00XX.
XEE0

ESWC

SWC

EA1

EA0

PRGEN1 PRGEN0

SWAP

PRSC

1101.
0101

WDTP

S0P

T2P1

T2P0

T1P1

T1P0

T0P1

T0P0

IEN1

EXEN2 SWDT

EX6

EX5

EX4

EX3

EX2

EADC

IP1

0X00.
0000

PDIR

S0RELH

XXXX.
XX11

S1RELH

XXXX.
XX11

CT1CON

X1XX.
0000

CT1P

CT1F

CLK12

CLK11

CLK10

IEN3

XXXX.
00XX

ECT1

ECC1

IRCON2

ICC17

ICC16

ICC15

ICC14

ICC13

ICC12

ICC11

ICC10

PDIR=0

EICC1

EICC17

EICC16

EICC15

EICC14

EICC13

EICC12

EICC11

EICC10

PDIR=1

IRCON0

EXF2

TF2

IEX6

IEX5

IEX4

IEX3

IEX2

IADC

CCEN

COCAH3 COCAL3 COCAH2 COCAL2 COCAH1 COCAL1 COCAH0 COCAL0

1) X means that the value is indeterminate or the location is reserved.
2) SFRs with a comment in this column are mapped registers.
3) "E" means that the value of the bit is defined by the logic level at pin PRGEN at the rising edge of the RESET

or HWPD signals

Shaded registers are bit-addressable special function registers.

Table 5
Contents of the SFRs, SFRs in numeric order of their addresses (cont'd)

Addr

Register

Content
after
Reset

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Mapped
by

Semiconductor Group

09.96

C509-L

CCL1

CCH1

CCL2

CCH2

CCL3

CCH3

T2CON

T2PS

I3FR

I2FR

T2R1

T2R0

T2CM

T2I1

T2I0

CC4EN

COCO

EN1

COCO

EN0

COCAH
4

COCAL
4

COM0

CRCL

CRCH

TL2

TH2

CCL4

CCH4

PSW

RS1

RS0

IRCON1

ICMP7

ICMP6

ICMP5

ICMP4

ICMP3

ICMP2

ICMP1

ICMP0

CML0

RMAP=0

CC1L0

RMAP=1

CMH0

RMAP=0

CC1H0

RMAP=1

CML1

RMAP=0

CC1L1

RMAP=1

CMH1

RMAP=0

CC1H1

RMAP=1

CML2

RMAP=0

CC1L2

RMAP=1

CMH2

RMAP=0

CC1H2

RMAP=1

ADCON0

CLK

ADEX

BSY

ADM

MX2

MX1

MX0

ADDATH

(MSB)

1) X means that the value is indeterminate or the location is reserved.
2) SFRs with a comment in this column are mapped registers.

Shaded registers are bit-addressable special function registers.

Table 5
Contents of the SFRs, SFRs in numeric order of their addresses (cont'd)

Addr

Register

Content
after
Reset

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Mapped
by

C509-L

Semiconductor Group

ADDATL

.6
(LSB)

ADCON1

0100.
0000

ADCL1 ADCL0 ADST1 ADST0 MX3

MX2

MX1

MX0

CTRELL

RMAP=0

CT1RELL

RMAP=1

CTRELH

RMAP=0

CT1RELH

RMAP=1

ACC

CTCON

0100.
0000

T2PS1

CTP

ICR

ICS

CTF

CLK2

CLK1

CLK0

CML3

RMAP=0

CC1L3

RMAP=1

CMH3

RMAP=0

CC1H3

RMAP=1

CML4

RMAP=0

CC1L4

RMAP=1

CMH4

RMAP=0

CC1H4

RMAP=1

CML5

RMAP=0

CC1L5

RMAP=1

CMH5

RMAP=0

CC1H5

RMAP=1

CM7

CM6

CM5

CM4

CM3

CM2

CM1

CM0

PDIR=0

DIR4

PDIR=1

MD0

MD1

MD2

MD3

MD4

1) X means that the value is indeterminate or the location is reserved.
2) SFRs with a comment in this column are mapped registers.

Shaded registers are bit-addressable special function registers.

Table 5
Contents of the SFRs, SFRs in numeric order of their addresses (cont'd)

Addr

Register

Content
after
Reset

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Mapped
by

Semiconductor Group

09.96

C509-L

MD5

ARCON

0XXX.
XXXX

MDEF

MDOV

SLR

SC.4

SC.3

SC.2

SC.1

SC.0

CML6

RMAP=0

CC1L6

RMAP=1

CMH6

RMAP=0

CC1H6

RMAP=1

CML7

RMAP=0

CC1L7

RMAP=1

CMH7

RMAP=0

CC1H7

RMAP=1

CMEN

RMAP=0

CC1EN

RMAP=1

CMSEL

RMAP=0

CAFR

RMAP=1

CCM7

CCM6

CCM5

CCM4

CCM3

CCM2

CCM1

CCM0

PDIR=0

DIR5

PDIR=1

CC17

CC16

CC15

CC14

CC13

CC12

CC11

CC10

PDIR=0

DIR9

PDIR=1

.6.

TxD1

RxD1

ADST

PDIR=0

DIR6

PDIR=1

1) X means that the value is indeterminate or the location is reserved.
2) SFRs with a comment in this column are mapped registers.

Shaded registers are bit-addressable special function registers.

Table 5
Contents of the SFRs, SFRs in numeric order of their addresses (cont'd)

Addr

Register

Content
after
Reset

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Mapped
by

C509-L

Semiconductor Group

Digital I/O Ports

The C509-L allows for digital I/O on 64 lines grouped into 8 bidirectional 8-bit ports. Each port bit
consists of a latch, an output driver and an input buffer. Read and write accesses to the I/O ports P0
through P6 and P9 are performed via their corresponding special function registers P0 to P6 and
P9. The port structure of the C509-L is designed to operate either as a quasi-bidirectional port
structure, compatible to the standard 8051-Family, or as a genuine bidirectional port structure. This
port operating mode can be selected by software (setting or clearing the bit PMOD in the SFR
SYSCON).

The output drivers of port 0 and 2 and the input buffers of port 0 are also used for accessing external
memory. In this application, port 0 outputs the low byte of the external memory address, time-
multiplexed with the byte being written or read. Port 2 outputs the high byte of the external memory
address when the address is 16 bits wide. Otherwise, the port 2 pins continue emitting the P2 SFR
contents.

Analog Input Ports

Ports 7 and 8 are available as input ports only and provide for two functions. When used as digital
inputs, the corresponding SFR's P7 and P8 contain the digital value applied to port 7 and port 8
lines. When used for analog inputs the desired analog channel is selected by a three-bit field in SFR
ADCON0 or a four-bit field in SFR ADCON1. Of course, it makes no sense to output a value to these
input-only ports by writing to the SFR's P7 or P8; this will have no effect.

lf a digital value is to be read, the voltage levels are to be held within the input voltage specifications
(

). Since P7 and P8 are not bit-addressable registers, all input lines of P7 or P8 are read at the

same time by byte instructions.

Nevertheless, it is possible to use ports 7 and 8 simultaneously for analog and digital input.
However, care must be taken that all bits of P7 or P8 that have an undetermined value caused by
their analog function are masked.

Semiconductor Group

09.96

C509-L

Port Structure Selection

After a reset operation of the C509-L, the quasi-bidirectional 8051-compatible port structure is
selected. For selection of the bidirectional port structure (CMOS) the bit PMOD of SFR SYSCON
must be set. Because each port pin can be programmed as an input or an output, additionally, after
the selection of the bidirectional mode the direction register of the ports must be written (except the
analog/digital input ports 7,8). This direction registers are mapped to the port registers. This means,
the port register address is equal to its direction register address. Figure 16 illustrates the port- and
direction register configuration.

Figure 16
Port Register, Direction Register

For the access the direction registers a double instruction sequence must be executed. The first
instruction has to set bit PDIR in SFR IP1. Thereafter, a second instruction can read or write the
direction registers. PDIR will automatically be cleared after the second machine cycle (S2P2) after
having been set. For this time, the access to the direction register is enabled and the register can
be read or written. Further, the double instruction sequence as shown in figure 16, cannot be
interrupted by an interrupt,

When the bidirectional port structure is activated (bit PMOD in SFR SYSCON =1) after a reset, the
ports are defined as inputs (direction registers default values after reset are set to FFH).
With PMOD = 0 (quasi-bidirectional port structure selected), any access to the direction registers
has no effect on the port driver circuitries.

C509-L

Semiconductor Group

Timer / Counter 0 and 1

Timer/Counter 0 and 1 can be used in four operating modes as listed in table 6 :

In the "timer" function (C/T = `0') the register is incremented by a count rate of

OSC

/6 up to

OSC

/32.

In the "counter" function the register is incremented in response to a 1-to-0 transition at its
corresponding external input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a
falling edge the max. count rate is

OSC

/12. External inputs INT0 and INT1 (P3.2, P3.3) can be

programmed to function as a gate to facilitate pulse width measurements. Figure 17 illustrates the
input clock logic of timer 0/1.

Figure 17
Timer/Counter 0 and 1 Input Clock Logic

Table 6
Timer/Counter 0 and 1 Operating Modes

Mode

Description

TMOD

Input Clock

internal

external (max)

8-bit timer/counter with a
divide-by-32 prescaler

OSC

/6x32 up to

OSC

/48x32

OSC

/12x32

16-bit timer/counter

OSC

/6 up to

OSC

/12

8-bit timer/counter with
8-bit autoreload

Timer/counter 0 used as one
8-bit timer/counter and one
8-bit timer
Timer 1 stops

TxP1

TxP0

Prescaler

C509-L

Semiconductor Group

The block diagram in figure 18 shows the general configuration of the CCU. All CC1 to CC4
registers and the CRC register are exclusively assigned to timer 2. Each of the eight compare
registers CM0 through CM7 can either be assigned to timer 2 or to the faster compare timer, e.g. to
provide up to 8 PWM output channels. The assignment of the CMx registers - which can be done
individually for every single register - is combined with an automatic selection of one of the two
possible compare modes. The compare/capture registers CC10 to CC17 and the reload register
CT1REL are assigned to compare timer 1 and are mapped to the corresponding registers of the
compare timer.

The compare function and the reaction of the corresponding outputs depend on the timer/compare
register combination. Table 7 shows the possible configurations of the CCU and the corresponding
compare modes which can be selected. The following sections describe the function of these
configurations.

Table 7
CCU Configurations

Assigned
Timer

Compare
Register

Compare Output at

Possible Modes

Timer 2

CRCH/CRCL
CCH1/CCL1
CCH2/CCL2
CCH3/CCL3
CCH4/CCL4

P1.0/INT3/CC0
P1.1/INT4/CC1
P1.2/INT5/CC2
P1.3/INT6/CC3
P1.4/INT2/CC4

Compare mode 0, 1 + Reload
Compare mode 0, 1 / capture
Compare mode 0, 1 / capture
Compare mode 0, 1 / capture
Compare mode 0, 1 / capture)

CCH4/CCL4

P1.4/INT2/CC4
P5.0/CCM0

P5.7/CCM7

Compare mode 1
"Concurrent compare"

CMH0/CML0

CMH7/CML7

P4.0/CM0

P4.7/CM7

Compare mode 0

COMSET
COMCLR

P5.0/CCM0

P5.7/CCM7

Compare mode 2

Compare
Timer

CMH0/CML0

CMH7/CML7

P4.0/CM0

P4.7/CM7

Compare mode 1

Compare
Timer 1

CC1H0/CC1L0

CC1H7/CC1L7

P5.0/CCM0

P5.7/CCM7

Compare mode 0 / capture

Semiconductor Group

09.96

C509-L

Timer 2 Operation

Gated Timer Mode : In gated timer function, the external input pin P1.7/T2 operates as a gate to the
input of timer 2. lf T2 is high, the internal clock input is gated to the timer. T2 = 0 stops the counting
procedure.The external gate signal is sampled once every machine cycle.

Event Counter Mode : In the event counter function, the timer 2 is incremented in response to a 1-
to-0 transition at its corresponding external input pin P1.7/T2. In this function, the external input is
sampled every machine cycle. The maximum count rate is 1/12 of the oscillator frequency.

Reload of Timer 2 : Two reload modes are selectable:
In mode 0, when timer 2 rolls over from all 1's to all 0's, it not only sets TF2 but also causes the timer
2 registers to be loaded with the 16-bit value in the CRC register, which is preset by software.
In mode 1, a 16-bit reload from the CRC register is caused by a negative transition at the correspon-
ding input pin P1.5/T2EX.

Figure 19
Block Diagram of Timer 2

Semiconductor Group

09.96

C509-L

Compare Modes

The compare function of a timer/register combination operates as follows. the 16-bit value stored in
a compare or compare/capture register is compared with the contents of the timer register. lf the
count value in the timer register matches the stored value, an appropriate output signal is generated
at a corresponding port pin. Several timer/compare register combinations are selectable (see table
7). In these configurations three cdifferent ompare modes are selectable.

Compare Mode 0

In compare mode 0, upon matching the timer and compare register contents, the output signal
changes from low to high. lt goes back to a low level on timer overflow. As long as compare mode
0 is enabled, the appropriate output pin is controlled by the timer circuit only and writing to the port
will have no effect. Figure 21 shows a functional diagram of a port circuit when used in compare
mode 0. The port latch is directly controlled by the timer overflow and compare match signals. The
input line from the internal bus and the write-to-latch line of the port latch are disconnected when
compare mode 0 is enabled.

Figure 21
Port Latch in Compare Mode 0

Compare Mode 1

Ilf compare mode 1 is enabled (can only be selected for compare registers assigned to timer 2) and
the software writes to the appropriate output latch at the port, the new value will not appear at the
output pin until the next compare match occurs. Thus, it can be choosen whether the output signal
has to make a new transition (1-to-0 or 0-to-1, depending on the actual pin-level) or should keep its
old value at the time when the timer value matches the stored compare value.

In compare mode 1 (see figure 22) the port circuit consists of two separate latches. One latch
(which acts as a "shadow latch") can be written under software control, but its value will only be
transferred to the port latch (and thus to the port pin) when a compare match occurs.

Semiconductor Group

09.96

C509-L

Multiplication / Division Unit (MDU)

This on-chip arithmetic unit of the C509-L provides fast 32-bit division, 16-bit multiplication as well
as shift and normalize features. All operations are unsigned integer operations. Table 8 describes
the five general operations the MDU is able to perform.

1) 1

= 6

CLP = 1 machine cycle = 375 ns at 16-MHz oscillator frequency

2) The maximal shift speed is 6 shifts per machine cycle

The MDU consists of seven special function registers (MD0-MD5, ARCON) which are used as
operand, result, and control registers. The three operation phases are shown in figure 24.

Figure 24
Operating Phases of the MDU

Table 8
MDU Operation Characteristics

Operation

Result

Remainder

Execution Time

32bit/16bit
16bit/16bit
16bit x 16bit
32-bit normalize
32-bit shift L/R

32bit
16bit
32bit

16bit
16bit

C509-L

Semiconductor Group

For starting an operation, registers MD0 to MD5 and ARCON must be written to in a certain
sequence according table 8 and 9. The order the registers are accessed determines the type of the
operation. A shift operation is started by a final write operation to SFR ARCON.

Abbrevations :

D'end

: Dividend, 1st operand of division

D'or

: Divisor, 2nd operand of division

M'and

: Multiplicand, 1st operand of multiplication

M'or

: Multiplicator, 2nd operand of multiplication

: Product, result of multiplication

Rem

: Remainder

Quo

: Quotient, result of division

...L

: means, that this byte is the least significant of the 16-bit or 32-bit operand

...H

: means, that this byte is the most significant of the 16-bit or 32-bit operand

Table 9
Programming the MDU for Multiplication and Division

Operation

32Bit/16Bit

16Bit/16Bit

16Bit x 16Bit

First Write

Last Write

MD0

D'endL

MD1

D'end

MD2

D'end

MD3

D'endH

MD4

D'orL

MD5

D'orH

MD0

D'endL

MD1

D'endH

MD4

D'orL

MD5

D'orH

MD0

M'andL

MD4

M'orL

MD1

M'andH

MD5

M'orH

First Read

Last Read

MD0

QuoL

MD1

Quo

MD2

Quo

MD3

QuoH

MD4

RemL

MD5

RemH

MD0

QuoL

MD1

QuoH

MD4

RemL

MD5

RemH

MD0

PrL

MD1

MD2

MD3

PrH

Table 10
Programming athe MDU for a Shift or Normalize Operation

Operation

Normalize, Shift Left, Shift Right

First write

Last write

MD0

least significant byte

MD1

MD2

MD3

most significant byte

ARCON

start of conversion

First read

Last read

MD0

least significant byte

MD1

MD2

MD3

most significant byte

Semiconductor Group

09.96

C509-L

Serial Interfaces 0 and 1

The C509-L has two serial interfaces which are functionally nearly identical concerning the
asynchronous modes of operation. The two channels are full-duplex, meaning they can transmit
and receive simultaneously. The serial channel 0 is completely compatible with the serial channel
of the C501 (one synchronous mode, three asynchronous modes). Serial channel 1 has the same
functionality in its asynchronous modes, but the synchronous mode and the fixed baud rate UART
mode is missing.

The operating modes of the serial interfaces is illustrated in table 11. The possible baudrates can
be calculated using the formulas given in table 12.

Table 11
Operating Modes of Serial Interface 0 and 1

Serial
Interface

Mode

S0CON

S1CON

Description

SM0

SM1

Shift register mode
Serial data enters and exits through R

D0;

D0 outputs the shift clock; 8-bit are

transmitted/received (LSB first); fixed baud rate

8-bit UART, variable baud rate
10 bits are transmitted (through T

D0) or

received (at R

D0)

9-bit UART, fixed baud rate
11 bits are transmitted (through T

D0) or

received (at R

D0)

9-bit UART, variable baud rate
Like mode 2

9-bit UART; variable baud rate
11 bits are transmitted (through T

D1) or

received (at R

D1)

8-bit UART; variable baud rate
10 bits are transmitted (through T

D1) or

received (at R

D1)

C509-L

Semiconductor Group

For clarification some terms regarding the difference between "baud rate clock" and "baud rate"
should be mentioned. In the asynchronous modes the serial interfaces require a clock rate which is
16 times the baud rate for internal synchronization. Therefore, the baud rate generators/timers have
to provide a "baud rate clock" (output signal in figure 25 and figure 26) to the serial interface
which - there divided by 16 - results in the actual "baud rate". Further, the abrevation f

OSC

refers to

the oscillator frequency (crystal or external clock operation).

The variable baud rates for modes 1 and 3 of the serial interface 0 can be derived from either timer
1 or a decdicated baud rate generator (see figure 25). The variable baud rates for modes A and B
of the serial interface 1 are derived from a decdicated baud rate generator as shown in figure 26.

Figure 25
Serial Interface 0 : Baud Rate Generation Configuration

Figure 26
Serial Interface 1 : Baud Rate Generator Configuration

Semiconductor Group

09.96

C509-L

Table 12 below lists the values/formulas for the baud rate calculation of serial interface 0 and 1 with
its dependencies of the control bits BD, SMOD, S0P, and S1P.

Table 12
Serial Interface 0 - Baud Rate Dependencies

Serial Interface 0
Operating Modes

Active Control Bits

Baud Rate Calculation

S0P

SMOD S1P

Mode 0 (Shift Register)

OSC

/ 6

Mode 1 (8-bit UART)
Mode 3 (9-bit UART)

0 or 1

Controlled by timer 1 overflow :
(2

SMOD

timer 1 overflow rate) / 32

0 or 1

Controlled by baud rate generator :
(2

S0P

SMOD

OSC

) /

(64

baud rate generator overflow rate)

Mode 2 (9-bit UART)

0
1

OSC

/ 32

OSC

/ 16

Mode A (9-bit UART)
Mode B (8-bit UART)

0 or 1

S1P

OSC

) /

(32

baud rate generator overflow rate)

Semiconductor Group

09.96

C509-L

The A/D converter provides the following features:

15 multiplexed input channels, which can also be used as digital inputs (port 7, port 8)
10-bit resolution
Single or continuous conversion mode
Internal or external start-of-conversion trigger capability
Programmable conversion and sample clock
Interrupt request generation after each conversion
Using successive approximation conversion technique via a capacitor array
Built-in hidden calibration of offset and linearity errors

The A/D converter uses basically three clock signals for operation : the input clock f

(=1/t

), the

conversion clock f

ADC

(=1/t

ADC

) and the sample clock f

(=1/t

). All clock signals are derived

from the C509-L system clock f

OSC

which is applied at the XTAL pins. The input clock f

is equal

to f

OSC

while the conversion clock and the sample clock must be adapted. The conversion clock is

limited to a maximum frequency of 2 MHz. The table in figure 28 defines the divider ratio for the
conversion and sample clock of each combination of the prescaler bits.

Figure 28
A/D Converter Clock Selection

Conversion Clock

ADC

Sample Clock

ADCL1 ADCL0

ADC

ADST1 ADST0
0

ADST1 ADST0
1

/ 4

/ 8

/ 16

/ 32

/ 64

/ 8

/ 16

/ 32

/ 64

/ 128

/ 16

/ 32

/ 64

/ 128

/ 256

/ 32

/ 64

/ 128

/ 256

/ 512

C509-L

Semiconductor Group

A/D Conversion Timing

An A/D conversion is internally started by writing into the SFR ADDATL with dummy data. A write
to SFR ADDATL will start a new conversion even if a conversion is currently in progress. Basically,
the A/D conversion procedure is divided into three parts :

Sample phase (t

), used for sampling the analog input voltage.

Conversion phase (t

), used for the real A/D conversion.(includes calibration)

Write result phase (t

), used for writing the conversion result into the ADDAT registers.

The total A/D conversion time is defined by t

ADCC

which is the sum of the two phase times t

and

. The duration of the two phases of an A/D conversion is specified by its specific timing

parameter as shown in figure 29.

Figure 29
A/D Conversion Timing

Conversion Clock

Prescaler

ADCL1 ADCL0

Sample Clock

Prescaler

ADST1 ADST0

Sample

Time

Conversion

Time

ConversionTime

ADCC

Number of

CPU Cycles

8 x t

16 x t

32 x t

64 x t

40 x t

48 x t

56 x t

72 x t

104 x t

8
9

12
17

16 x t

32 x t

64 x t

128 x t

80 x t

96 x t

112 x t

144 x t

208 x t

16
18
24
34

32 x t

64 x t

128 x t

256 x t

160 x t

192 x t

224 x t

288 x t

416 x t

32
37
48
69

64 x t

128 x t

256 x t

512 x t

320 x t

384 x t

448 x t

576 x t

832 x t

64
74
96

138

Semiconductor Group

09.96

C509-L

Table 13
Interrupt Sources and their Corresponding Interrupt Vectors

Interrupt Source

Interrupt Vector Address

Interrupt Request Flags

External Interrupt 0

0003H

IE0

Timer 0 Overflow

000BH

TF0

External Interrupt 1

0013H

IE1

Timer 1 Overflow

001BH

TF1

Serial Channel 0

0023H

RI0 / TI0

Timer 2 Overflow / Ext. Reload

002BH

TF2 / EXF2

A/D Converter

0043H

IADC

External Interrupt 2

004BH

IEX2

External Interrupt 3

0053H

IEX3

External Interrupt 4

005BH

IEX4

External Interrupt 5

0063H

IEX5

External Interrupt 6

006BH

IEX6

Serial Channel 1

0083H

RI1 / TI1

Compare Match Interupt of
Compare Registers CM0-CM7
assigned to Timer 2

0093H

ICMP0 - ICMP7

Compare Timer Overflow

009BH

CTF

Compare Match Interupt of
Compare Register COMSET

00A3H

ICS

Compare Match Interupt of
Compare Register COMCLR

00ABH

ICR

Compare / Capture Event interrupt 00D3H

ICC10 - ICC17

Compare Timer 1 Overflow

00DBH

CT1F

C509-L

Semiconductor Group

Fail Save Mechanisms

The C509-L offers two on-chip peripherals which monitor the program flow and ensure an automatic
"fail-safe" reaction for cases where the controller's hardware fails or the software hangs up:

A programmable watchdog timer (WDT) with variable time-out period from 189 microseconds

up to approx. 0.79 seconds at 16 MHz.

An oscillator watchdog (OWD) which monitors the on-chip oscillator and forces the

microcontroller into the reset state if the on-chip oscillator fails.

Programmable Watchdog Timer

The watchdog timer in the C509-L is a 15-bit timer, which is incremented by a count rate of

OSC

/12

up to

OSC

/384. For programming of the watchdog timer overflow rate, the upper 7 bit of the watchdog

timer can be written. Figure 34 shows the block diagram of the watchdog timer unit.

Figure 34
Block Diagram of the Programmable Watchdog Timer

The watchdog timer can be started by software (bit SWDT) or by hardware through pin PE/SWD,
but it cannot be stopped during active mode of the C509-L. If the software fails to refresh the running
watchdog timer an internal reset will be initiated on watchdog timer overflow. For refreshing of the
watchdog timer the content of the SFR WDTREL is transferred to the upper 7-bit of the watchdog
timer. The refresh sequence consists of two consecutive instructions which set the bits WDT and
SWDT each. The reset cause (external reset or reset caused by the watchdog) can be examined
by software (flag WDTS). It must be noted, however, that the watchdog timer is halted during the
idle mode and power down mode of the processor.

Semiconductor Group

09.96

C509-L

Oscillator Watchdog

The oscillator watchdog of the C509-L serves for three functions :

Monitoring of the on-chip oscillator's function.

The watchdog supervises the on-chip oscillator's frequency; if it is lower than the frequency of
the auxiliary RC oscillator in the watchdog unit, the internal clock is supplied by the RC
oscillator and the device is brought into reset; if the failure condition disappears (i.e. the on-
chip oscillator has a higher frequency than the RC oscillator), the part executes a final reset
phase of appr. 0.5 ms in order to allow the oscillatior to stabilize; then the oscillator watchdog
reset is released and the part starts program execution again.

Restart from the hardware power down mode.

If the hardware power down mode is terminated the oscillator watchdog has to control the
correct start-up of the on-chip oscillator and to restart the program. The oscillator watchdog
function is only part of the complete hardware power down sequence; however, the watchdog
works identically to the monitoring function.

Fast internal reset after power-on.

In this function the oscillator watchdog unit provides a clock supply for the reset before the on-
chip oscillator has started. In this case the oscillator watchdog unit also works identically to
the monitoring function.

Figure 35
Block Diagram of the Oscillator Watchdog

C509-L

Semiconductor Group

Power Saving Modes

The C509-L provides three power saving modes in which power consumption can be significantly
reduced.

Idle mode

The CPU is gated off from the oscillator. All peripherals are still provided with the clock and
are able to work.

Power down mode

The operation of the C509-L is completely stopped and the oscillator is turned off. This mode
is used to save the contents of the internal RAM with a very low standby current. Power down
mode can be entered by software or by hardware (pin HWPD).

Slow-down mode

The controller keeps up the full operating functionality, but its normal clock frequency is
internally divided by eight. This slows down all parts of the controller, the CPU and all
peripherals, to 1/8 th of their normal operating frequency. Slowing down the frequency greatly
reduces power consumption.

Table 14 gives a general overview of the entry and exit procedures of the power saving modes.

In the power down mode of operation,

can be reduced to minimize power consumption. It must

be ensured, however, that

is not reduced before the power down mode is invoked, and that

is restored to its normal operating level, before the power down mode is terminated.

If e.g. the idle mode is left through an interrupt, the microcontroller state (CPU, ports, peripherals)
remains preserved. If a power saving mode is left by a hardware reset, the microcontroller state is
disturbed and replaced by the reset state of the C509-L.

Table 14
Power Saving Modes Overview

Mode

Entering
2-Instruction
Example

Leaving by

Remarks

Idle mode

ORL PCON, #01H
ORL PCON, #20H

Ocurrence of an
interrupt from a
peripheral unit

CPU clock is stopped;
CPU maintains their data;
peripheral units are active (if
enabled) and provided with
clock

Hardware Reset

Software
Power-Down Mode

Hardware
Power-Down Mode

ORL PCON, #02H
ORL PCON, #40H

Hardware Reset

Oscillator is stopped;
contents of on-chip RAM and
SFR's are maintained;

Low level at pin
HWPD

High level at pin
HWPD

Slow Down Mode

ORL PCON,#10H

ANL PCON,#0EFH
or
Hardware Reset

Oscillator frequency is
reduced to 1/8 of its nominal
frequency

Semiconductor Group

09.96

C509-L

Absolute Maximum Ratings

Ambient temperature under bias (

) ......................................................... 40 to 110

Storage temperature (

stg

) .......................................................................... 65

C to 150

Voltage on

pins with respect to ground (

) ....................................... 0.5 V to 6.5 V

Voltage on any pin with respect to ground (

) ......................................... 0.5 V to

+0.5 V

Input current on any pin during overload condition ..................................... 10 mA to 10 mA
Absolute sum of all input currents during overload condition ..................... I 100 mA I
Power dissipation........................................................................................ 1 W

Note:

Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage of the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for longer
periods may affect device reliability. During overload conditions (

) the

Voltage on

pins with respect to ground (

) must not exceed the values defined by the

absolute maximum ratings.

DC Characteristics

= 5 V + 10%, 15%;

= 0 V

= 0 to 70

for the SAB-C509

= 40 to 85

C for the SAF-C509

Parameter

Symbol

Limit Values

Unit

Test Condition

min.

max.

Input low voltage
(except EA, RESET, HWPD)

0.5

0.2

0.1

Input low voltage (EA)

IL1

0.5

0.2

0.3

Input low voltage (HWPD,
RESET)

IL2

0.5

0.2

0.1

Input low voltage (CMOS)
(ports 0 - 9)

ILC

0.5

0.3

Input high voltage (except
RESET, XTAL2 and HWPD

0.2

0.9

+ 0.5

Input high voltage to XTAL2

IH1

0.7

+ 0.5

Input high voltage to RESET and
HWPD

IH2

0.6

+ 0.5

Input high voltage (CMOS)
(ports 0 - 9)

IHC

0.7

+ 0.5

CMOS input hysteresis
(ports 1, 3 to 9)

IHYS

0.1

C509-L

Semiconductor Group

Output low voltage
(ports 1, 2, 3, 4, 5, 6, 9)

0.45

= 1.6

Output low voltage
(port 0, ALE, PSEN/RDF, RO)

OL1

0.45

= 3.2mA

Output high voltage
(ports 1, 2, 3, 4, 5, 6, 9)

2.4

0.9

V
V

= 80

= 10

Output high voltage
(port 0 in external bus mode, ALE,
PSEN/RDF, RO)

OH1

2.4

0.9

V
V

= 800

= 80

Output high voltage (CMOS)
(ports 1, 2, 3, 4, 5, 6, 9)

OHC

0.9

= 800

Logic input low current
(ports 1, 2, 3, 4, 5, 6, 9)

= 0.45 V

Logical 1-to-0 transition current
(ports 1, 2, 3, 4, 5, 6, 9)

650

= 2 V

Input leakage current

(port 0, 7, 8, HWPD)

(port 0 in CMOS)

100

0.45 <

150

0.45 <

> 100

Input leakage current
(EA, PRGEN)
(ports 1, 2, 3, 4, 5, 6, 9 in CMOS)

LIC

0.45 <

Input low current to RESET for reset

LI2

100

= 0.45 V

Input low current (XTAL2)

LI3

= 0.45 V

Input low current (PE/SWD, OWE)

LI4

= 0.45 V

Pin capacitance

= 1 MHz

= 25

Overload current

10) 11)

Parameter

Symbol

Limit Values

Unit

Test Condition

min.

max.

Semiconductor Group

09.96

C509-L

Notes :

1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the

of ALE

and port 1, 3, 4, 5, 6, and 9. The noise is due to external bus capacitance discharging into the port 0 and port
2 pins when these pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading
> 100 pF), the noise pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE
with a schmitt-trigger, or use an address latch with a schmitt-trigger strobe input.

2) Capacitive loading on ports 0 and 2 may cause the

on ALE and PSEN/RDF to momentarily fall below the

0.9

specification when the address lines are stabilizing.

(power down mode) is measured under following conditions:

EA = RESET =

; Port0 = Port7 = Port8 =

; XTAL1 = N.C.; XTAL2 =

; PE/SWD = OWE =

;

HWDP =

;

AREF

;

AGND

; all other pins are disconnected.

Hardware power down mode current (

) is measured with OWE =

(active mode) is measured with:

XTAL2 driven with

= 5 ns ,

+ 0.5 V,

0.5 V; XTAL1 = N.C.; EA = PE/SWD=

;

Port0 =

Port7 =

Port8 =

; HWPD =

; RESET =

; all other pins are disconnected.

would be

slightly higher if a crystal oscillator is used.

(idle mode) is measured with all output pins disconnected and with all peripherals disabled;

XTAL2 driven with

= 5 ns,

+ 0.5 V,

0.5 V; XTAL1 = N.C.; RESET =

;

HWPD =

; Port0 = Port7 =

Port8 =

; EA =

PE/SWD =

; all other pins are disconnected;

(slow down mode) is measured with all output pins disconnected and with all peripherals disabled;

XTAL2 driven with

= 5 ns,

+ 0.5 V,

0.5 V; XTAL1 = N.C.; RESET =

;

HWPD =

; Port7 =

Port8 =

; EA =

PE/SWD =

; all other pins are disconnected;

7) Input leakage current for port 0 is measured with RESET =

CC max

at other frequencies is given by:

active mode:TBD
idle mode:TBD
where

osc

is the oscillator frequency in MHz.

values are given in mA and measured at

= 5 V.

9) Typical power supply current (

CC typ

) with test conditiones as defined in note 4 and 5 is given by:

active mode, 12 MHz :45 mA
active mode, 16 MHz :72 mA
idle mode, 16 MHz :29 mA

10)Overload conditions occur if the standard operating conditions are exeeded, ie. the voltage on any pin exceeds

the specified range (i.e.

+ 0.5 V or

- 0.5 V). The supply voltage

and

must remain

within the specified limits. The absolute sum of input currents on all port pins may not exceed 50 mA.

11)Not 100% tested, guaranteed by design characterization.

12)The typical

values are periodically measured at

= +25 °C but not 100% tested.

Parameter

Symbol

Limit Values

Unit

Test Condition

typ.

12)

max.

Power supply current:
C509-L, Active mode, 12 MHz

C509-L, Active mode, 16 MHz

C509-L, Idle mode, 12 MHz

C509-L, Idle mode, 16 MHz

C509-L, Slow down mode, 12 MHz
C509-L, Slow down mode, 16 MHz
C509-L, Power Down Mode

TBD
TBD
TBD
TBD
TBD
TBD
50

mA
mA
mA
mA
mA
mA

= 5 V,

= 2...5.5

C509-L

Semiconductor Group

A/D Converter Characteristics

= 0 to 70

for the SAB-C509

= 40 to 85

C for the SAF-C509

= 5 V + 10%, 15%;

= 0 V

4 V

AREF

+0.1 V ;

-0.1 V

AGND

+0.2 V

Notes see next page.

Clock calculation table

Further timing conditions : t

ADC

min = 500 ns = CCP x CLP

= 1 / f

OSC

= CLP

= t

ADC

x SCP

Parameter

Symbol

Limit Values

Unit

Test Condition

min.

max.

Analog input voltage

AIN

AGND

AREF

Sample time

512

see table below

Conversion time

ADCC

832

see table below

Total unadjusted error

TUE

LSB

Internal resistance of reference
voltage source

AREF

ADC

/ 250

- 0.25

ADC

in [ns]

5) 6)

Internal resistance of analog
source

ASRC

/ 500

- 0.25

in [ns]

3) 6)

ADC input capacitance

AIN

Conversion Clock Selection

Sample Clock Selection

Sample Time

Conversion Time

ADCC

ADCL1 ADCL0

Prescaler

CCP

ADST1 ADST0

Prescaler

SCP

8 x t

16 x t

32 x t

64 x t

48 x t

56 x t

72 x t

104 x t

16 x t

32 x t

64 x t

128 x t

96 x t

112 x t

144 x t

208 x t

32 x t

64 x t

128 x t

256 x t

192 x t

224 x t

288 x t

416 x t

64 x t

128 x t

256 x t

512 x t

384 x t

448 x t

576 x t

832 x t

Semiconductor Group

09.96

C509-L

Notes:

1) V

AIN

may exeed V

AGND

or V

AREF

up to the absolute maximum ratings. However, the conversion result in

these cases will be X000

or X3FF

, respectively.

2) During the sample time the input capacitance

AIN

can be charged/discharged by the external source. The

internal resistance of the analog source must allow the capacitance to reach their final voltage level within t

After the end of the sample time t

, changes of the analog input voltage have no effect on the conversion result.

3) This parameter includes the sample time t

, the time for determining the digital result and the time for the

calibration. Values for the conversion clock f

ADC

depend on programming and can be taken from the table

below.

4) T

is tested at V

AREF

= 5.0 V, V

AGND

= 0 V, V

= 4.9 V. It is guaranteed by design characterization for all

other voltages within the defined voltage range.
If an overload condition occurs on maximum 2 not selected analog input pins and the absolute sum of input
overload currents on all analog input pins does not exceed 10 mA, an additional conversion error of 1/2 LSB
is permissible.

5) During the conversion the ADC's capacitance must be repeatedly charged or discharged. The internal

resistance of the reference source must allow the capacitance to reach their final voltage level within the
indicated time. The maximum internal resistance results from the programmed conversion timing.

6) Not 100% tested, but guaranteed by design characterization.

C509-L

Semiconductor Group

AC Characteristics

Interfacing the C509-L to devices with float times up to 20 ns is permissible. This limited bus contention will not
cause any damage to port 0 drivers.

= 5 V + 10%, 15%;

= 0 V

= 0 to 70

for the SAB-C509

= 40 to 85

C for the SAF-C509

(

for port 0, ALE and PSEN outputs = 100 pF;

for all other outputs = 80 pF)

Program Memory Characteristics

Parameter

Symbol

Limit Values

Unit

16-MHz clock

Duty Cycle

0.4 to 0.6

Variable Clock

1/CLP = 3.5 MHz to

16 MHz

min.

max.

min.

max.

ALE pulse width

LHLL

CLP-15

Address setup to ALE

AVLL

TCL

Hmin

-15

Address hold after ALE

LLAX

TCL

Hmin

-15

Address to valid instruction in

LLIV

2 CLP-50

ALE to PSEN/RDF

LLPL

TCL

Lmin

-15

PSEN/RDF pulse width

PLPH

CLP+
TCL

Hmin

-15

PSEN/RDF to valid instruction in

PLIV

CLP+
TCL

Hmin

-50

Input instruction hold after PSEN/
RDF

PXIX

Input instruction float after PSEN/
RDF

PXIZ

TCL

Lmin

-10

Address valid after PSEN/RDF

PXAV

TCL

Lmin

-5

Address to valid instruction in

AVIV

2 CLP+
TCL

Hmin

-55

Address float to PSEN/RDF

AZPL

- 5

Semiconductor Group

09.96

C509-L

External Data Memory Characteristics

Parameter

Symbol

Limit Values

Unit

16-MHz clock

Duty Cycle

0.4 to 0.6

Variable Clock

1/CLP= 3.5 MHz to

16 MHz

min.

max.

min.

max.

RD pulse width

RLRH

158

3 CLP-30

WR pulse width

WLWH

158

3 CLP-30

Address hold after ALE

LLAX2

CLP -15

RD to valid data in

RLDV

100

2 CLP+
TCL

Hmin

-50

Data hold after RD

RHDX

Data float after RD

RHDZ

CLP-12

ALE to valid data in

LLDV

200

4 CLP-50

Address to valid data in

AVDV

200

4 CLP+
TCL

Hmin

-75

ALE to WR or RD

LLWL

103

CLP+
TCL

Lmin

-15

CLP+
TCL

Lmin

+15

Address valid to WR

AVWL

2 CLP-30

WR or RD high to ALE high

WHLH

TCL

Hmin

-15

TCL

Hmin

+15 ns

Data valid to WR transition

QVWX

TCL

Lmin

-20

Data setup before WR

QVWH

163

3 CLP+
TCL

Lmin

-50

Data hold after WR

WHQX

TCL

Hmin

-20

Address float after RD

RLAZ

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