Type
Ordering Code
Package
FZE 1658G
Q67000-A8361
P-DSO-24-1
8 x Digital Sensor Interface
P-DSO-24-1
Features
q
Input protection against 2000 V burst/500 V surge
pulse according to IEC 801 4/5
q
Input characteristic according to IEC 65 A, type 2
(24 V DC)
q
Digital filter
q
Serial in/out for easy cascading
q
Low power dissipation
q
SMD package
Semiconductor Group
1
01.97
FZE 1658G
The FZE 1658G is an integrated interface for digital sensors - i.e. proximity switches - in
industrial automation equipment. The IC has eight integrated highly protected and
failsafe inputs with status LED and a serial synchronous output for direct MC-interfacing.
FZE 1658G
Semiconductor Group
2
Pin Configuration
(top view)
FZE 1658G
Semiconductor Group
3
Pin Definitions and Functions
Pin
Symbol
Function
15, 13, 11, 9,
5, 3, 1, 23
I0 - I7
Inputs for 24-V signals, in conjunction with
R
V
and
R
EXT
current sink characteristic.
16, 14, 12,
10, 6, 4, 2, 24
L0 - L7
Outputs for the status LEDs; LED lights when H-signal is
present at input.
21
CT
Pin for connecting the frequency-determining capacitor for
the filter clock; also reset input if CT is connected to DGND
.
7
GND
Ground for all 24-V signals, substrate.
22
DGND
Ground for all 5-V signals, no internal connection to GND.
Any interruption of GND or DGND with the supply voltage
present may result in destruction of the device.
8
V
S
Supply voltage; undervoltage activates internal reset.
20
SO-N
Serial output, open drain.
17
SE-N
Extention input for serial cascading with pull-up current
source.
18
LO-N
Latch input, edge H-L results in transfer of data from the
digital filters to the output register.
19
T
Clock for serial output, positive edge triggered.
FZE 1658G
Semiconductor Group
4
Functional Description and Application
The Integrated circuit FZE 1658G is used to detect the signal states of eight independent
input lines according to IEC 65A Type 2 (e.g. two-wire proximity switches) with a
common ground (GND). For operation in accordance with IEC 65A, it is necessary for
the device to be wired with resistors rated
R
V
= 820
and
R
EXT
= 4.4 k
with
2 %
tolerance and 200 ppm TK. The input device has the following characteristics:
Minimization of power dissipation due to constant current characteristic
Inputs protected against reverse polarity and transient overvoltages
Status LED output for each input
Digital averaging of the input signals to suppress interference pulses
Serial output of the detected signals (cascadable)
Maximum voltage ratings at inputs D0 ... D7 within test circuit 2.
The rated voltage may be applied to all inputs simultaneously.
The values given in the table may be regarded as guaranteed, but are only checked as
part of a qualification (no 100 % series testing).
Within the application circuit given the same voltage ratings as above apply for the
supply line.
1)
Non-destructive in temperature range 15
C
T
A
35
C.
2)
In temperature range 15
C
T
A
35
C:
Data retained if the supply voltage remains within the operating range; without supply voltage
non-destructive.
Voltage Range
Notes
DC voltage
3 V ... + 32 V
32 V ... + 32 V
full function
non-destructive, no latch-up
Overvoltage 500 ms
3 V ... + 35 V
35 V ... + 35 V
full function
non-destructive, no latch-up
Overvoltage 1.3 ms
to VDE 0160
3 V ... + 55 V
55
full function
non-destructive, no latch-up
Surge pulse 50
s
to IEC 801-5,
Z
i
= 2
0.5 kV
1)
Burst pulse 50 ns
to IEC 801-4,
Z
i
= 50
2 kV
2)
FZE 1658G
Semiconductor Group
5
Circuit Description
In IEC 65A, the following values are specified for 24-VDC input stages of type 2:
The current in the input circuit is determined by the switching element in state "0" and by
characteristics of the input stage in state "1".
The octal input device FZE 1658G is intended for a configuration comprising two
specified external resistors per channel, as shown in the block diagram. As a result the
power dissipation within the P-DSO-24-1 package is at a minimum.
The voltage dependent current through the external resistor
R
EXT
is compensated by a
negative differential resistance of the current sink across pins E and L, therefore input D
behaves like a constant current sink.
The comparator assigns level 1 or 0 to the voltage present at input E. To improve
interference protection, the comparator is provided with hysteresis and a delay element.
A status LED is connected in series with the input circuit (
R
EXT
and current sink). The
LED drive short-circuits the status LED if the comparator detects "0". A constant current
sink in parallel with the LED reduces the operating current of the LED, and a voltage
limiter ensures that the input circuit remains operational if the LED is interrupted. The
specified switching thresholds may change if the LED is interrupted.
For each channel a digital filter is provided which samples the comparator signal at a rate
provided by the clock oscillator. The digital filter is designed as a 5-section shift register.
If any four out of 5 sampling values are identical, the output S changes to the
corresponding state.
On a falling edge at input LO-N, the parallel data S0 - S7 are clocked into the output shift
register. The data can be shifted out serially to the output SO-N by the clock signal T,
with a "1" at the input being represented by a L-signal at the output SO-N. The serial
interface of the shift register fits the synchronous interface of the 8051 microcontroller
(see diagram Serial Data Output Function). By connecting output SO-N to input SE-
N of the next device, several FZE 1658G can be cascaded (see Application Circuit).
SO-N is designed as an open-drain output. SE-N has an internal pull-up current source.
Inputs SE-N, T and SO-N have Schmitt trigger characteristics. The device has separate
ground pins for the input circuitry (GND) and for the logic (DGND). If the supply voltage
falls below
V
USR
or CT is connected to DGND, the output shift register will be cleared and
the output SO-N disabled. If the supply voltage is too low, the LED drives will also be
disabled, i.e. the LED lights as soon as current flows in the input circuit.
Level
Input Voltage
Input Current
1
0
min. 11 V
max. 11 V
or max. 5 V
min. 6 mA
max. 2 mA
FZE 1658G
Semiconductor Group
6
Block Diagram
FZE 1658G
Semiconductor Group
7
Absolute Maximum Ratings
T
j
= 40 to 150
C
Parameter
Symbol
Limit Values
Unit
Notes
min.
max.
Transient input current
inputs I0 - I7
I
I
0.6
1.2
2.5
0.6
1.2
2.5
A
A
A
t
50 %
50
s
t
50 %
1.2
s
t
50 %
50 ns
Ground current
I
GND
5
10
5
10
A
A
t
50 %
50
s
t
50 %
50 ns
Junction temperature
T
j
40
150
C
Storage temperature
T
S
50
125
C
Thermal resistance
System/air
R
thja
95
K/W
soldered-in
Transient thermal resistance;
Same current through all
inputs I0 - I7
Z
th
Z
th
0.15
0.4
K/W
K/W
50
s pulse
120
s pulse
Supply voltage
V
S
0.3
65
V
Ground offset DGND to GND
V
DGND
4
4
V
V
DGND
<
V
S
Current at the LED outputs
I
L
15
500
250
125
15
500
250
125
mA
mA
mA
mA
t
50 %
50
s
t
50 %
1.2
s
t
50 %
50
s
Voltage at
T, LO-N, SO-N, SE-N
V
LOG
4
0.3
9
9
V
V
referred to DGND
Capacitance at CT
C
CT
2
F
when
V
S
falls
below
V
CT
ESD voltage 100 pF / 1.5 k
V
ESD
1000
1000
V
MIL Std. 883
Meth. 3015
All voltages are, unless otherwise specified, referred to GND. This also applies to the
operating range and the characteristics.
FZE 1658G
Semiconductor Group
8
1)
Input voltages may rise before the supply voltage.
Full function at
V
S
>
V
VSRO
(see Characteristics).
2)
Limits GND potential difference at minimum supply voltage.
3)
Also applies to several cascaded FZE 1658G (note dependence with clock frequency).
For definition of timing items, see timing diagram.
Operating Range
Parameter
Symbol
Limit Values
Unit
Notes
min.
max.
Supply voltage
V
S
10
48
V
Note power
dissipation
1)
Supply voltage rise
SR
VS
0.1
1
V/
s
Supply voltage
V
S
-
V
DGND
9
V
2)
GND potential difference
V
DGND
1.5
1.5
V
Input terminal current
I
IT
10
10
mA
Input voltage SE-N, T, LO-N
V
IH
V
IL
2.8
0.5
6
1.7
V
V
Input current SE-N, T, LO-N
I
I
1
1
mA
Clamp current
Junction temperature
T
j
25
150
C
Ambient temperature
T
A
25
105
C
Dependent on
R
th
Clock frequency
f
T
1
MHz
Clock pulse width H or L
t
TH
,
t
TL
300
ns
SE-N set up time to T
t
VSE
300
ns
LO-N set up time to T
t
VLO
1.2
s
SE-N, LO-N, T rise and fall time
within thresholds
t
r
,
t
f
3
s
3)
FZE 1658G
Semiconductor Group
9
Characteristics
V
S
= 15 V to 30 V;
V
DGND
= 0,
T
j
= 25
C <
T
j
< 125
C
Parameter
Symbol
Limit Values
Unit
Test Condition Test
Circuit
min.
typ.
max.
Inputs I0 - I7 or D0 - D7 Respectively
Switching
threshold H
V
DH
10.85
1)
V
2
Switching
threshold L
V
DL
8
V
V
L
2.2 V
2
Hysteresis
V
DHY
1
V
V
L
2.2 V
2
Switching
threshold L
I
DLL
2.5
mA
I
LED
= 0
2
Input current
I
DH
6.2
1)
8
mA
V
L
3.5 V,
V
D
= 11 ... 30 V
2
Input current
I
DL
5
7
mA
V
L
=
V
LL
,
V
D
= 5 V
2
Input current
I
IC +
1
mA
V
I
= 30 V
2)
1
Input clamp voltage
V
IT +
35
75
V
I
I
= 10 mA,
T
j
= 25
C
2)
1
Input current
I
IC
1
mA
V
I
= 30 V
2)
1
Input clamp voltage
V
IT
75
35
V
I
I
= 10 mA,
T
j
= 25
C
2)
1
1)
Headroom to IEC 65 A for tolerance of ext. resistor.
2)
Also valid at
V
S
= 0.
FZE 1658G
Semiconductor Group
10
LED Drive L0 - L7
Open-load voltage
V
LO
3.5
5
V
V
D
= 24 V,
I
LED
= 0
2
"Low"- voltage
V
LL
0
0.75
V
V
D
= 5 V,
I
LED
= 0
2
Output current
I
LED
3
5
mA
V
D
= 11 ... 30 V,
V
L
= 1.5 ... 3 V
2
Output current
I
LED
1.5
6
mA
V
D
= 11 ... 30 V,
V
L
= 1.2 ... 3.5 V
2
Power down
output current
I
L
0.12
mA
V
S
<
V
VSRU
1
Propagation delay
rising and falling
edge
t
DL
7.5
75
s
V
D
= 12 V
7 V
2
Oscillator
CT source/sink
current
I
CT
150
250
A
1
Frequency
f
CT
1
1.5
kHz
C
T
= 39 nF
2
Upper switching
threshold
V
CTP
3.3
4.3
V
2
Lower switching
threshold
V
CTN
1.4
2.2
V
2
Reset threshold
V
CTR
0.8
1.4
V
1
Reset input current
I
CTR
300
150
A
V
CT
= 0.8 V
1
Signal delay
t
DFI
2
4
ms
C
T
= 39 nF
2
Characteristics (cont'd)
V
S
= 15 V to 30 V;
V
DGND
= 0,
T
j
= 25
C <
T
j
< 125
C
Parameter
Symbol
Limit Values
Unit
Test Condition Test
Circuit
min.
typ.
max.
FZE 1658G
Semiconductor Group
11
5-V Logic
Input current
T, LO-N
I
I
10
10
A
V
i
= 0 ... 5 V
1
Input current SE-N
I
ISE
600
400
A
V
i
= 0 ... 3 V
1
Input current
T, LO-N, SE-N
I
I0
0
20
A
V
i
= 0 ... 5 V
V
S
= 0 V
1
Input capacitance
C
I
10
pF
1
L-output current
SO-N
I
SOL
5.5
8
mA
V
Q
= 3 ... 5 V
1
L-output level SO-N
V
SOL
0
0.5
V
I
SO
= 2 mA
1
H-leakage current
SO-N
I
SOH
0
50
A
V
SO
= 5 V
1
Output
capacitance SO-N
C
SOH
20
pF
V
SO
= 1.5 V
1
Rise/fall time of
output current
SO-N
t
rSO
,
t
fSO
50
ns
V
SO
= 2.5 V
1
Delay time
T to SO-N
(see timing
diagram)
t
SOT
150
ns
V
SO
= 2.5 V
1
Delay time
LO-N to SO-N
(see timing
diagram)
t
SOLO
300
ns
V
SO
= 2.5 V
1
Hysteresis SE-N,
LO-N
60
mV
no 100% testing
Characteristics (cont'd)
V
S
= 15 V to 30 V;
V
DGND
= 0,
T
j
= 25
C <
T
j
< 125
C
Parameter
Symbol
Limit Values
Unit
Test Condition Test
Circuit
min.
typ.
max.
FZE 1658G
Semiconductor Group
12
Hysteresis
Clock input
200
mV
no 100% testing
Voltage Supply
Current drain static
I
S
2
5
mA
V
S
= 10 ... 30 V
V
LO-N
= 5 V
V
T
= 5 V
I
SE-N
= 0
2
Current drain
during serial
readout
I
S
2
6
mA
V
S
= 10 ... 40 V
V
LO-N
= 0 V
f
T
= 1 MHz
2
Current drain
during high supply
voltage
I
SMAX
7
mA
V
S
< 45 V
2
Logic ground
current
I
DGND
2.5
0
mA
V
DGND
=
1.5 ... 1.5 V,
LO-N = H
1
Under voltage
lockout
V
VSRO
V
VSRU
V
VSRH
8
0.2
10
V
V
V
upper switching
treshold
lower switching
threshold
hysteresis
2
2
2
Characteristics (cont'd)
V
S
= 15 V to 30 V;
V
DGND
= 0,
T
j
= 25
C <
T
j
< 125
C
Parameter
Symbol
Limit Values
Unit
Test Condition Test
Circuit
min.
typ.
max.
FZE 1658G
Semiconductor Group
13
Test Circuit 1
Test Circuit 2
FZE 1658G
Semiconductor Group
14
Application Circuit
Supply Voltage Decoupling Circuit
Cascading Multiple FZE 1658G
FZE 1658G
Semiconductor Group
15
Serial Data Output Function
FZE 1658G
Semiconductor Group
16
Timing Diagram
FZE 1658G
Semiconductor Group
17
Input Characteristic with Worst-Case
Values per IEC 65A Input D Rest Circuit D
FZE 1658G
Semiconductor Group
18
Package Outlines
GPS05144
Plastic-Package, P-DSO-24-1 (SMD)
(Plastic Dual Small Outline Package)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book "Package Information".
Dimensions in mm
SMD = Surface Mounted Device
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