Semiconductor Group 1 1.96

1 048 576 words by 16-bit organization

0 to 70 °C operating temperature

Performance:

Single + 3.3 V (

0.3 V) supply

Low power dissipation
max. 720 active mW ( HYB3118160BSJ/BST-50)
max. 648 active mW ( HYB3118160BSJ/BST-60)
max. 576 active mW ( HYB3118160BSJ/BST-70)
max. 360 active mW ( HYB3116160BSJ/BST-50)
max. 324 active mW ( HYB3116160BSJ/BST-60)
max. 288 active mW ( HYB3116160BSJ/BST-70)
7.2 mW standby (LV-TTL)
3.6 mW standby (LV-CMOS)
720

W standby for L-version

Output unlatched at cycle end allows two-dimensional chip selection

Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh,
self refresh

Fast page mode capability

2 CAS / 1 WE

All inputs, outputs and clocks fully LV-TTL-compatible

1024 refresh cycles / 16 ms for HYB 3118160BSJ

4096 refresh cycles / 64 ms for HYB 3116160BSJ

Plastic Package:

P-SOJ-42-1 400 mil

P-TSOPII-50/44-1 400mil

-50

-60

-70

RAC

RAS access time

CAC

CAS access time

Access time from address

Read/Write cycle time

110

130

Fast page mode cycle time

1M x 16-Bit Dynamic RAM
(1k & 4k -Refresh)

Advanced Information

HYB3116160BSJ/BST(L)-50/-60/-70
HYB3118160BSJ/BST(L)-50/-60/-70

Semiconductor Group

HYB3116(8)160BSJ/BST(L)-50/-60/-70

3.3V 1M x 16-DRAM

The HYB 3116(8)160BSJ/BST is a 16 MBit dynamic RAM organized as 1 048 576 words by 16 bits.
The HYB 3116(8)160BSJ/BST utilizes a submicron CMOS silicon gate process technology, as well
as advanced circuit techniques to provide wide operating margins, both internally and for the system
user. Multiplexed address inputs permit the HYB 3116(8)160BSJ/BST to be packaged in standard
SOJ-42 and TSOPII-50/44 plastic package with 400mil width. These packages provide high system
bit densities and are compatible with commonly used automatic testing and insertion equipment.
System-oriented features include single + 3.3 V (

0.3 V) power supply, direct interfacing with high-

performance logic device families.The HYB3116160BSTL parts have a very low power ,,sleep
mode" suppported by Self Refresh.

Ordering Information

Pin Names

Type

Ordering Code

Package

Descriptions

HYB 3116160BSJ-50

on request

P-SOJ-42 400 mil

DRAM (access time 50 ns)

HYB 3116160BSJ-60

on request

P-SOJ-42 400 mil

DRAM (access time 60 ns)

HYB 3116160BSJ-70

on request

P-SOJ-42 400 mil

DRAM (access time 70 ns)

HYB 3118160BSJ-50

on request

P-SOJ-42 400 mil

DRAM (access time 50 ns)

HYB 3118160BSJ-60

on request

P-SOJ-42 400 mil

DRAM (access time 60 ns)

HYB 3118160BSJ-70

on request

P-SOJ-42 400 mil

DRAM (access time 70 ns)

HYB 3116160BST-50

on request

P-TSOPII-50/44 400 mil

DRAM (access time 50 ns)

HYB 3116160BST-60

on request

P-TSOPII-50/44 400 mil

DRAM (access time 60 ns)

HYB 3116160BST-70

on request

P-TSOPII-50/44 400 mil

DRAM (access time 70 ns)

HYB 3118160BST-50

on request

P-TSOPII-50/44 400 mil

DRAM (access time 50 ns)

HYB 3118160BST-60

on request

P-TSOPII-50/44 400 mil

DRAM (access time 60 ns)

HYB 3118160BST-70

on request

P-TSOPII-50/44 400 mil

DRAM (access time 70 ns)

A0 to A9

Row Address Inputs for 1k-refresh version HYB3118160BSJ/BST

A0 to A9

Column Addess Inputs for 1k-refresh version HYB3118160BSJ/BST

A0 to A11

Row Address Inputs for 4k-refresh version HYB3116160BSJ/BST

A0 to A7

Column Address Inputs for 4k-refresh version HYB3116160BSJ/BST

RAS

Row Address Strobe

Output Enable

I/O1-I/O16

Data Input/Output

UCAS

Upper Column Address Strobe

LCAS

Lower Column Address Strobe

Read/Write Input

Power Supply (+ 3.3 V)

Ground (0 V)

N.C.

not connected

Semiconductor Group

HYB3116(8)160BSJ/BST(L)-50/-60/-70

3.3V 1M x 16-DRAM

Truth Table

RAS

LCAS

UCAS

I/O1-I/O8

I/O9-I/O16

Operation

High-Z

Dout

High-Z

Dout

Din

Don't care

Din

High-Z

Dout

Don't care

Din

High-Z

Standby

Refresh

Lower byte read

Upper byte read

Word read

Lower byte write

Upper byte write

Word write

NOP

P-SOJ-42 (400 mil)

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21

Vcc
I/O1
I/O2
I/O3
I/O4
Vcc
I/O5
I/O6
I/O7
I/O8
N.C.
N.C.
WE
RAS

A11/NC
A10/NC

A0
A1
A2
A3
Vcc

42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22

Vss
I/O16
I/O15
I/O14
I/O13
Vss
I/O12
I/O11
I/O10
I/O9
N.C.
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
Vss

Vcc
I/O1
I/O2
I/O3
I/O4
Vcc
I/O5
I/O6
I/O7
I/O8
N.C.

N.C.
N.C.
WE
RAS

A11/N.C.
A10.N.C.

A0
A1
A2
A3
Vcc

1
2
3
4
5
6
7
8
9
10
11

15
16
17
18
19
20
21
22
23
24
25

50
49
48
47
46
45
44
43
42
41
40

36
35
34
33
32
31
30
29
28
27
26

Vss
I/O16
I/O15
I/O14
I/O13
Vss
I/O12
I/O11
I/O10
I/O9
N.C.

N.C.
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
Vss

P-TSOPII-50/44 (400mil)

*) A11 and A10 are not connected for HYB3118160BSJ/BST (1k-refresh version)

Semiconductor Group

HYB3116(8)160BSJ/BST(L)-50/-60/-70

3.3V 1M x 16-DRAM

Absolute Maximum Ratings

Operating temperature range ............................................................................................0 to 70 °C

Storage temperature range......................................................................................... 55 to 150 ° C

Soldering time.............................................................................................................................10 s

Input/output voltage ................................................................................-0.5 to min (Vcc+0.5,4.6) V

Power supply voltage..................................................................................................-0.5 V to 4.6 V

Power dissipation..................................................................................................................... 1.0 W

Data out current (short circuit) ................................................................................................ 50 mA

Note:

Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of
the device. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.

DC Characteristics (values in brackets for HYB3116160BSJ)

= 0 to 70 °C,

= 0 V,

= 3.3 V

0.3 V,

= 5 ns

Parameter

Symbol

Limit Values

Unit Test

Condition

min.

max.

Input high voltage

2.0

Vcc+0.5

Input low voltage

0.5

0.8

TTL Output high voltage (

OUT

= 2 mA)

2.4

TTL Output low voltage (

OUT

= 2 mA)

0.4

CMOS Output high voltage (

OUT

= 100

Vcc-0.2

CMOS Output low voltage (

OUT

= 100

0.2

Input leakage current,any input
(0 V

Vcc + 0.3V, all other pins = 0 V)

I(L)

Output leakage current
(DO is disabled, 0 V

OUT

Vcc + 0.3V)

O(L)

Average

supply current:

-50 ns version
-60 ns version
-70 ns version

(RAS, CAS, address cycling,

min.

)

CC1

200(100)
180 (90)
160 (80)

mA
mA
mA

2) 3) 4)

Standby

supply current (RAS = CAS =

)

CC2

Semiconductor Group

HYB3116(8)160BSJ/BST(L)-50/-60/-70

3.3V 1M x 16-DRAM

Average

supply current, during RAS-only

refresh cycles:

-50 ns version
-60 ns version
-70 ns version

(RAS cycling: CAS =

min.

)

CC3

200(100)
180 (90)
160 (80)

mA
mA
mA

2) 4)

Average

supply current,

during fast page mode:

-50 ns version
-60 ns version
-70 ns version

(RAS =

, CAS, address cycling,

min.

)

CC4

55 (40)
50 (35)
45 (30)

mA
mA
mA

2) 3) 4)

Standby

supply current

(RAS = CAS =

0.2 V)

CC5

Standby

supply current (L-version)

(RAS = CAS =

0.2 V)

CC5

200

Average

supply current, during CAS-

before-RAS refresh mode: -50 ns version

-60 ns version
-70 ns version

(RAS, CAS cycling,

min.)

CC6

200(100)
180 (90)
160 (80)

mA
mA
mA

2) 4)

Average Self Refresh Current

(CBR cycle with tRAS>TRASSmin., CAS held low,
WE=Vcc-0.2V, Address and Din=Vcc--0.2V or 0.2V)

CC7

1
250

L-version

Capacitance

= 0 to 70 °C,

= 3.3 V

0.3 V,

= 1 MHz

Parameter

Symbol

Limit Values

Unit

min.

max.

Input capacitance (A0 to A11)

Input capacitance (RAS, UCAS, LCAS, WE, OE)

I/O capacitance (I/O1-I/O16)

DC Characteristics (values in brackets for HYB3116160BSJ)

(cont'd)

= 0 to 70 °C,

= 0 V,

= 3.3 V

0.3 V,

= 5 ns

Parameter

Symbol

Limit Values

Unit Test

Condition

min.

max.

Semiconductor Group

HYB3116(8)160BSJ/BST(L)-50/-60/-70

3.3V 1M x 16-DRAM

AC Characteristics

5)6)

16F

= 0 to 70 °C,

= 3.3 V

0.3 V,

= 5 ns

Parameter

Symbol

Limit Values

Unit

Note

-50

-60

-70

min.

max. min.

max.

common parameters

Random read or write cycle time

110

130

RAS precharge time

RAS pulse width

RAS

10k

CAS pulse width

CAS

10k

Row address setup time

ASR

Row address hold time

RAH

Column address setup time

ASC

Column address hold time

CAH

RAS to CAS delay time

RCD

RAS to column address delay
time

RAD

RAS hold time

RSH

CAS hold time

CSH

CAS to RAS precharge time

CRP

Transition time (rise and fall)

Refresh period for HYB3118160

REF

Refresh period for HYB3116160

REF

Refresh period for L-versions

REF

256

Read Cycle

Access time from RAS

RAC

8, 9

Access time from CAS

CAC

8, 9

Access time from column address

8,10

OE access time

OEA

Column address to RAS lead time

RAL

Read command setup time

RCS

Read command hold time

RCH

Read command hold time
referenced to RAS

RRH

Semiconductor Group

HYB3116(8)160BSJ/BST(L)-50/-60/-70

3.3V 1M x 16-DRAM

CAS to output in low-Z

CLZ

Output buffer turn-off delay

OFF

Output buffer turn-off delay from
OE

OEZ

Data to OE low delay

DZO

CAS high to data delay

CDD

OE high to data delay

ODD

Write Cycle

Write command hold time

WCH

Write command pulse width

Write command setup time

WCS

Write command to RAS lead time

RWL

Write command to CAS lead time

CWL

Data setup time

Data hold time

Data to CAS low delay

DZC

Read-Modify-Write Cycle

Read-write cycle time

RWC

126

150

180

RAS to WE delay time

RWD

CAS to WE delay time

CWD

Column address to WE delay time

A WD

OE command hold time

OEH

Fast Page Mode Cycle

Fast page mode cycle time

CAS precharge time

Access time from CAS precharge

CPA

RAS pulse width

RAS

200k

200k 70

200k

AC Characteristics

(cont'd)

5)6)

16F

= 0 to 70 °C,

= 3.3 V

0.3 V,

= 5 ns

Parameter

Symbol

Limit Values

Unit

Note

-50

-60

-70

min.

max. min.

max.

Semiconductor Group

HYB3116(8)160BSJ/BST(L)-50/-60/-70

3.3V 1M x 16-DRAM

CAS precharge to RAS Delay

RHPC

Fast Page Mode Read-Modify-Write Cycle

Fast page mode read-write cycle
time

PRWC

CAS precharge to WE

CPWD

CAS-before-RAS Refresh Cycle

CAS setup time

CSR

CAS hold time

CHR

RAS to CAS precharge time

RPC

Write to RAS precharge time

WRP

Write hold time referenced to RAS

WRH

CAS-before-RAS Counter Test Cycle

CAS precharge time

CPT

Self Refresh Cycle

RAS pulse width

RASS

100k

RAS precharge time

RPS

110

130

CAS hold time

CHS

-50

AC Characteristics

(cont'd)

5)6)

16F

= 0 to 70 °C,

= 3.3 V

0.3 V,

= 5 ns

Parameter

Symbol

Limit Values

Unit

Note

-50

-60

-70

min.

max. min.

max.

Semiconductor Group

HYB3116(8)160BSJ/BST(L)-50/-60/-70

3.3V 1M x 16-DRAM

Notes:

1) All voltages are referenced to VSS.

2) ICC1, ICC3, ICC4 and ICC6 depend on cycle rate.

3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open.

4) Address can be changed once or less while RAS = VIL. In the case of ICC4 it can be changed once or less

during a fast page mode cycle (tPC).

5) An initial pause of 200

s is required after power-up followed by 8 RAS cycles of which at least one cycle has

to be a refresh cycle, before proper device operation is achieved. In case of using internal refresh counter, a
minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.

6) AC measurements assume tT = 5 ns.

7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also

measured between VIH and VIL.

8) Measured with a load equivalent to 100 pF and at Voh=2.0 V (Ioh = -2mA) , Vol=0.8V (Iol=2mA).

9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a

reference point only: If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by
tCAC.

10)Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a

reference point only: If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by
tAA.

11)Either tRCH or tRRH must be satisfied for a read cycle.

12)tOFF (max.) and tOEZ (max.) define the time at which the outputs achieve the open-circuit condition and are

not referenced to output voltage levels.

13)Either tDZC or tDZO must be satisfied.

14)Either tCDD or tODD must be satisfied.

15)tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data

sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and the I/O pin
will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD
(min.), tAWD > tAWD (min.) and tCPWD > tCPWD (min.) , the cycle is a read-write cycle and I/O pins will
contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of
the I/O pins (at access time) is indeterminate.

16)These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge

in read-write cycles.

17)When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM

operation:

If row addresses are being refreshed on an evenly distributed manner over the refresh interval using CBR
refresh cycles, then only one CBR cycle must be performed immediately after exit from Self Refresh.

If row addresses are being refreshed in any other manner (ROR - Distributed/Burst; or CBR-Burst) over the
refresh interval, then a full set of row refreshes must be performed immediately before entry to and immediately
after exit from Self Refresh.

Semiconductor Group

HYB3116(8)160BSJ/BST(L)-50/-60/-70

3.3V 1M x 16-DRAM

Read Cycle

AAAA

AAA

AAAA

Row

Column

Row

AAAA

Valid Data Out

RAS

UCAS

Address

I/O
(Inputs)

I/O
(Outputs)

VIL

VOL

RAS

CSH

RAD

CAS

RAH

CRP

RSH

RCD

RAL

ASR

CAH

ASC

ASR

RCH

RRH

RCS

OEA

CLZ

CAC

OEZ

ODD

CDD

OFF

DZC

DZO

RAC

Hi Z

AAAA

AAA

"H" or "L"

WL1

LCAS

Semiconductor Group

HYB3116(8)160BSJ/BST(L)-50/-60/-70

3.3V 1M x 16-DRAM

Write Cycle (Early Write)

AAAA

RAS

UCAS

Address

I/O
(Inputs)

I/O
(Outputs)

VIL

VOL

RAS

CSH

RAD

CAS

CRP

RSH

RCD

RAL

ASR

CAH

ASR

AAAA

AAA

AAAA

AAA

AAAA

AAA

CWL

RWL

ASC

WCH

Valid Data In

Hi Z

Column

AAAA

Row

RAH

WCS

AAAA

AAA

"H" or "L"

WL2

LCAS

Semiconductor Group

HYB3116(8)160BSJ/BST(L)-50/-60/-70

3.3V 1M x 16-DRAM

Write Cycle (OE Controlled Write)

AAAA

AAA

AAAA

Valid Data

AAAA

RWL

OEH

ODD

CWL

AAAA

DZO

OEA

CLZ

OEZ

AAAA

AAA

AAAA

AAA

AAAA

Row

DZC

AAAA

"H" or "L"

Hi-Z

Column

Row

ASC

RAD

RAL

CAH

RAH

RAS

UCAS

Address

I/O
(Inputs)

I/O
(Outputs)

VIL

VOL

RAS

CSH

CAS

CRP

RSH

RCD

ASR

WL3

LCAS

Semiconductor Group

HYB3116(8)160BSJ/BST(L)-50/-60/-70

3.3V 1M x 16-DRAM

Read-Write (Read-Modify-Write) Cycle

AAA

AAAA

AAA

AAAA

AAA

AAAA

AAA

AAAA

AAA

AAAA

AAA

AAAA

Row

CSH

CAS

CRP

RWC

AWD

ASR

RAS

RAH

CAH

I/O
(Outputs)

I/O
(Inputs)

VIL

ASR

Column

RCD

RSH

RAD

CWD

OEH

RWD

RWL

CWL

CLZ

RCS

OEA

DZC

DZO

ODD

CAC

OEZ

Valid

Data in

Data

Out

RAC

AAAA

"H" or "L"

ASC

RAS

UCAS

Address

VIL

WL4

LCAS

Semiconductor Group

HYB3116(8)160BSJ/BST(L)-50/-60/-70

3.3V 1M x 16-DRAM

Fast Page Mode Read Cycle

AAAA

AAA

AAAA

AAA

AAAA

AAA

AAAA

AAA

AAAA

AAA

RASP

CAS

RCD

CSH

CAH

ASC

ASR

RAH

RAD

RCS

ASC

CAH

CAS

RSH

CRP

ASR

RCH

CPA

OEA

DZC

CDD

RRH

CPA

OEA

DZC

DZO

ODD

DZO

ODD

DZO

OFF

OEZ

OFF

OEZ

CAC

CLZ

OFF

RAC

CAC

Valid

Data Out

Valid

Column

Row

RAS

I/O
(Outputs)

I/O
(Inputs)

Address

UCAS

AAAA

"H" or "L"

RHCP

RCH

Column

FPM1

LCAS

Semiconductor Group

HYB3116(8)160BSJ/BST(L)-50/-60/-70

3.3V 1M x 16-DRAM

Fast Page Mode Early Write Cycle

AAAA

AAA

AAAA

AAA

AAAA

AAA

AAAA

AAA

AAAA

AAA

AAAA

AAA

AAAA

RAS

RSH

CAS

CRP

RAL

CAH

ASR

CWL

RWL

CAH

ASC

CWL

WCS

WCH

RAD

CAS

RCD

CAH

RAH

ASR

ASC

Column

Row

Valid

Data In

Valid

Data In

Column

HI-Z

RAS

I/O
(Outputs)

I/O
(Inputs)

Address

CAS

VIL

AAAA

AAA

"H" or "L"

FPM2

Semiconductor Group

HYB3116(8)160BSJ/BST(L)-50/-60/-70

3.3V 1M x 16-DRAM

Fast Page Mode Read-Modify- Write Cycle

AAAA

OEA

ASR

ASC

ASR

ASC

CWL

CWD

OEH

OEZ

OEA

OEZ

OEH

OEA

OEH

V OL

ts)

(Ou

t
p

ts)

t
a

lumn

ess

l
u

lumn

AAAA

AAA

" o

r

"
L

OEZ

Semiconductor Group

HYB3116(8)160BSJ/BST(L)-50/-60/-70

3.3V 1M x 16-DRAM

RAS-Only Refresh Cycle

AAAA

CRP

RAH

RAS

ASR

RPC

VIL

Row

HI-Z

Address

RAS

CAS

I/O
(Outputs)

AAAA

"H" or "L"

WL9

Semiconductor Group

HYB3116(8)160BSJ/BST(L)-50/-60/-70

3.3V 1M x 16-DRAM

CAS-Before-RAS Refresh Cycle

AAAA

AAA

AAAA

RAS

CRP

RPC

CHR

WRH

WRP

CSR

RPC

OFF

OEZ

CDD

ODD

VIL

HI-Z

AAAA

"H" or "L"

RAS

I/O
(Outputs)

I/O
(Inputs)

UCAS

WL10

LCAS

Semiconductor Group

HYB3116(8)160BSJ/BST(L)-50/-60/-70

3.3V 1M x 16-DRAM

Hidden Refresh Cycle (Read)

AAAA

AAA

RAS

I/O
(Outputs)

I/O
(Inputs)

Address

UCAS

RAS

CRP

CHR

RAD

CAH

ASC

RAH

ASR

RCS

RRH

DZC

DZO

CAC

RAC

CLZ

OEZ

OFF

ODD

CDD

RCD

RSH

OEA

VIL

WRP

WRH

AAAA

AAA

"H" or "L"

Valid Data Out

Row

Column

Row

HI-Z

VOL

WL11

LCAS

Semiconductor Group

HYB3116(8)160BSJ/BST(L)-50/-60/-70

3.3V 1M x 16-DRAM

Hidden Refresh Cycle (Early Write)

AAAA

AAA

AAAA

AAA

AAAA

AAA

AAAA

AAA

RAS

I/O

(Output)

I/O

(Input)

Address

UCAS

VIL

AAAA

"H" or "L"

RAS

RCD

RSH

RAD

CAH

WCS

WCH

ASR

RAH

ASR

CRP

CHR

RAS

ASC

Row

Valid Data

HI-Z

Column

WRP

WRH

WL12

LCAS

Semiconductor Group

HYB3116(8)160BSJ/BST(L)-50/-60/-70

3.3V 1M x 16-DRAM

CAS before RAS Self Refresh Cycle

AAAA

AAA

AAAA

RPS

RASS

CRP

RPC

WRH

WRP

CSR

OFF

OEZ

CDD

ODD

VIL

HI-Z

AAAA

"H" or "L"

RAS

I/O

(Outputs)

I/O

(Inputs)

CAS

CHS

WL13

Semiconductor Group

HYB3116(8)160BSJ/BST(L)-50/-60/-70

3.3V 1M x 16-DRAM

CAS-Before-RAS Refresh Counter Test Cycle

AAAA

AAA

AAAA

CSR

ASR

ASC

CHR

WRP

RAL

CAH

RSH

RAS

CAS

RCS

CDD

CAC

WRH

OEA

ODD

CLZ

DZC

DZO

OEZ

OFF

RWL

CWL

WCH

WCS

WRH

WRP

V IL

VOH

VOL

V IL

RAS

I/O
(Inputs)

Address

CAS

I/O
(Outputs)

I/O
(Inputs)

Column

Row

Data Out

Data In

HI-Z

Read Cycle:

Write Cycle:

RRH

RCH

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: HYB3118160BST-70

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: HYB3118160BST-70