Semiconductor Group
1
1998-10-01
2 097 152 words by 8-bit organization
0 to 70
C operating temperature
Fast Page Mode operation
Performance:
Power dissipation:
Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh
and test mode
All inputs, outputs and clocks fully TTL (5 V versions) and LV-TTL (3.3 V version)-compatible
2048 refresh cycles / 32 ms (2k-refresh)
Plastic Package:
P-SOJ-28-3 400 mil
-50
-60
t
RAC
RAS access time
50
60
ns
t
CAC
CAS access time
13
15
ns
t
AA
Access time from address
25
30
ns
t
RC
Read/Write cycle time
84
104
ns
t
PC
Fast page mode cycle time
35
40
ns
HYB5117800
HYB3117800
-50
-60
-50
-60
Power Supply
5
10%
3.3
0.3 V
Active
440
385
288
252
mW
TTL Standby
11
7.2
mW
CMOS Standby
5.5
3.6
mW
2M
8 - Bit Dynamic RAM
2k Refresh
(Fast Page Mode)
Advanced Information
HYB 5117800/BSJ-50/-60
HYB 3117800BSJ-50/-60
HYB 5(3)117800/BSJ-50/-60
2M
8 DRAM
Semiconductor Group
2
1998-10-01
The HYB 5(3)117800 are 16 MBit dynamic RAMs based on the die revisions "G" & "F" and
organized as 2 097 152 words by 8-bits. The HYB 5(3)117800 utilizes a submicron CMOS silicon
gate process technology, as well as advanced circuit techniques to provide wide operating margins,
both internally and for the system user. Multiplexed address inputs permit the HYB 5(3)117800 to
be packaged in a standard SOJ-28 plastic package. Package with 400 mil width are available.
These packages provide high system bit densities and are compatible with commonly used
automatic testing and insertion equipment.
Ordering Information
Type
Ordering Code
Package
Descriptions
HYB 5117800BSJ-50
Q67100-Q1092
P-SOJ-28-3 400 mil
5 V 50 ns FPM-DRAM
HYB 5117800BSJ-60
Q67100-Q1093
P-SOJ-28-3 400 mil
5 V 60 ns FPM-DRAM
HYB 3117800BSJ-50
on request
P-SOJ-28-3 400 mil
3.3 V 50 ns FPM-DRAM
HYB 3117800BSJ-60
on request
P-SOJ-28-3 400 mil
3.3 V 60 ns FPM-DRAM
Pin Names and Configuration
A0 - A10
Row Address Inputs
A0 - A9
Column Address Inputs
RAS
Row Address Strobe
OE
Output Enable
I/O1 - I/O8
Data Input/Output
CAS
Column Address Strobe
WE
Read/Write Input
V
CC
Power Supply
+ 5 V for HYB 5117800
+ 3.3 V for HYB 3117800
V
SS
Ground (0 V)
N.C.
Not Connected
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
A5
OE
I/O5
CAS
A0
A1
A2
I/O3
I/O4
WE
RAS
N.C.
A10
SS
V
CC
V
A9
I/O8
I/O7
SS
V
I/O1
I/O2
V
CC
A3
A6
A7
28
27
26
A8
I/O6
SPP02803
A4
P-SOJ-28 400 mil
HYB 5(3)117800/BSJ-50/-60
2M
8 DRAM
Semiconductor Group
3
1998-10-01
Block Diagram
SPB03456
&
No.2 Clock
Generator
Address
Column
Buffers (10)
Controller
Refresh
Refresh
Counter (11)
Buffers (11)
Row
Address
Generator
No.1 Clock
11
10
A0
A1
A2
A3
A4
A5
A6
A7
A8
11
Row
Decoder
RAS
2048 x 1024 x 8
Memory Array
2048
1024
x 8
Sense Amplifier
I/O Gating
10
Column
Decoder
Buffer
Data IN
Data OUT
Buffer
I/O1
8
8
OE
Voltage Down
V
CC
V
CC
11
4
A9
(internal)
Generator
CAS
WE
A10
I/O2
I/O8
HYB 5(3)117800/BSJ-50/-60
2M
8 DRAM
Semiconductor Group
4
1998-10-01
Absolute Maximum Ratings
Operating temperature range ........................................................................................... 0 to 70
C
Storage temperature range........................................................................................ 55 to 150
C
Input/output voltage (5 V versions) ................................................... 0.5 to min (
V
CC
+ 0.5, 7.0) V
Input/output voltage (3.3 V versions) ................................................ 0.5 to min (
V
CC
+ 0.5, 4.6) V
Power supply voltage (5 V versions) ....................................................................... 1.0 V to 7.0 V
Power supply voltage (3.3 V versions) .................................................................... 1.0 V to 4.6 V
Power dissipation (5 V versions) ............................................................................................. 1.0 W
Power dissipation (3.3 V versions) .......................................................................................... 0.5 W
Data out current (short circuit) ................................................................................................ 50 mA
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage of the device. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
DC Characteristics
T
A
= 0 to 70
C,
V
SS
= 0 V,
t
T
= 2 ns
Parameter
Symbol
Limit Values
Unit Test
Condition
min.
max.
5 V Versions
Power supply voltage
V
CC
4.5
5.5
V
Input high voltage
V
IH
2.4
V
CC
+ 0.5 V
1
Input low voltage
V
IL
0.5
0.8
V
1
Output high voltage (
I
OUT
= 5 mA)
V
OH
2.4
V
1
Output low voltage (
I
OUT
= 4.2 mA)
V
OL
0.4
V
1
3.3 V Versions
Power supply voltage
V
CC
3.0
3.6
V
Input high voltage
V
IH
2.0
V
CC
+ 0.5 V
1
Input low voltage
V
IL
0.5
0.8
V
1
TTL Output high voltage (
I
OUT
= 2 mA)
V
OH
2.4
V
1
TTL Output low voltage (
I
OUT
= 2 mA)
V
OL
0.4
V
1
CMOS Output high voltage (
I
OUT
= 100
A)
V
OH
V
CC
0.2
V
CMOS Output low voltage (
I
OUT
= 100
A)
V
OL
0.2
V
HYB 5(3)117800/BSJ-50/-60
2M
8 DRAM
Semiconductor Group
5
1998-10-01
DC Characteristics (cont'd)
T
A
= 0 to 70
C,
V
SS
= 0 V,
t
T
= 2 ns
Parameter
Symbol
Limit Values
Unit Test
Condition
min.
max.
Common Parameters
Input leakage current
(0 V
V
IH
V
CC
+ 0.3 V, all other pins = 0 V)
I
I(L)
10
10
A
1
Output leakage current
(DO is disabled, 0 V
V
OUT
V
CC
+ 0.3 V)
I
O(L)
10
10
A
1
Average
V
CC
supply current
-50 ns version
-60 ns version
(RAS, CAS, address cycling:
t
RC
=
t
RC MIN.
)
I
CC1
80
70
mA
mA
2, 3, 4
2, 3, 4
Standby
V
CC
supply current (RAS = CAS =
V
IH
)
I
CC2
2
mA
Average
V
CC
supply current, during RAS-only
refresh cycles
-50 ns version
-60 ns version
(RAS cycling, CAS =
V
IH
,
t
RC
=
t
RC MIN.
)
I
CC3
80
70
mA
mA
2, 4
2, 4
Average
V
CC
supply current,
during fast page mode
-50 ns version
-60 ns version
(RAS =
V
IL
, CAS, address cycling:
t
PC
=
t
PC MIN.
)
I
CC4
25
20
mA
mA
2, 3,) 4
2, 3, 4
Standby
V
CC
supply current
(RAS = CAS =
V
CC
0.2 V)
I
CC5
1
mA
1
Average
V
CC
supply current, during CAS-
before-RAS refresh mode
-50 ns version
-60 ns version
(RAS, CAS cycling:
t
RC
=
t
RC MIN.
)
I
CC6
80
70
mA
mA
2, 4
2,) 4
Capacitance
T
A
= 0 to 70
C,
V
CC
= 5 V
10 %,
f
= 1 MHz
Parameter
Symbol
Limit Values
Unit
min.
max.
Input capacitance (A0 to A10)
C
I1
5
pF
Input capacitance (RAS, CAS, WE, OE)
C
I2
7
pF
I/O capacitance (I/O1 to I/O8)
C
IO
7
pF
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