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Электронный компонент: Q62702-F1628

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BF 1009S
Semiconductor Group
1
Au -25-1998
Silicon N-Channel MOSFET Tetrode
For low noise, high gain controlled
input stages up to 1GHz
Operating voltage 9V
Integrated bias network
ESD: Electrostatic discharge sensitive device, observe handling precaution!
Type
Marking
Pin Configuration
Package
Ordering Code
3 = G2
Q62702-F1628
1 = S
JLs
4 = G1
SOT-143
BF 1009S
2 = D
Maximum Ratings
Parameter
Symbol
Value
Unit
V
DS
12
Drain-source voltage
V
mA
25
I
D
Continuos drain current
Gate 1/gate 2 peak source current
10
I
G1/2SM
+
V
G1SE
3
Gate 1 (external biasing)
V
mW
P
tot
Total power dissipation,
T
S
76 C
200
Storage temperature
C
-55 ...+150
T
stg
T
ch
150
Channel temperature
Thermal Resistance
370
K/W
Channel - soldering point
R
thchs
Note:
It is not recommended to apply external DC-voltage on Gate 1 in active mode.
Semiconductor Group
1
1998-11-01
BF 1009S
Semiconductor Group
2
Au -25-1998
Electrical Characteristics at
T
A
= 25C, unless otherwise specified.
Parameter
Symbol
Values
Unit
min.
typ.
max.
DC characteristics
Drain-source breakdown voltage
I
D
= 300 A, -
V
G1S
= 4 V, -
V
G2S
= 4 V
V
-
V
(BR)DS
-
16
Gate 1 source breakdown voltage
I
G1S
= 10 mA,
V
G2S
=
V
DS
= 0
-
12
V
(BR)G1SS
8
Gate 2 source breakdown voltage
I
G2S
= 10 mA,
V
G1S
= 0 V,
V
DS
= 0 V
-
16
10
V
(BR)G2SS
Gate 1 source current
V
G1S
= 6 V,
V
G2S
= 0 V
-
-
A
60
+
I
G1SS
Gate 2 source leakage current
V
G2S
= 8 V,
V
G1S
= 0 V,
V
DS
= 0 V
I
G2SS
-
-
nA
50
I
DSS
-
500
A
-
Drain current
V
DS
= 9 V,
V
G1S
= 0 ,
V
G2S
= 6 V
I
DSO
10
14
Operating current (selfbiased)
V
DS
= 9 V,
V
G2S
= 6 V
mA
19
V
G2S(p)
-
0.9
-
V
Gate 2-source pinch-off voltage
V
DS
= 9 V,
I
D
= 100 A
AC characteristics
Forward transconductance (self biased)
V
DS
= 9 V,
V
G2S
= 6 V,
f = 1 kHz
g
fs
26
30
-
mS
Gate 1-input capacitance (self biased)
V
DS
= 9 V,
V
G2S
= 6 V,
f = 1 MHz
C
g1ss
-
2.1
2.7
pF
Output capacitance (self biased)
V
DS
= 9 V,
V
G2S
= 6 V,
f = 100 MHz
C
dss
-
0.9
-
Power gain (self biased)
V
DS
= 9 V,
V
G2S
= 6 V,
f = 800 MHz
G
ps
18
22
-
dB
Noise figure (self biased)
V
DS
= 9 V,
V
G2S
= 6 V,
f = 800 MHz
F
800
-
1.4
-
Gain control range (self biased)
V
DS
= 9 V,
V
G2S
= 1 V,
f = 800 MHz
G
ps
40
50
-
Semiconductor Group
2
1998-11-01
BF 1009S
Semiconductor Group
3
Au -25-1998
Total power dissipation
P
tot
=
f (T
S
)
0
20
40
60
80
100
120 C
150
T
S
0
50
100
150
200
mW
300

P
tot
Drain current
I
D
=
f (V
G2S
)
0.0
1.0
2.0
3.0
4.0
V
6.0
V
G2S
0
1
2
3
4
5
6
7
8
9
10
11
12
mA
15

I
D
Forward transfer admittance
|
Y
21
| =
f (V
G2S
)
0.0
1.0
2.0
3.0
4.0
V
6.0
V
G2S
0
2
4
6
8
10
12
14
16
18
20
22
24
mS
28
|
Y
21
|
Insertion power gain
|
S
21
|
2
=
f (V
G2S
)
0.0
1.0
2.0
3.0
4.0
V
6.0
V
G2S
-60
-55
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
dB
10

| S
21
|
2
Semiconductor Group
3
1998-11-01
BF 1009S
Semiconductor Group
4
Au -25-1998
Gate 1 input capacitance
C
g1ss
=
f (V
g2s
)
f = 200MHz
0.0
1.0
2.0
3.0
4.0
V
6.0
V
G2S
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
pF
3.0

C
g1ss
Output capacitance
C
dss
=
f (V
G2
)
f = 200MHz
0.0
1.0
2.0
3.0
4.0
V
6.0
V
G2S
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
pF
3.0

C
dss
Semiconductor Group
4
1998-11-01