Data Sheet 04.95
ICs for Communications
Primary Rate Access Clock Generator and Transceiver
PRACT
PEB 22320
Version 2.1
Data Classification
Maximum Ratings
Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible
damage to the integrated circuit.
Characteristics
The listed characteristics are ensured over the operating range of the integrated circuit. Typical
characteristics specify mean values expected over the production spread. If not otherwise specified,
typical characteristics apply at
T
A
= 25
C and the given supply voltage.
Operating Range
In the operating range the functions given in the circuit description are fulfilled.
For detailed technical information about "Processing Guidelines" and "Quality Assurance" for
ICs, see our Product Overview "ICs for Communications"
PEB 22320
Revision History
Current Version: 04.95
Previous Version:
05.93
Page
Subjects (changes since last revision)
10
Architecture of the PRACT
14
Input Jitter Specification
16
Jitter Attenuator Block Diagram
17
Clock- and Synchronization Table
18
Jitter Attenuation Characteristics
23
Master/Slave Selection
24
Reset
28
Delay Times
29
DC Characteristics
31
Recommended Oscillator Circuits
32, 33
Crystal Tuning Range
PEB 22320
General Information
Table of Contents
Page
Semiconductor Group
3
1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.1
Pin Configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
1.2
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
1.3
System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
2
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.1
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
2.1.1
Basic Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
2.1.2
Clock and Data Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
2.1.3
Input Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2.1.4
Jitter Attenuator and Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
2.2
Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
2.2.1
Basic Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
2.2.2
Output Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
2.3
Local Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
2.4
Remote Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
2.5
Bypass Jitter Attenuator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
2.6
Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
2.7
Receiver Loss of Signal Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
2.8
Master/Slave Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
3
Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
3.1
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
3.1.1
Reset with CS Pin Fixed to
V
SS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
3.1.2
Reset Using CS Pin to Latch Programming (a controller is used) . . . . . . . . .26
3.2
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
4
Electrical Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
4.1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
4.2
Delay Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
4.2.1
Delay from XDIP/XDIN to XL1/XL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
4.2.2
Delay from RL1/RL2 to RDOP/RDON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
4.3
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
4.4
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
4.5
Recommended Oscillator Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
4.6
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
4.6.1
Dual Rail Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
4.6.2
System Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
4.6.3
Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
4.6.4
XTAL Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
PEB 22320
Semiconductor Group
4
4.7
Pulse Templates - Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
4.8
Overvoltage Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
5
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
IOM
, IOM
-1, IOM
-2, SICOFI
, SICOFI
-2, SICOFI
-4, SICOFI
-4C, SLICOFI
, ARCOFI
, ARCOFI
-BA,
ARCOFI
-SP, EPIC
-1, EPIC
-S, ELIC
, IPAT
-2, ITAC
, ISAC
-S, ISAC
-S TE, ISAC
-P, ISAC
-P TE, IDEC
,
SICAT
, OCTAT
-P, QUAT
-S are registered trademarks of Siemens AG.
MUSAC
TM
-A, FALC
TM
54, IWE
TM
, SARE
TM
, UTPT
TM
, ASM
TM
, ASP
TM
are trademarks of Siemens AG.
Purchase of Siemens
I
2
C components conveys a license under the Philips'
I
2
C patent to use the components in
the
I
2
C-system provided the system conforms to the
I
2
C specifications defined by Philips. Copyright Philips 1983.
P-LCC-44
Semiconductor Group
5
04.95
Primary Rate Access Clock Generator
and Transceiver
PRACT
PEB 22320
Preliminary Data
CMOS
1
Features
ISDN line interface for 1544 and 2048 kbit/s (T1 and
CEPT)
Data and clock recovery
Transparent to ternary codes
Low transmitter output impedance for a high return
loss with reasonable protection resistors (CCITT
G.703 requirements for the line input return loss
fulfilled)
Adaptively controlled receiver threshold
Programmable pulse shape for T1 applications
Jitter specifications of CCITT I.431 and BELLCORE
TR-NWT-000499 publications met
Wander and jitter attenuation
Jitter tolerance of receiver: 0.5 UI s
Implements local and remote loops for diagnostic purposes
Monolithic line driver for a minimum of external components
Low power, reliable CMOS technology
Loss of signal indication for receiver
Clock generator for system clocks
The Primary Rate Access Clock Generator and Transceiver PRACT (PEB 22320) is a
monolithic CMOS device which implements the analog receive and transmit line
interface functions to primary rate PCM carriers. It may be programmed or hard wired to
operate in 1.544-Mbit/s (T1) or 2.048-Mbit/s (CEPT) carrier systems.
The PRACT recovers clock and data using an adaptively controlled receiver threshold.
It will meet the requirement of CCITT I.431 and Bellcore TR-NWT-000499 Issue 5,
December 1993 (Transport System Generic Requirements) in case of pulse shape, jitter
tolerance and jitter transfer characteristic.
Type
Ordering Code
Package
PEB 22320 N
Q67100-A6059
P-LCC-44 (SMD)
PEB 22320
Features
Semiconductor Group
6
Specially designed line interface circuits simplify the tedious task of protecting the device
against overvoltage damage while still meeting the return loss requirements.
The PRACT is suitable for use in a wide range of voice and data applications such as for
connections of digital switches and PBX's to host computers, for implementations of
primary ISDN subscriber loops as well as for terminal applications. The maximum range
is determined by the maximum allowable attenuation.
In the T1 case the PRACT's power consumption is mainly determined by the line length
and type of the cable.
PEB 22320
Features
Semiconductor Group
7
1.1
Pin Configuration
(top view)
ITP04874
6
5
4
3
2
1 44 43 42 41 40
28
27
26
25
24
23
22
21
20
19
18
29
30
31
32
33
34
35
36
37
38
39
7
8
9
10
11
12
13
14
15
16
17
FSC
LS0
XTAL4
LS1
XTAL2
XTAL1
LS2
CLK16M
CLK12M
SYNC
XL1
N.C.
XL2
N.C.
RL
MODE
XTIN
XTIP
XDIN
XDIP
XCLK
CS
RDON
RCLK
CLK2M
CLK2M
JATT
RL2
LL
CLK4M
CLK4M
FSC
PRACT
PEB 22320
SSD
V
RL1
V
DDD
RDOP
XTAL3
V
DD2
DDR
V
SSR
V
V
SSX
SSX
V
DDX
V
DDX
V
PEB 22320
Features
Semiconductor Group
8
1.2
Pin Definitions and Functions
Pin Definitions and Functions
Pin No.
Symbol
Input (I)
Output (O)
Function
1
V
DD2
O
Reference voltage for tapping the input transformer
2
RL2
I
Line receiver pin 2
3
LL
I
Local loopback:
A high level selects the device for the local
loopback mode.
4
5
CLK4M
CLK4M
O
O
System clock 4.096 MHz inverted and
non-inverted
6
7
FSC
FSC
O
O
8-kHz frame synchronization pulse inverted and
non-inverted
8
LS0
I
Line length select
9
10
XTAL4
XTAL3
O
I
Crystal connection 12.352 MHz
If an external clock generator is used and T1 mode
is selected the PRACT works as a master.
11
LS1
I
Line length select
12
13
XTAL2
XTAL1
O
I
Crystal connection 16.384 MHz
When an external clock is used, normally if the
MODE pin is set high, the PRACT functions as a
master.
14
LS2
I
Line length select
15
CLK16M O
System clock 16.384 MHz
16
CLK12M O
System clock 12.352 MHz
17
SYNC
I
If a clock is detected at the SYNC pin the PRACT
synchronizes to this clock (2.048 MHz for CEPT,
1.544 MHz for T1). (Please refer to table 3).
18, 19
V
DDX
I
Positive power supply for transmit subcircuits
20
XL1
O
Line transmit pin 1
21, 25
N.C.
not connected
22, 23
V
SSX
I
Ground for transmit subcircuits
24
XL2
O
Line transmit pin 2
PEB 22320
Features
Semiconductor Group
9
26
RL
I
Remote loopback:
High level puts the device to the remote loopback
mode.
27
MODE
I
Master/Slave selection
If the MODE pin is set to a low level the PRACT
functions as a slave. (Please refer to table 3)
28
29
XTIN
XTIP
I
I
Positive and negative test data inputs, active low,
full bauded
30
31
XDIN
XDIP
I
I
Positive and negative data inputs, active low, full
bauded
32
XCLK
I/O
If the T1 mode is selected the XCLK is a clock
output with a clock frequency of 1.544 MHz.
Otherwise the XCLK is a clock input whose
frequency is 2.048 MHz. (Please refer to table 3)
33
CS
I
Chip Select:
A low level selects the PEB 22320 for a register
write operation.
34
V
DDD
I
Positive power supply for the digital subcircuits.
35
V
SSD
I
Power ground supply for digital subcircuits.
36
37
RDOP
RDON
O
O
Receive data output positive and negative, fully
bauded, active low.
38
RCLK
O
Receive clock refer to table 3.
39
40
CLK2M
CLK2M
O
O
System clock 2.048 MHz inverted and
non-inverted.
41
V
SSR
I
Power ground supply for receive subcircuits.
42
V
DDR
I
Positive power supply for the receive subcircuits.
43
JATT
I
If the JATT pin is set to a low level the jitter
attenuator is bypassed.
44
RL1
I
Line receiver pin 1.
Pin Definitions and Functions (cont'd)
Pin No.
Symbol
Input (I)
Output (O)
Function
PEB 22320
Features
Semiconductor Group
10
1.3
System Integration
Figure 1 shows the architecture of a primary access board for data transmission. It
exhibits the following functions:
Line Interface (PEB 22320, PRACT)
Clock and Data Recovery (PEB 22320, PRACT)
Jitter Attenuation (PEB 22320, PRACT)
Clock Generation (PEB 22320, PRACT)
Coding/Decoding (PEB 2035, ACFA)
Framing (PEB 2035, ACFA)
Elastic Buffer (PEB 2035, ACFA)
Multichannel Protocol Controller (PEB 20320, MUNICH32)
System Adaptation (PEB 20320, MUNICH32)
P Interface (all devices)
Figure 1
Architecture of the PRACT
ITS04875
TCLK/RCLK
TSP/RSP
MUNICH32
PEB 20320
PEB 2035
ACFA
SCLK
SYPQ
PRACT
PEB 22320
CLK4M FSC FSC CLK2M
4.096 MHz
8 kHz
kHz
8
MHz
2.048
Memory
MPU
PC
Interface
PEB 22320
Functional Description
Semiconductor Group
11
2
Functional Description
Figure 2
Functional Block Diagram of the PRACT
Jitter Attenuator
&
Clock Generator
Loss of
Signal
Detection
LOS
P
Recovery
Data
Clock &
N
RRCLK
Remote Loop
Timing &
Pulseshaper
ROM
D/A
Local Loop
Receiver
Driver
RL
XDIN
XDIP
ITB04876
RDON
RDOP
RCLK
XCLK (T1)
MODE
SYNC
JATT
XTAL1, 2, 3, 4
LL
RL1
RL2
XL2
XL1
LS0, 1, 2
System
Clocks
XCLK
(CEPT)
Transmit
Output
Input
Receive
XTIP
Transmit
XTIN
Test Data
PEB 22320
Functional Description
Semiconductor Group
12
2.1
Receiver
2.1.1
Basic Functionality
The receiver recovers data from the ternary coded signal at the ternary interface and
outputs it as 2 unipolar signals at the dual rail interface. One of the lines carries the
positive pulses, the other the negative pulses of the ternary signal.
The signal at the ternary interface is received at both ends of a center-tapped
transformer as shown in figure 3.
.
Figure 3
Receiver Configuration
The transformer is center-tapped at the PRACT side. The recommended transmission
factors for the different line characteristic impedances are listed in table 1.
Table 1
Recommended Receiver Configuration Values
Wired in this way the receiver has a return loss
a
r
> 12 dB
for
0.025
f
b
f
0.05
f
b
,
a
r
> 18 dB
for
0.05
f
b
f
1.0
f
b
and
a
r
> 14 dB
for
1.0
f
b
f
1.5
f
b
,
with
f
b
being 2048 kHz. Thus it complies with CCITT G.703.
Application
T1
CEPT
Characteristic
Impedances
[
]
100
140 (ICOT)
120
75
R
2
(
2.5%)
[
]
28.7
39.2
60
60
t
2
:
t
1
=
t
2
: (
t
11
+
t
12
)
69:52
69:(26 + 26)
69:52
69:(26 + 26)
52:52
52:(26 + 26)
41:52
41:(26 + 26)
ITS00560
t
11
t
12
t
2
R
2
R
2
R
L
R
L
V
DD
Line
2
1
2
PEB 22320
Functional Description
Semiconductor Group
13
The receiver is transparent to the logical 1's polarity and outputs positive logical 1's on
RDOP and negative logical 1's on RDON. RDON and RDOP are active low and fully
bauded. The comparator threshold to detect logical 1's and logical 0's is automatically
adjusted to be 45% of the peak signal level.
Provided the noise is below 10
V/
Hz the bit error rate will be less than 10
7
.
2.1.2
Clock and Data Recovery
An analog PLL extracts the internal recovered route clock RRCLK from the data stream
received at the RL1 and RL2 lines. The PLL uses as a reference the system clock
CLK16M for CEPT and CLK12M for T1 applications. The clock and data recovery is
tolerant to long strings of consecutive zeros, because the data sampler will continuously
sample data based on its last input. A block diagram of the clock and data recovery
circuit is shown in figure 4.
Figure 4
Clock and Data Recovery Circuit
ITS04877
PD
VCO
Filter
Data
Sampling
P
N
Data
RRCLK
CLK16M (CEPT)
CLK12M (T1)
Input Data
derived from RL
1, 2
PEB 22320
Functional Description
Semiconductor Group
14
2.1.3
Input Jitter Tolerance
The PRACT receiver's tolerance to input jitter complies to CCITT and Bellcore
requirements for CEPT and T1 application.
Figure 5 shows the curves of the different input jitter specifications stated above as well
as the PRACT performance for the various line codes used at the S1/S2 interfaces.
In figure 5 the curves show that the PRACT at low frequencies has more than 20 dB/
decade fall off, and at high frequencies is in a steady state of 0.5 UI (horizontal).
Figure 5
Comparison of Input Jitter Specification and PRACT Performance
ITD06576
1
10
100
1000
10000
100000
Hz
0.1
Jitter Input Tolerance
Jitter Frequency
1
10
100
UI
TR-NWT 000499
Cat I
II
Cat
000499
TR-NWT
PRACT CEPT
PRACT T1
CCITT G.823
PEB 22320
Functional Description
Semiconductor Group
15
2.1.4
Jitter Attenuator and Clock Generator
The jitter attenuator reduces wander and jitter in the recovered clock which are produced
by the line-, clock- and data-recovery characteristics. The attenuator consists of one PLL
with a tunable crystal oscillator and a 288-bit FIFO. To provide for T1 mode a 1.544-MHz
clock (XCLK) and a 2.048-MHz clock (CLK2M) for the system, a second PLL is placed
in series with the first one (refer to figure 6).
If the JATT pin is set to low the FIFO is bypassed and the propagation delay from RL1, 2
to RDOP/RDON is reduced by the pass time of the FIFO.
After loss of signal detection, the internal PLL is synchronized to the 2.048 MHz (CEPT)
provided at the SYNC pin (1.544 MHz in the case of T1). If this SYNC pin is not
connected or connected to logical zero, the PRACT switches automatically to master
operating mode (refer to table 3).
With the MODE pin a master selection is provided. That means if the MODE pin is set to
high the master function is selected in which the VCO's of the jitter attenuator are
centered (
50 ppm of the crystal frequencies). If a clock is detected at the SYNC pin the
PRACT automatically synchronized to this clock.
Table 2
Jitter Input Tolerance
Frequency
TR-NWT
000499
TR-NWT
000499
PRACT
PRACT
Hz
CCITT G.823
Cat I
Cat II
CEPT
T1
1
2.9
10
5
10
20
1.5
192.9
10
500
5
90
70
2400
1.5
5.8
4.5
6430
0.3
8000
0.1
1.15
0.95
10000
0.95
0.8
18000
0.2
0.62
0.58
20000
0.58
0.55
25000
0.55
0.55
40000
0.1
0.3
0.5
0.5
50000
0.55
0.55
100000
0.55
0.55
PEB 22320
Functional Description
Semiconductor Group
16
The jitter attenuator meets the jitter transfer requirements of the Bellcore
TR-NWT 000 499 and Rec. I.431 (refer to figure 7 and table 4).
The amount of generated output jitter when no input jitter is shown in table 5.
Figure 6
Jitter Attenuator Block Diagram
ITB04879
PD
VCO
256
2
4
16.384 MHz
kHz
8
2 MHz
4 MHz
MHz
16
12 MHz
MHz
12.352
8
193
VCO
PD
MODE
193
8 kHz
256
1.5 MHz
(XCLK-T1)
T1
SYNC
LOS
RCLK
RDON
RDOP
Recovery
Clock & Data
RL1, 2
N Data
Data
P
RRCLK
FIFO
R
W
JATT
_
<
_
<
_
<
_
<
_
<
_
<
_
<
PEB 22320
Functional Description
Semiconductor Group
17
Table 3
Clock and Synchronization Table
JAT
T
=
1:
Ji
t
t
er at
t
e
n
uat
or
enabl
ed
12
M =
12.
352 MH
z
R
R
C
L
K =
I
n
t
e
rnal
recovered
rout
e
cl
o
c
k
M
O
D
E
= 0
Sl
ave
m
o
d
e
sel
e
ct
ed
JAT
T
= 0:
B
y
pass
j
i
t
t
er at
t
enuat
or
16 M
= 16.
384
MH
z
S
Y
N
C
= 0:
I
nput
t
i
ed t
o
l
o
w
M
O
D
E =
1
:
M
a
st
er
mode sel
e
ct
ed
4 M
= 4.
09
6
MH
z
S
Y
N
C
= 2 M
:
I
nput
conn
ect
ed t
o
2 M
8
k
=
8.
0 kH
z
LO
S =
0:
I
nput
abo
ve recei
v
er
t
h
r
e
sh
ol
d
2
M =
2.
04
8 MH
z
S
Y
N
C
=
1.
5 M:
I
nput
connect
ed
t
o
1.
5 M
= d
o
n
't
c
a
r
e
LO
S =
1:
I
nput
bel
ow
recei
v
er
t
h
r
e
sho
l
d
1
.
5
M
= 1.
544
MH
z
= N
o
C
onnect
i
o
n
Pin
JA
TT
Int. Sig
LO
S
Pi
n
SY
N
C
Pin
MOD
E
Pin
LS0..2
Pin
XT
A
L
3
Pi
n
XT
A
L
4
Pin
XTA
L
1
Pin
XTAL2
System C
l
ocks
4M
, 2M, 8K
D
e
r
ived fr
om
Pin
XC
LK
Pin
RCL
K
10
X
0
T1
12 M C
r
ystal
16 M
C
r
ys
tal
16 M c
r
y
s
tal
sync
.
on XC
LK
ou
tput: 1.5 M
sync
.
on R
R
C
L
K
=
1.5 M
1
1
0
0
T1
12 M C
r
ystal
16 M
C
r
ys
tal
16 M c
r
y
s
tal
sync
.
on XC
LK
ou
tput: 1.5 M,
freq. centered
=
1.5 M
1
1
1.5 M
0
T1
12 M C
r
ystal
16 M
C
r
ys
tal
16 M c
r
y
s
tal
sync
.
on XC
LK
ou
tput: 1.5 M
sync
.
on SY
N
C
=
1.5 M
1
X
1.5 M
1
T1
12 M C
r
ystal
16 M
C
r
ys
tal
16 M c
r
y
s
tal
sync
.
on XC
LK
ou
tput: 1.5 M
sync
.
on SY
N
C
=
1.5 M
1
X
0
1
T
1
12 M C
r
ystal
16 M
C
r
ys
tal
16 M c
r
y
s
tal
sync
.
on XC
LK
ou
tput: 1.5 M
fr
e
q. centered
=
1.5 M
1
X
X
X
T
1
12 M in
N
.
C
.
16 M
C
r
ys
tal
16 M c
r
y
s
tal
sync
.
on XC
LK
ou
tput: 1.5 M
sync
.
on XTA
L
3
=
1.5 M
10
X
0
C
EPT
X
X
16 M
C
r
ys
tal
16 M c
r
y
s
tal
sync
.
on R
R
C
L
K
i
nput (2 M from
A
C
FA)
=
2 M
1
1
0
0
C
EPT
X
X
16 M
C
r
ys
tal
16 M c
r
y
s
tal
sync
.
freq. cent
er
e
d
i
nput (2 M from
A
C
FA)
=
2 M
1
1
2 M
0
C
EPT
X
X
16 M
C
r
ys
tal
16 M c
r
y
s
tal
sync
.
on SY
N
C
i
nput (2 M from
A
C
FA)
=
2 M
1
X
2
M
1
C
EPT
X
X
16 M
C
r
ys
tal
16 M c
r
y
s
tal
sync
.
on SY
N
C
i
nput (2 M from
A
C
FA)
=
2 M
1
X
0
1
C
EPT
X
X
16 M
C
r
ys
tal
16 M c
r
y
s
tal
sync
.
freq. cent
er
e
d
i
nput (2 M from
A
C
FA)
=
2 M
1
X
X
X
C
EPT
X
X
16 M
in
N
.
C
.
16 M i
n
i
nput (2 M from
A
C
FA)
=
2 M
00
X
0
T1
12 M C
r
ystal
16 M
C
r
ys
tal
16 M c
r
y
s
tal
sync
.
on XC
LK
ou
tput: 1.5 M
sync
.
on R
R
C
L
K
=
R
R
C
L
K
0
1
0
0
T1
12 M C
r
ystal
16 M
C
r
ys
tal
16 M c
r
y
s
tal
sync
.
on XC
LK
ou
tput: 1.5 M,
freq. centered
=
R
R
C
LK
0
1
1.5 M
0
T1
12 M C
r
ystal
16 M
C
r
ys
tal
16 M c
r
y
s
tal
sync
.
on XC
LK
ou
tput: 1.5 M
sync
.
on SY
N
C
=
R
R
C
LK
0
X
1.5 M
1
T1
12 M C
r
ystal
16 M
C
r
ys
tal
16 M c
r
y
s
tal
sync
.
on XC
LK
ou
tput: 1.5 M
sync
.
on SY
N
C
=
R
R
C
LK
0
X
0
1
T
1
12 M C
r
ystal
16 M
C
r
ys
tal
16 M c
r
y
s
tal
sync
.
on XC
LK
ou
tput: 1.5 M
fr
e
q. centered
=
R
R
C
LK
0
X
X
X
T
1
12 M in
N
.
C
16 M
C
r
ys
tal
16 M c
r
y
s
tal
sync
.
on XC
LK
ou
tput: 1.5 M
sync
.
on XTA
L
3
=
R
R
C
L
K
00
X
0
C
EPT
X
X
16 M
C
r
ys
tal
16 M c
r
y
s
tal
sync
.
on R
R
C
L
K
i
nput (2 M from
A
C
FA)
=
R
R
C
L
K
0
1
0
0
C
EPT
X
X
16 M
C
r
ys
tal
16 M c
r
y
s
tal
sync
.
freq. cent
er
e
d
i
nput (2 M from
A
C
FA)
=
R
R
C
L
K
0
1
2 M
0
C
EPT
X
X
16 M
C
r
ys
tal
16 M c
r
y
s
tal
sync
.
on SY
N
C
i
nput (2 M from
A
C
FA)
=
R
R
C
L
K
0
X
2
M
1
C
EPT
X
X
16 M
C
r
ys
tal
16 M c
r
y
s
tal
sync
.
on SY
N
C
i
nput (2 M from
A
C
FA)
=
R
R
C
L
K
0
X
0
1
C
EPT
X
X
16 M
C
r
ys
tal
16 M c
r
y
s
tal
sync
.
freq. cent
er
e
d
i
nput (2 M from
A
C
FA)
=
R
R
C
L
K
0
X
X
X
C
EPT
X
X
16 M
in
N
.
C
.
16 M i
n
i
nput (2 M from
A
C
FA)
=
R
R
C
L
K
X
N.
C.
PEB 22320
Functional Description
Semiconductor Group
18
Figure 7
Jitter Attenuation Characteristics
Table 4
Jitter Transfer Characteristics
Frequency
CCITT G. 735
TR-NWT 000499
PRACT
PRACT
Hz
CCITT I.431
Cat I to Cat II
CEPT
T1
0.3
0.00
1
3
0.00
20.00
10
0.5
0.10
30
20.00
40.00
40
0.5
100
ITD06577
0.1
Hz
-60
Jitter Transfer Characteristics
Jitter Frequency
CCITT G.735
CCITT I.431
PRACT CEPT
PRACT T1
1
10
100
1000
10000
100000
I
Cat
000499
TR-NWT
Cat I
to
-50
-40
-30
-20
-10
0
2
dB
PEB 22320
Functional Description
Semiconductor Group
19
Table 5
Generated Output Jitter
200
250
300
39.40
60.00
350
400
19.50
9650
1000
1412
2500
34.07
3000
60.00
-80.00
10000
15000
19.50
49.63
Specification
Measurement Filter Bandwidth
Output Jitter
Lower Cutoff
Upper Cutoff
(UI peak to peak)
I.431
20 Hz
700 Hz
100 kHz
100 kHz
0.125
0.02
PUB 62411 Dez. 90
10 Hz
8 kHz
10 Hz
8 kHz
40 kHz
40 kHz
0.02
0.025
0.025
broad band
0.05
ETS 300 011
40 Hz
100 kHz
0.11
Table 4
Jitter Transfer Characteristics (cont'd)
Frequency
CCITT G. 735
TR-NWT 000499
PRACT
PRACT
Hz
CCITT I.431
Cat I to Cat II
CEPT
T1
PEB 22320
Functional Description
Semiconductor Group
20
2.2
Transmitter
2.2.1
Basic Functionality
The transmitter transforms unipolar data to ternary (alternate bipolar) return to zero
signals of the appropriate shape. The unipolar data is provided at XDIP (positive pulses)
and XDIN (negative pulses), synchronously with the transmit clock XCLK. XDIP and
XDIN are active low and full bauded. Data is sampled on the falling edge of the input
clock (XCLK). The input clock (XCLK) must be derived from the (system) clocks
generated by the PRACT. This ensures the recommended fixed relationship between
XLCK and internal generated clock (4 times XCLK) for the pulse shaper.
The transmitter includes a programmable pulse shaper to satisfy the requirements of the
AT&T Technical Advisory # 34 at the cross connect point for T1 applications. The pulse
shaper is programmed via the line length selection pins LS0, LS1 and LS2.
For T1 application the line length selection supports both low capacitance cable with a
characteristic line capacitance of C'
40 nF/km = 65 nF/mile (e.g. MAT, ICOT) and
higher capacitance cable with a characteristic line capacitance of 40 nF/
km
C'
54 nF/km (65 nF/mile
C'
87 nF/mile) e.g. ABAM, PIC and PULP cables.
This ensures that for various cable types the signal at the DSX-1 cross connect point
complies with the pulse shape of the AT&T Technical Advisory # 34.
The line length is selected programming the LS0, LS1 and LS2 pins as shown for typical
values in table 6.
Table 6
Line Length Selection
Note: * For ICOT-cable the characteristic impedance is 140
By selecting an all-zero code for LS0, LS1 and LS2 the PRACT can be adapted for
CEPT applications.
LS2
LS1
LS0
PIC/PULP Cable 24 AWG
range/m
ICOT Cable
range/m*
0
0
0
CEPT
0
0
1
T1/G.703
0
50
0
80
0
1
0
T1
20
80
65
145
0
1
1
T1
60
130
130
210
1
0
0
T1
110
200
195
275
1
0
1
T1
140
230
260
340
1
1
0
T1
210
290
325
405
1
1
1
T1
270
320
390
470
PEB 22320
Functional Description
Semiconductor Group
21
The pulse shape according to CCIT G.703 (1544-kbit/s interface) is achieved by using
the same line length selection code as for the lowest T1 cable range. To switch the
device into a low power dissipation mode, XDIP and XDIN should be held high.
The transmitter requires an external step up transformer to drive the line. The
transmission factor and the source serial resistor values can be seen in figure 8 and
table 7 for the various applications.
Figure 8
Transmitter Configuration
Table 7
Transmitter Configuration Values
Wired in this way the transmitter has a return loss
a
r
> 8 dB
for
0.025
f
b
f
0.05
f
b
,
a
r
> 14 dB
for
0.05
f
b
f
1.0
f
b
and
a
r
> 10 dB
for
1.0
f
b
f
1.5
f
b
,
with
f
b
being 2048 kHz (CEPT applications). A termination resistor of 120
is assumed.
In T1 applications the return loss is higher than 10 dB.
Please note, that the transformer ratio at the receiver is half of that at the transmitter. The
same type of transformer can thus be used at the receiver and at the transmitter. At the
transmitter the two windings are connected in parallel, at the receiver in series. Thus,
unbalances are avoided.
Application
T1
CEPT
Characteristic line impedance
[
]
100
140 (ICOT)
120
75
t
11
:
t
2
=
t
12
:
t
2
26:69
26:69
26:52
26:41
R
1
(
2.5%) [
]
4.3
6
15
15
ITS00562
t
11
t
12
t
2
R
1
R
1
Line
XL1
2
XL
PEB 22320
Functional Description
Semiconductor Group
22
2.2.2
Output Jitter
In the absence of any input jitter the PRACT generates the output jitter, which is specified
in table 5.
Note: The generated output jitter on the line is the same as the output jitter of the system
clocks.
2.3
Local Loopback
The local loopback mode disconnects the receive lines RL1 and RL2 from the receiver.
Instead of the signals coming from the line the data provided at XTIP and XTIN are
routed through the receiver. The XDIN and XDIP signals continue to be transmitted on
the line. The local loopback occurs in response to LL going high.
2.4
Remote Loopback
In the remote loopback mode the clock and data recovered from the line inputs RL1 and
RL2 are routed back to the line outputs XL1 and XL2 via the transmitter. As in normal
mode they are also output at RDOP and RDON. XDIP and XDIN are disconnected from
the transmitter.
The remote loopback mode is selected by a high RL signal.
2.5
Bypass Jitter Attenuator
If the JATT pin is set to low the jitter attenuator (FIFO) is bypassed and the propagation
delay from the line to the dual rail interface is reduced by the path time of the FIFO. Also
in this mode the jitter in the system clocks (CLK2M, CLK4M, FSC) is attenuated.
2.6
Microprocessor Interface
The PRACT is fully controlled by six parallel data lines (LS0, LS1, LS2, LL, RL and JATT)
and one control line (CS). To adapt the device to a standard microprocessor interface
the low state of CS is decoded from the microprocessor address, CS, WR and ALE lines.
To hardwire the chip, CS must be fixed to ground.
2.7
Receiver Loss of Signal Indication
In the case that the signal at the line receiver input (pins RL1, RL2) becomes smaller
than
V
in
0.3
V
OP
loss of signal is indicated. This voltage value corresponds to a line
attenuation of about 14 dB in the CEPT case. This is performed by turning both signals
RDOP, RDON after at least 32 bits simultaneously to 5 V, i.e. a logical 0 on both lines.
The following ACFA processes this indication for the system. In this mode the PRACT
synchronizes to the clock at the SYNC pin.
PEB 22320
Functional Description
Semiconductor Group
23
2.8
Master/Slave Selection
If the MODE pin is set to high and the SYNC pin is not connected or connected to
V
SS
the
PRACT works as a master for the system. The VCO's of the jitter attenuator are centered
(
50 ppm of the crystal frequencies) and the system clocks are stable (divided from the
VCO frequencies). If a clock (2.048 MHz for CEPT, 1.544 MHz for T1) is detected at the
SYNC pin the PRACT synchronizes automatically to this clock. In master mode, the
PRACT is independent from the receiver loss of signal detection.
Note: The MODE pin can not be controlled by the
P interface and requires CMOS
levels as input signals. It must always be connected either to
V
DD
or
V
SS
.
A voltage of 2.5 V at the MODE Pin switch the PRACT into test mode.
PEB 22320
Operational Description
Semiconductor Group
24
3
Operational Description
3.1
Reset
After power up resetting the device is necessary to synchronize the internal circuitries.
After reset a stabel RCLK is available after 65536 clock cycles. This results in 32 ms in
CEPT mode and 42.5 ms in T1 mode. A reset can be performed by two ways.
3.1.1
Reset with CS Pin Fixed to
V
SS
In this reset operation the CS pin is normally hardwired to
V
SS
. Before giving a reset the
operational mode has to be selected (CEPT, T1) by setting the pins LS2, LS1, LS0 to
000 for CEPT-application, to 001 for NTT-application or 001 ... 111 for T1 application.
A reset is made by simultaneously setting both RL and LL to high (CS = 0) for at least
1
s. Reset will be initiated on the falling edge of RL or LL, the one that falls first.
The following figures explain the procedure in some examples.
Figure 9
Resetting PRACT for CEPT Applications
t
1.
2.
ITD04881
1. Start of Reset
2. End of Reset
LL
RL
LS0
LS1
LS2
CS
s
1
PEB 22320
Operational Description
Semiconductor Group
25
Figure 10
Resetting PRACT for CEPT Applications and Setting Local Loop with Jitter
Attenuation
Figure 11
Resetting PRACT for T1 Applications (max. line length selected) and Setting
Remote Loop
Note: If the PRACT is initiated for T1 applications the line length selection can be
changed without a new reset.
t
1.
2.
ITD04882
1. Start of Reset
2. End of Reset and local loop is initiated
JATT
RL
LS0
LS1
LS2
CS
LL
t
1.
2.
ITD04883
1. Start of Reset
2. End of Reset, regular operation in T1 Mode
LL
RL
LS0
LS1
LS2
CS
3.
3. Remote loop is initiated
PEB 22320
Operational Description
Semiconductor Group
26
3.1.2
Reset Using CS Pin to Latch Programming (a controller is used)
Reset is done by setting the pins RL and LL to logical 1 for at least 1
s and latching
these values into PRACT by a rising edge at pin CS.
The selection of CEPT, T1 applications is achieved by setting the pins LS2, LS1, LS0
simultaneously with the reset to 000 for CEPT application or a T1 line length code
(001 ... 111 see table 6). The logical level of the RL, LL, LS2, LS1, LS0, JATT input parts
are latched with the rising edge of the CS. Refer to figure 20.
The following figures explain the procedure in some examples.
Figure 12
Resetting PRACT for CEPT Applications and Jitter Attenuation
Figure 13
Resetting PRACT for CEPT Application and Setting Remote Loop
t
1.
ITD04884
1. Start of Reset
2. End of Reset, Regular operation in CEPT Mode
LL
RL
CS
2.
LS0, 1, 2
s
1
JATT
t
1.
ITD04885
1. Start of Reset
2. End of Reset and setting remote loop
LL
RL
CS
2.
LS0, 1, 2
PEB 22320
Operational Description
Semiconductor Group
27
Figure 14
Resetting PRACT for T1 Applications and Changing Line Length Code
Figure 15
Resetting PRACT for T1 Application and Setting Local Loop
3.2
Operation
The PRACT is in normal operation as soon as the reset phase is finished. The CS pin is
activated again only when PRACT is reprogrammed (for example setting a loop or
changing line length code). That means CS pin could be kept high for normal operation.
t
1.
ITD04886
1. Start of Reset
2. End of Reset and setting line length code, Regular operation in T1 Mode
LL
RL
CS
2.
3. Changing line length code, Regular operation in T1 Mode with
LS0, 1, 2
001
xxx
xxx
001
xxx
3.
010
xxx
xxx
changed line length code
t
1.
ITD04887
1. Start of Reset
2. End of Reset and setting local loop and
LL
RL
CS
2.
line length code
LS0, 1, 2
111
xxx
xxx
111
xxx
PEB 22320
Electrical Specification
Semiconductor Group
28
4
Electrical Specification
4.1
Absolute Maximum Ratings
4.2
Delay Times
4.2.1
Delay from XDIP/XDIN to XL1/XL2
The delay from XDIP/XDIN to XL1,XL2 is 770 ns in T1 mode and 860 ns in CEPT mode.
This relates to the falling edge of the XCLK and the leading edge of XL1 or XL2.
4.2.2
Delay from RL1/RL2 to RDOP/RDON
The delay from RL1/RL2 to RDOP/RDON is given with 700 ns in T1 mode and 540 ns in
CEPT mode. This relates to the leading edge of the RL1 or RL2 to the falling edge of
RDOP or RDON.
Parameter
Symbol
Limit Values
Unit
Voltage on any pin with respect to
ground
V
S
0.4 to
V
DD
+ 0.4 V
Ambient temperature under bias
T
A
0 to 70
C
Storage temperature
T
stg
65 to 125
C
PEB 22320
Electrical Specification
Semiconductor Group
29
4.3
DC Characteristics
T
A
= 0 to 70
C;
V
DD
= 5 V
5%,
V
SS
= 0 V
DC Characteristics
Parameter
Symbol
Limit Values
Unit Test Condition
Pins
min.
max.
L-input voltage
V
IL
0.4
0.8
V
All
pins
except
MODE,
RLx,
XLx
XTALx,
V
DD2
,
SYNC
H-input voltage
V
IH
2.0
V
DD
+ 0.4 V
L-output voltage
V
OL
0.45
V
I
OL
= 2 mA
H-output voltage
V
OH
2.4
V
I
OH
= 400
A
H-output voltage
V
OH
V
DD
0.5
V
I
OH
= 100
A
Input leakage
current
I
LI
1
A
0 V <
V
IN
<
V
DD
to
0 V
Output leakage
current
I
LO
0 V <
V
OUT
<
V
DD
to
0 V
Peak voltage of a
mark (CEPT)
V
XCEPT
2.7
3.3
V
wired according
figure 8 and table 7
XL1,
XL2
Peak voltage of a
mark (T1)
V
XT1
1.8
3.4
V
T1 application:
depending on line
length
Transmitter output
impedance
R
X
0.3
Transmitter output
current
I
X
50
mA
CEPT application
150
mA
T1 application:
depending on line
length
Receiver input
peak voltage of a
mark
V
R
1)
0.4
2.5
V
RL1,
RL2
Loss of signal
threshold
V
LOS
0.3
V
Receiver input
threshold
V
RTH
45
%
Voltage at
V
DD2
V
DD2
2.4
2.6
V
PEB 22320
Electrical Specification
Semiconductor Group
30
4.4
Characteristics
T
A
= 25
C;
V
DD
= 5 V
5 %,
V
SS
= 0 V
1)
Measured against
V
DD2
L-input voltage
V
XTALIL
0.4
1.0
V
XTAL1,
XTAL2,
XTAL3,
XTAL4
H-input voltage
V
XTALIH
4.0
V
DD
+
0.4
V
Input leakage
current
I
XTALI
1
A
0 V
V
IN
V
DD
to
0 V
Operational
power supply
current
I
CC
40
110
mA
CEPT application
55
190
mA
T1 application,
min value for all
zeros, max value
for all ones and
max. line length for
T1 appl.
L-input voltage
V
IL
0.4
0.8
V
MODE,
SYNC
H-input voltage
V
IH
4.0
V
DD
+
0.4
V
Input leakage
current
I
LI1
I
LI2
I
LI3
I
LI4
800
100
800
200
A
A
A
A
V
IL
= 0.8 V
V
IL
= 0.1 V
V
IH
= 4 V
V
IH
=
V
DD
Parameter
Symbol
Limit Values
Unit
Pins
min.
max.
Input capacitance
C
IN
10
pF
all except RLx, XLx,
XTALx
Output capacitance
C
OUT
15
pF
all except RLx, XLx,
XTALx
Input capacitance
C
IN
7
pF
RLx
Output capacitance
C
OUT
20
pF
XLx
DC Characteristics (cont'd)
Parameter
Symbol
Limit Values
Unit Test Condition
Pins
min.
max.
PEB 22320
Electrical Specification
Semiconductor Group
31
4.5
Recommended Oscillator Circuits
Figure 16
Oscillator Circuits
In CEPT mode if an external source is connected to XTAL1, the PRACT works,
independent of the MODE pin, in master mode.
In T1 mode if an external source is connected to XTAL3, the PRACT works, independent
of the MODE pin, in master mode. This operational mode requires a crystal
(16.384 MHz) at pins XTAL1 and XTAL2. The frequency is locked to the external source.
The jitter attenuator requires unique performance specifications for the crystals.
The following typical crystal parameters will meet this specifications:
Motional capacitance
C
1
= 25 fF min
Shunt capacitance
C
0
= 7 pF max
Load capacitance
C
L
= 18 pF typ, f
0
= 16.384 MHz
C
L
= 10 pF typ, f
0
= 12.352 MHz
Resonance resistance
R
r
25
ITS04888
XTAL1
(XTAL3)
(XTAL4)
XTAL2
PRACT
16.384
(12.352
MHz
MHz)
14 pF
pF
14
PRACT
XTAL2
(XTAL4)
(XTAL3)
XTAL1
External
Oscillator
Signal
N.C.
Crystal Oscillator mode
(slave mode/ master mode)
Driving from external source
(master mode)
(12.352
16.384
MHz)
MHz
(4 pF)
C
L
=
PEB 22320
Electrical Specification
Semiconductor Group
32
PRACT Tuning Range 16.384 MHz PLL
Crystal specified for
C
L
= 18 pF
Figure 17
16.384-MHz Crystal Tuning Range
ITD06578
14
-150
-100
-50
0
50
100
150
ppm
16
18
20
22
24
pF
26
d
f
f
0
C
L
PEB 22320
Electrical Specification
Semiconductor Group
33
PRACT Tuning Range 12.352 MHz PLL
Crystal specified for
C
L
= 10 pF
Figure 18
12.352-MHz Crystal Tuning Range
ITD06579
6
-250
ppm
8
pF
d
f
f
0
C
L
12
10
16
14
18
-200
-150
-100
-50
0
50
100
150
200
250
PEB 22320
Electrical Specification
Semiconductor Group
34
4.6
AC Characteristics
T
A
= 0 to 70
C;
V
DD
= 5 V
5 %
Figure 19
Input/Output Waveforms for AC Tests
Except from the line interface, inputs are driven at 2.4 V for a logical 1 and 0.4 V for a
logical 0. Timing measurements are made at 2.0 V for a logical 1 and at 0.8 V for a logical
0. AC testing input/output waveforms are shown in figure 19.
4.6.1
Dual Rail Interface
RDOP, RDON, XDIP, XDIN, XTIP, XTIN are active low.
Figure 20
Timing of the Dual Rail Interface
ITS00621
= 150
Load
C
Test
Under
Device
0.45
2.4
2.0
0.8
0.8
2.0
Test Points
pF
ITT04889
t
CPR
CPRH
t
t
CPRL
DROH
t
t
DROS
RCLK
RDON
XDIN
XCLK
DRIS
t
t
DRIH
CPXL
t
t
CPXH
CPX
t
XTIN
RDOP,
XTIP,
XDIP,
PEB 22320
Electrical Specification
Semiconductor Group
35
Parameter
Symbol
Limit Values
Unit
PCM 30
PCM 24
min.
max.
min.
max.
RCLK clock period
t
CPR
typ. 488
typ. 648
ns
RCLK clock period low
t
CPRL
200
260
ns
RCLK clock period high
t
CPRH
200
260
ns
Dual rail output setup
t
DROS
200
260
ns
Dual rail output hold
t
DROH
200
260
ns
XCLK clock period
t
CPX
typ. 488
typ. 648
ns
XCLK clock period low
t
CPXL
200
250
ns
XCLK clock period high
t
CPXH
200
250
ns
Dual rail input setup
t
DRIS
25
25
ns
Dual rail input hold
t
DRIH
25
25
ns
PEB 22320
Electrical Specification
Semiconductor Group
36
4.6.2
System Clock Interface
Figure 21
Timing of the System Clock Interface
ITT04890
t
CP16
CP16H
t
t
CP16L
t
CP4
CP4H
t
CP4L
t
t
CP2L
t
CP2H
CP2
t
SS
t
t
SH
CP12L
t
t
CP12H
CP12
t
t
CP15
CP15H
t
CP15L
t
CLK16M
CLK4M
CLK4M
CLK2M
CLK2M
FSC
FSC
CLK12M
XCLK (T1)
PEB 22320
Electrical Specification
Semiconductor Group
37
System Clock Interface Timing Parameter Values
Parameter
Symbol
Limit Values
Unit
min.
max.
CLK16M period 16 MHz
t
CP16
typ. 61
ns
CLK16M period 16 MHz low
t
CP16L
20
ns
CLK16M period 16 MHz high
t
CP16H
20
ns
CLK4M period 4 MHz
t
CP4
typ. 244
ns
CLK4M period 4 MHz low
t
CP4L
110
ns
CLK4M period 4 MHz high
t
CP4H
110
ns
CLK2M period 2 MHz
t
CP2
typ. 488
ns
CLK2M period 2 MHz low
t
CP2L
220
ns
CLK2M period 2 MHz high
t
CP2H
220
ns
FSC setup time
t
SS
110
ns
FSC hold time
t
SH
240
ns
CLK12M period 12 MHz
t
CP12
typ. 81
ns
CLK12M period 12 MHz low
t
CP12L
30
ns
CLK12M period 12 MHz high
t
CP12H
30
ns
XCLK period 1.5 MHz
t
CP15
typ. 648
ns
XCLK period 1.5 MHz low
t
CP15 L
300
ns
XCLK period 1.5 MHz high
t
CP15 H
300
ns
PEB 22320
Electrical Specification
Semiconductor Group
38
4.6.3
Microprocessor Interface
Figure 22
Timing of the Microprocessor Interface
Parameter
Symbol
Limit Values
Unit
min.
max.
CS pulse width
t
WC
60
ns
Data setup time to CS
t
DW
35
ns
Data hold time from CS
t
WD
10
ns
Cycle time
t
CYC
120
ns
ITT04891
t
CYC
WC
t
WD
t
t
DW
CS
2)
DATA
LS0,
RL,
(JATT,
LL,
1,
PEB 22320
Electrical Specification
Semiconductor Group
39
4.6.4
XTAL Timing
Figure 23
Timing of XTAL1/XTAL3
XTAL1/XTAL3 Timing Parameter Values
Note: If an external clock is used the PRACT works as a master. Please refer to Pin
Definitions.
Parameter
Symbol
Limit Values
Unit
Condition
min.
typ.
max.
Clock period of crystal/
clock
t
P
61
81
ns
XTAL1
XTAL3
High phase crystal/clock
t
WH
20
30
ns
XTAL1
XTAL3
Low phase of crystal/clock
t
WL
20
30
ns
XTAL1
XTAL3
ITT04892
XTAL1
WL
t
t
WH
P
t
3.5 V
V
0.8
XTAL3
PEB 22320
Electrical Specification
Semiconductor Group
40
4.7
Pulse Templates - Transmitter
The PRACT meets both CCITT and T1 pulse template requirements.
Figure 24
Pulse Template at the Transmitter Output for CEPT Applications
ITD00573
10
%
10
%
%
10
10
%
%
10
10
%
20
%
269 ns
(244 + 25)
(244 - 50)
ns
194
219 ns
(244 - 25)
ns
244
(244 + 244)
ns
488
%
0
50 %
%
V=100
Nominal Pulse
%
20
20
%
PEB 22320
Electrical Specification
Semiconductor Group
41
Figure 25
T1 Pulse Shape at the Cross Connect Point
Table 8
T1 Pulse Template Corner Points at the Cross Connect Point
Maximum Curve
Minimum Curve
(0
0.05)
(0,
0.05
(250,
0.05)
(350,
0.05)
(325,
0.80)
(350,
0.50)
(325,
1.15)
(400,
0.95)
(425,
1.15)
(500,
0.95)
(500,
1.05)
(600,
0.90)
(675,
1.05)
(650,
0.50)
(725,
0.07)
(650,
0.45)
(1100,
0.05)
(800,
0.45)
(1250,
0.05)
(925,
0.20)
(1100,
0.05)
(1250,
0.05)
ITD00574
%
100
=
V
50 %
0
-50 %
0
250
500
750
1000
ns
t
Normalized Amplitude
PEB 22320
Electrical Specification
Semiconductor Group
42
Figure 26
Pulse Shape According to CCITT G.703
4.8
Overvoltage Tolerance
To prevent the PRACT from being damaged by overvoltage (i.e. from lightning), external
devices like diodes or resistors have to be connected to one or both sides of the line
interface transformers. Thus, overvoltage peaks are cut off. However, some residual
overvoltage may remain.
The PRACT simplifies the task of designing external protection circuits. Its transmitter
exhibits a low line impedance so that reasonable external resistors can be connected to
the line outputs. Figure 8 with the element values of table 7 gives an example of how an
overvoltage protection against residual overvoltages at the ternary interface can be
accomplished. The solution shown also meets the stated return loss requirements.
A similar consideration applies to the receiver. The resistors R2 of figure 3 provide
protection against residual overvoltages by attenuating voltages of both polarities across
RL1 and RL2.
The maximum input current allowed to reach the PRACT pins under overvoltage
conditions is given as a function of the width of a rectangular input current pulse
according to figure 27. Figure 29 shows the curve of the maximum allowed input current
across the pins RL1 and RL2, figure 28 across the pins XL1 and XL2.
ITD00575
0.3
1.2
50 ns
50 ns
0.7
0.7
3 T
8
-
-
4
T
0
T
8
T
4
3 T
8
T
2
T = 1/1544
kHz
0
1.5
3.0
V
PEB 22320
Electrical Specification
Semiconductor Group
43
Figure 27
Measurement of Overvoltage Stress
Figure 28
Tolerated Input Current at the XL1, XL2 Pins
ITS04893
t
p
t
WI
Condition: All other pins grounded
FALC
TM
-54
ITD00578
1
-9
10
-6
10
-3
10
1
10 dB/Decade
R
i
2
A
s
t
P
WI
10
-2
10
50
100
0.5
5
2x10
-1
_
<
PEB 22320
Electrical Specification
Semiconductor Group
44
Figure 29
Tolerated Input Current at the RL1, RL2 Pins
ITD00577
20
10
1
-1
10
-10
-9
10
-6
10
-4
10
-3
10
1
6x10
10
-1
2x10
-1
A
s
P
WI
t
300
dB/Decade
10
R <
i
_
PEB 22320
Package Outlines
Semiconductor Group
45
5
Package Outlines
Plastic Package, P-LCC-44 (SMD)
(Plastic Leaded Chip Carrier)
GP
L05
102
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book "Package Information".
Dimensions in mm
SMD = Surface Mounted Device
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