Edition 02.97
This edition was realized using the software system FrameMaker

Published by Siemens AG,
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81541 München

Siemens AG 1997.

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SDA 5642-6/X
Revision History:

Current Version: 02.97

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SDA 5642-6/X

Table of Contents

Page

Semiconductor Group

02.97

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.2

Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.3

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.4

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

System Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1

Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2

C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2.1

General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2.2

Chip Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2.3

Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.2.4

Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.3

Order of Data Output on the

C Bus and Bit Allocation . . . . . . . . . . . . . . . 12

2.4

Description of DAVN and EHB Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

VPS-Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.1

Control Register Write (

C-Bus Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.2

Data Register Read (

C-Bus Read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.3

DAVN and EHB Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.4

Position of VPS Data Lines within the Vertical Blanking Interval . . . . . . . . . 23

5.5

Definition of Voltage Levels for VPS Data Line . . . . . . . . . . . . . . . . . . . . . . 23

5.6

Data Format of Programme Delivery Data in the Dedicated TV Line (VPS) 24

Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Purchase of Siemens

C components conveys the license under the Philips

C patent to use the components

in the

C system provided the system conforms to the

C specifications defined by Philips.

SDA 5642-6/X

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02.97

1.3

Pin Description

Pin No.

Symbol Function

P-DIP-14-1

P-DSO-20-1

Ground (0 V)

SSA

Analog ground (0 V)

SSD

Digital ground (0 V)

3, 8, 13, 18 N.C.

Not connected

SCL

Serial clock input of

C Bus.

SDA

Serial data input of

C Bus.

CS0

Chip select input determining the

C-Bus addresses:

/ 21

, when pulled low

/ 23

, when pulled high.

VCS

Video Composite Sync output from sync slicer used
for PLL based clock generation.

DAVN

Data available output active low, when VPS data is
received.

EHB

Output signaling the presence of the first field active
high.

Test input; activates test mode when pulled high.
Connect to ground for operating mode.

PD1

Phase detector/charge pump output of data PLL
(DAPLL).

PD2/
VCO2

Connector of the loop filter for the SYSPLL.

VCO1

Input to the voltage controlled oscillator #1 of the
DAPLL.

REF

Reference current input for the on-chip analog circuit.

CVBS

Composite video signal input.

Positive supply voltage (+ 5 V nom.).

DDD

Positive supply voltage for the digital circuits
(+ 5 V nom.).

DDA

Positive supply voltage for the analog circuits
(+ 5 V nom.).

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02.97

System Description

2.1

Functions

Referring to the functional block diagram of the VPS decoder, the composite video signal
with negative going sync pulses is coupled to the pin CVBS through a capacitor which is
used for clamping the bottom of the sync pulses to an internally fixed level. The signal is
passed on to the slicer, an analogue circuitry separating the sync and the data parts of
the CVBS signal, thus yielding the digital composite sync signal VCS and a digital data
signal for further processing by comparing those signals to internally generated slicing
levels.

The output of the sync separator is forwarded, on one hand, to the output pin VCS, and
on the other hand, to the clock generator and the timing block. The VCS signal
represents a key signal that is used for deriving a system clock signal by means of a PLL
and all other timing signal.

The data slicer separates the data signal from the CVBS signal by comparing the video
voltage to an internally generated slicing level which is found by averaging the data
signal during TV line no. 16.

The clock generator delivers the system clock needed for the basic timing as well as for
the regeneraton of the dataclock. It is based on two phase locked loops (PLL's) all parts
of which are integrated on chip with the exception of the loop filter components. Each of
the PLL's is composed of a voltage controlled relaxation oscillator (VCO), a phase/
frequency detector (PFD), and a charge pump which converts the digital output signals
of the PFD to an analogue current. That current is transformed to a control voltage for
the VCO by the off-chip loop filter. The generated VCO frequency is 10 MHz.

All signals necessary for the control of sync and data slicing as well as for the data
acquisition are generated by the Timing block.

The extracted data bits of TV line no. 16 are checked for biphase errors. With no biphase
errors encountered, the acquired bytes are stored in the transfer register to the

C Bus.

That transfer is signalled by a H/L transition of the DAVN output.

Data are updated when a new data line has been received, provided that the chip is not
accessed via the

C Bus at the same time.

A micro controller can read the stored bytes via the

C-Bus interface at any time.

However, one must be aware that the storage of new data from the acquisition interface
is inhibited as long as the VPS decoder is being accessed via the

C Bus.

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02.97

2.2

C Bus

2.2.1

General Information

The

C-Bus interface implemented on the VPS decoder is a slave transmitter/receiver,

i.e., both reading from and writing to the VPS decoder is possible. The clock line SCL is
controlled only by the bus master usually being a micro controller, whereas the SDA line
is controlled either by the master or by the slave. A data transfer can only be initiated by
the bus master when the bus is free, i.e., both SDA and SCL lines are in a high state. As
a general rule for the

C Bus, the SDA line changes state only when the SCL line is low.

The only exception to that rule are the Start Condition and the Stop Condition. Further
Details are given below. The following abbreviations are used:

START:

Start Condition generated by master

AS:

Acknowledge by slave

AM:

Acknowledge by master

NAM:

No Acknowledge by master

STOP:

Stop condition generated by master

2.2.2

Chip Address

There are two pairs of chip addresses, which are selected by the CS0-input pin
according to the following table:

CS0 Input

Write Mode

Read Mode

Low

20 (hex)

21 (hex)

High

22 (hex)

23 (hex)

SDA 5642-6/X

Semiconductor Group

02.97

2.2.3

Write Mode

For writing to the VPS decoder, the following format has to be used:

Description of Data Transfer (Write Mode)

Step1:

In order to start a data transfer the master generates a Start Condition on the
bus by pulling the SDA line low while the SCL line is held high.

Step 2:

The bus master puts the chip address on the SDA line during the next eight
SCL pulses.

Step 3:

The master releases the SDA line during the ninth clock pulse. Thus the slave
can generate an acknowledge (AS) by pulling the SDA line to a low level.

Step 4:

The controller transmits the data byte to set the Control register

Step 5:

The slave acknowledges the reception of the byte.

Step 6:

The master concludes the data communication by generating a Stop
Condition.

The write mode is used to set the

C-Bus control register which determines the

operating mode:

Control Register:

Default: All bits are set to 0 on power-up.

The bits T4 through T7 are used for test purposes and must not be changed for normal
operation by user software! (0 = normal operation)

You may write 00H, 01H, 02H, 03H, 04H, 05H, 06H, 07H, 08H, 09H, 0AH, 0BH, 0CH,
0DH, 0EH, 0FH to the register without efect. This enables the SDA 5642-6 to be used
for VPS decoding instead of the SDA 5050 or SDA 5649 without software problems.

Start

Chipaddress and Write Mode

Byte to set Control Register

AS Stop

Bit Number: 7

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02.97

2.2.4

Read Mode

For reading from the VPS decoder, the following format has to be used

The contents of up to 16 registers (bytes) can be read starting with byte 1 bit 7 (refer to
the table Order of Data Output on the

C Bus and...) depending on the selected

operating mode.

Description of Data Transfer (Read Mode)

Step1:

To start a data transfer the master generates a Start Condition on the bus by
pulling the SDA line low while the SCL line is held high. The byte address
counter in the decoder is reset and points to the first byte to be output.

Step 2:

The bus master puts the chip address on the SDA line during the next eight
SCL pulses.

Step 3:

The master releases the SDA line during the ninth clock pulse. Thus the slave
can generate an acknowledge (AS) by pulling the SDA line to a low level. At
this moment, the slave switches to transmitting mode.

Step 4:

During the next eight clock pulses the slave puts the addressed data byte
onto the SDA line.

Step 5:

The reception of the byte is acknowledged by the master device which, in
turn, pulls down the SDA line during the next SCL clock pulse. By
acknowledging a byte, the master prompts the slave to increment its internal
address counter and to provide the output of the next data byte.

Step 6:

Steps no. 4 and no. 5 are repeated, until the desired amount of bytes have
been read.

Step 7:

The last byte is output by the slave since it will not be acknowledged by the
master.

Step 8:

To conclude the read operation, the master doesn't acknowledge the last byte
to be received. A No Acknowledge by the master (NAM) causes the slave to
switch from transmitting to receiving mode. Note that the master can
prematurely cease any reading operation by not acknowledging a byte.

Step 9:

The master gains control over the SDA line and concludes the data transfer
by generating a Stop Condition on the bus, i. e., by producing a low/high
transition on the SDA line while the SCL line is in a high state. With the SDA
and the SCL lines being both in a high state, the

C Bus is free and ready for

another data transfer to be started.

Start

Chipaddress Read Mode

1st Byte

AM .....

Last Byte

NAM Stop

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02.97

2.4

Description of DAVN and EHB Outputs

DAVN

(Data Valid active low)

EHB

(First Field active high)

In test mode (i.e. TI = high), both DAVN and EHB are controlled by the CS0 pin and
reproduce the state of the CS0 input.

Signal Output

VPS Mode

DAVN

H/L-transition
(set low)

in line 16 when valid VPS data is received

L/H-transition
(set high)

at the start of line 16

always set high

on power-up or during

C-Bus accesses when the

bus master doesn't acknowledge in order to
generate the stop condition

EHB

L/H-transition

at the beginning of the first field

H/L-transition

at the beginning of the second field

SDA 5642-6/X

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02.97

Electrical Characteristics

Absolute Maximum Ratings

= 25

Parameter

Symbol

Limit Values

Unit Test

Condition

min.

typ.

max.

Ambient temperature

in operation

Storage temperature

stg

125

by storage

Total power dissipation

tot

300

Power dissipation per
output

Input voltage

0.3

Supply voltage

0.3

Thermal resistance

th SU

K/W

Note: Maximum ratings are absolute ratings; exceeding any one of these values may

cause irreversible damage to the integrated circuit.

Operating Range

Supply voltage

4.5

5.5

Supply current

Ambient temperature
range

Note: In the operating range the functions given in the circuit description are fulfilled.

SDA 5642-6/X

Semiconductor Group

02.97

Electrical Characteristics

= 25

Parameter

Symbol

Limit Values

Unit Test Condition

min.

typ.

max.

Input Signals SDA, SCL, CS0

H-input voltage

0.7

L-input voltage

0.3

Input capacitance

Input current

Input Signal TI

H-input voltage

0.9

L-input voltage

0.1

Input capacitance

Input current

Input Signals CVBS
(pos. Video, neg. Sync)

Video input signal
level

CVBS

0.7

1.0

2.0

2 Vpp with
0.8 V

SYNC

and

1.2 V

DAT

Synchron signal
amplitude

SYNC

0.15

0.3

0.8 (1.0)

1.0 V only related
to VCS signal
generation

Data amplitude

DAT

0.25
1.5

SYNC

0.5

1.2

Coupling capacitor

H-input current

= 5 V

L-input current

1000

400 100

= 0 V

Source impedance

250

Leakage resistance
at coupling capacitor

0.91

1.2

SDA 5642-6/X

Semiconductor Group

02.97

Output Signals DAVN, EHB, VCS

H-output voltage

0.5

= 100

L-output voltage

0.4

= 1.6 mA

Output Signals SDA (Open-Drain-Stage)

L-output voltage

0.4

= 3.0 mA

Permissible output
voltage

5.5

PLL-Loop Filter Components (see application circuit)

Resistance at PD2/
VCO2

6.8

Resistance at VCO1

1200

Attenuation
resistance

6.8

Resistance at PD2/
VCO2

1200

Integration capacitor

2.2

Integration capacitor

VCO Frequence Range Adjustment

Resistance at IREF
(for bias current
adjustment)

100

Note: The listed characteristics are ensured over the operating range of the integrated

circuit. Typical characteristics specify mean values expected over the production
spread. If not otherwise specified, typical characteristics apply at

= 25

C and

the given supply voltage.

Electrical Characteristics (cont'd)

= 25

Parameter

Symbol

Limit Values

Unit Test Condition

min.

typ.

max.

SDA 5642-6/X

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02.97

Figure 3

C-Bus Timing

All values referred to

and

levels.

Parameter

Symbol

Limit Values

Unit

min.

max.

Clock frequency

SCL

100

kHz

Inactive time prior to new transmission start-up

BUF

4.7

Hold time during start condition

HD; STA

4.0

Low-period of clock

LOW

4.7

High-period of clock

HIGH

4.0

Set-up time for data

SU;DAT

250

Rise time for SDA and SCL signal

TLH

Fall time for SDA and SCL signal

THL

300

Set-up time for SCL clock during stop condition

SU; STO

4.7

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