ICs for Communications
Memory Time Switch Large
MTSL
PEB 2047
PEB 2047-16
Version 2.1
Data Sheet 03.95
Edition 03.95
This edition was realized using the software
system FrameMaker
,
.
Published by Siemens AG,
Bereich Halbleiter, Marketing-
Kommunikation, Balanstrae 73,
81541 Mnchen
Siemens AG 1995.
All Rights Reserved.
Attention please!
As far as patents or other rights of third par-
ties are concerned, liability is only assumed
for components, not for applications, pro-
cesses and circuits implemented within com-
ponents or assemblies.
The information describes the type of compo-
nent and shall not be considered as assured
characteristics.
Terms of delivery and rights to change design
reserved.
For questions on technology, delivery and
prices please contact the Semiconductor
Group Offices in Germany or the Siemens
Companies and Representatives worldwide
(see address list).
Due to technical requirements components
may contain dangerous substances. For in-
formation on the types in question please
contact your nearest Siemens Office, Semi-
conductor Group.
Siemens AG is an approved CECC manufac-
turer.
Packing
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Components used in life-support devices
or systems must be expressly authorized
for such purpose!
Critical components
1
of the Semiconductor
Group of Siemens AG, may only be used in
life-support devices or systems
2
with the ex-
press written approval of the Semiconductor
Group of Siemens AG.
1 A critical component is a component used
in a life-support device or system whose
failure can reasonably be expected to
cause the failure of that life-support device
or system, or to affect its safety or effec-
tiveness of that device or system.
2 Life support devices or systems are in-
tended (a) to be implanted in the human
body, or (b) to support and/or maintain
and sustain human life. If they fail, it is rea-
sonable to assume that the health of the
user may be endangered.
Data Classification
Maximum Ratings
Maximum ratings are absolute ratings; exceeding only one of these values may cause
irreversible damage to the integrated circuit.
Characteristics
The listed characteristics are ensured over the operating range of the integrated circuit.
Typical characteristics specify mean values expected over the production spread. If not
otherwise specified, typical characteristics apply at
T
A
= 25
C and the given supply
voltage.
Operating Range
In the operating range the functions given in the circuit description are fulfilled.
For detailed technical information about "Processing Guidelines" and
"Quality Assurance" for ICs, see our "Product Overview".
PEB 2047
PEB 2047-16
Revision History:
Current Version: 03.95
Previous Version:
Data Book 01.94
Page
(in Version
01.94)
Page
(in new
Version)
Subjects (changes since last revision)
124
5
Version 2.1
127
8
Pin No. 6: INT open drain output
135
16
Figure 8: Improved
142
23
STAR: FSAD(2:1) position
143
25
MASK: Write address
148
31
Figure 12: 2
Data Rate, Figure 13: 1
Data Rate
153
36
Abs. Max. Ratings:
V
S
definition
154
37
t
LA
min. = 15 ns,
t
AH
min. = 15 ns,
t
RWD
min. = 0 ns
157
40
Figure 23:
t
RWD
158
41
t
S
min. = 15 ns
159
42
Sequence of 1., 2. and 3. bit of frame
PEB 2047
PEB 2047-16
Semiconductor Group
4
Table of Contents
Page
1
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.1
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
1.2
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
1.3
General Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
1.4
System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
2
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
2.1
MTSL Internal Timing and Channel Delay . . . . . . . . . . . . . . . . . . . . . . . . .15
2.2
Special Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3
Operational Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3.1
Initialization Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3.2
Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3.3
Indirect Access Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3.4
Frame Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4
Detailed Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.1
Mode Register (MOD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.2
Command Register (CMDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.3
Status Register (STAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4.4
Interrupt Status Register (ISTA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
4.5
Mask Register (MASK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
4.6
Indirect Access Register (IAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
4.7
Indirect Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
5
Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
6
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
6.1
Determination of MTSL Frame Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
6.2
Example for a MTSL Design guaranteeing
Constant Frame Delay for all Time Slots . . . . . . . . . . . . . . . . . . . . . . . . . .48
7
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Semiconductor Group
5
03.95
Memory Time Switch Large
(MTSL)
PEB 2047
PEB 2047-16
Preliminary Data
CMOS IC
Type
Ordering Code
Package
PEB 2047-N V2.1
Q67100-H6238
P-LCC-44 (SMD)
PEF 2047-N-16 V2.1
Q67100-H6301
P-LCC-44 (SMD)
P-LCC-44
1
Features
q
Non-blocking time/space switch for 2048-, 4096-, 8192- or
16 384-kbit/s PCM systems
q
Different modes programmable for input and output
separately
q
Configurable for a 4096-kHz, 8192-kHz or 16 384-kHz
device clock
q
Switching of up to 1024 incoming PCM channels to up to
1024 outgoing PCM channels
q
16 input and 8 output PCM lines
q
Tristate function for further expansion and tandem
operation
q
P read-access to PCM data
q
Programmable clock shift with half clock step resolution for
input and output
q
Individual line delay measurement and clock shift
mechanism for 8 PCM inputs
q
Built-in selftest
q
8-bit Motorola or Intel type
P interface
q
Constant or minimal channel-delay programmable on a per
time-slot basis
q
In-operation adjustment of bit-sampling without bit errors
q
Low power consumption
q
Single 5 V power supply
Important Note: All 16 384-MHz features described in this
data sheet are only available with the PEB 2047-16!
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