Semiconductor Group 1 1.96
2 097 152 words by 8-bit organization
0 to 70 C operating temperature
Performance:
Single + 3.3 V (
0.3V) supply
Low power dissipation
max. 432 active mW (-50 version)
max. 396 active mW (-60 version)
max. 360 active mW (-70 version)
7.2 mW standby (LV-TTL)
3.6 mW standby (CMOS)
Output unlatched at cycle end allows two-dimensional chip selection
Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh,
self refresh and test mode
Fast page mode capability
All inputs, outputs and clocks fully LVTTL-compatible
2048 refresh cycles / 32 ms
Plastic Package:
P-SOJ-28-3 400 mil
-50
-60
-70
tRAC
RAS access time
50
60
70
ns
tCAC
CAS access time
13
15
20
ns
tAA
Access time from address
25
30
35
ns
tRC
Read/Write cycle time
90
110
130
ns
tPC
Fast page mode cycle time
35
40
45
ns
2M x 8-Bit Dynamic RAM
Advanced Information
HYB3117800BSJ-50/-60/-70
Semiconductor Group
2
HYB 3117800BSJ-50/-60/-70
2M x 8-DRAM
The HYB 3117800BSJ is a 16 MBit dynamic RAM organized as 2097152 words by 8-bits. The HYB
3117800BSJ utilizes a submicron CMOS silicon gate process technology, as well as advanced
circuit techniques to provide wide operating margins, both internally and for the system user.
Multiplexed address inputs permit the HYB 3117800BSJ to be packaged in a standard SOJ 28
400 mil plastic package. These packages provide high system bit densities and are compatible with
commonly used automatic testing and insertion equipment. System-oriented features include single
+ 3.3 V (
0.3V) power supply, direct interfacing with high-performance logic device families.
Ordering Information
Pin Names
Type
Ordering Code
Package
Descriptions
HYB 3117800BSJ-50
Q67100-Q1147
P-SOJ-28-3 400 mil
3.3V DRAM (access time 50 ns)
HYB 3117800BSJ-60
Q67100-Q1148
P-SOJ-28-3 400 mil
3.3V DRAM (access time 60 ns)
HYB 3117800BSJ-70
P-SOJ-28-3 400 mil
3.3V DRAM (access time 70 ns)
A0 to A10
Row Address Inputs
A0 to A9
Column Address Inputs
RAS
Row Address Strobe
OE
Output Enable
I/O1-I/O8
Data Input/Output
CAS
Column Address Strobe
WE
Read/Write Input
V
CC
Power Supply (+ 3.3 V)
V
SS
Ground (0 V)
N.C.
not connected
Semiconductor Group
3
HYB 3117800BSJ-50/-60/-70
2M x 8-DRAM
Pin Configuration
P-SOJ-28-3 (400mil)
1
2
3
4
5
6
9
10
11
12
13
14
23
24
25
26
27
28
VSS
I/O8
I/O7
I/O6
I/O5
CAS
A8
A7
A6
A5
A4
VSS
VCC
I/O1
I/O2
I/O3
N.C.
A10
A0
A1
A2
A3
VCC
15
16
17
18
19
20
O
OE
A9
WE
I/O4
7
22
21
8
RAS
Semiconductor Group
4
HYB 3117800BSJ-50/-60/-70
2M x 8-DRAM
No. 2 Clock
Generator
Column
Address
Buffer(10)
Refresh
Controller
Refresh
Counter (11)
Address
Buffers(11)
Row
No. 1 Clock
Generator
&
Data in
Buffer
Data out
Buffer
Column
Decoder
Sense Amplifier
I/O Gating
Memory Array
2048x1024x8
Row
Decoder
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
WE
CAS
2048
1024
x8
.
RAS
10
11
8
I/O1
I
/O2
OE
11
11
A10
8
8
10
I
/O8
Block Diagram
Semiconductor Group
5
HYB 3117800BSJ-50/-60/-70
2M x 8-DRAM
Absolute Maximum Ratings
Operating temperature range ............................................................................................0 to 70 C
Storage temperature range......................................................................................... 55 to 150 C
Input/output voltage ...............................................................................-0.5 to min (Vcc+0.5, 4.6) V
Power supply voltage...................................................................................................-1.0V to 4.6 V
Power dissipation..................................................................................................................... 0.5 W
Data out current (short circuit) ................................................................................................ 50 mA
Note:
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of
the device. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
DC Characteristics
T
A
= 0 to 70 C,
V
SS
= 0 V,
V
CC
= 3.3 V
0.3V,
t
T
= 5 ns
Parameter
Symbol
Limit Values
Unit Test
Condition
min.
max.
Input high voltage
V
IH
2.0
Vcc+0.5
V
1)
Input low voltage
V
IL
0.5
0.8
V
1)
LVTTL Output high voltage (
I
OUT
= 2 mA)
V
OH
2.4
V
1)
LVTTL Output low voltage (
I
OUT
= 2 mA)
V
OL
0.4
V
1)
CMOS Output high voltage (
I
OUT
= 100
A)
V
OH
Vcc-0.2
V
CMOS Output low voltage (
I
OUT
= 100
A)
V
OL
0.2
V
)
Input leakage current,any input
(0 V
V
IH
Vcc + 0.3V, all other pins = 0 V)
I
I(L)
10
10
A
1)
Output leakage current
(DO is disabled, 0 V
V
OUT
Vcc + 0.3V)
I
O(L)
10
10
A
1)
Average
V
CC
supply current:
-50 ns version
-60 ns version
-70 ns version
(RAS, CAS, address cycling,
t
RC
=
t
RC
min.)
I
CC1
120
110
100
mA
mA
mA
2) 3) 4)
2) 3) 4)
2) 3) 4)
Standby
V
CC
supply current (RAS = CAS =
V
IH
)
I
CC2
2
mA
Average
V
CC
supply current, during RAS-only
refresh cycles:
-50 ns version
-60 ns version
-70 ns version
(RAS cycling: CAS =
V
IH
,
t
RC
=
t
RC
min.)
I
CC3
120
110
100
mA
mA
mA
2) 4)
2) 4)
2) 4)
Semiconductor Group
6
HYB 3117800BSJ-50/-60/-70
2M x 8-DRAM
Average
V
CC
supply current,
during fast page mode:
-50 ns version
-60 ns version
-70 ns version
(RAS =
V
IL
, CAS, address cycling,
t
PC
=
t
PC
min.
)
I
CC4
40
35
30
mA
mA
mA
2) 3) 4)
2) 3) 4)
2) 3) 4)
Standby
V
CC
supply current
(RAS = CAS =
V
CC
0.2 V)
I
CC5
1
mA
1)
Average
V
CC
supply current, during CAS-
before-RAS refresh mode: -50 ns version
-60 ns version
-70 ns version
(RAS, CAS cycling,
t
RC
=
t
RC
min
.)
I
CC6
120
110
100
mA
mA
mA
2) 4)
2) 4)
2) 4)
Average Self Refresh Current
(CBR cycle with tRAS>TRASSmin., CAS held low,
WE=Vcc-0.2V, Address and Din=Vcc-0.2V or 0.2V)
I
CC7
_
1
mA
Capacitance
T
A
= 0 to 70 C,
V
CC
= 3.3 V
0.3V,
f
= 1 MHz
Parameter
Symbol
Limit Values
Unit
min.
max.
Input capacitance (A0 to A10)
C
I1
5
pF
Input capacitance (RAS, CAS, WE, OE)
C
I2
7
pF
I/O capacitance (I/O1-I/O8)
C
IO
7
pF
DC Characteristics
(cont'd)
T
A
= 0 to 70 C,
V
SS
= 0 V,
V
CC
= 3.3 V
0.3V,
t
T
= 5 ns
Parameter
Symbol
Limit Values
Unit Test
Condition
min.
max.
Semiconductor Group
7
HYB 3117800BSJ-50/-60/-70
2M x 8-DRAM
AC Characteristics 5)6)
16F
T
A
= 0 to 70 C,
V
CC
= 3.3 V
0.3 V,
t
T
= 5 ns
Parameter
Symbol
Limit Values
Unit
Note
-50
-60
-70
min.
max. min.
max. min.
max.
common parameters
Random read or write cycle time
t
RC
90
110
130
ns
RAS precharge time
t
RP
30
40
50
ns
RAS pulse width
t
RAS
50
10k
60
10k
70
10k
ns
CAS pulse width
t
CAS
13
10k
15
10k
20
10k
ns
Row address setup time
t
ASR
0
0
0
ns
Row address hold time
t
RAH
8
10
10
ns
Column address setup time
t
ASC
0
0
0
ns
Column address hold time
t
CAH
10
15
15
ns
RAS to CAS delay time
t
RCD
18
37
20
45
20
50
RAS to column address delay
time
t
RAD
13
25
15
30
15
35
ns
RAS hold time
t
RSH
13
15
20
ns
CAS hold time
t
CSH
50
60
70
ns
CAS to RAS precharge time
t
CRP
5
5
5
ns
Transition time (rise and fall)
t
T
3
50
3
50
3
50
ns
7
Refresh period
t
REF
32
32
32
ms
Read Cycle
Access time from RAS
t
RAC
50
60
70
ns
8, 9
Access time from CAS
t
CAC
13
15
20
ns
8, 9
Access time from column address
t
AA
25
30
35
ns
8,10
OE access time
t
OEA
13
15
20
ns
Column address to RAS lead time
t
RAL
25
30
35
ns
Read command setup time
t
RCS
0
0
0
ns
Read command hold time
t
RCH
0
0
0
ns
11
Read command hold time
referenced to RAS
t
RRH
0
0
0
ns
11
CAS to output in low-Z
t
CLZ
0
0
0
ns
8
Output buffer turn-off delay
t
OFF
0
13
0
15
0
20
ns
12
Semiconductor Group
8
HYB 3117800BSJ-50/-60/-70
2M x 8-DRAM
Output buffer turn-off delay from
OE
t
OEZ
0
13
0
15
0
20
ns
12
Data to OE low delay
t
DZO
0
0
0
ns
13
CAS high to data delay
t
CDD
13
15
20
ns
14
OE high to data delay
t
ODD
13
15
20
ns
14
Write Cycle
Write command hold time
t
WCH
8
10
10
ns
Write command pulse width
t
WP
8
10
10
ns
Write command setup time
t
WCS
0
0
0
ns
15
Write command to RAS lead time
t
RWL
13
15
20
ns
Write command to CAS lead time
t
CWL
13
15
20
ns
Data setup time
t
DS
0
0
0
ns
16
Data hold time
t
DH
10
10
15
ns
16
Data to CAS low delay
t
DZC
0
0
0
ns
13
Read-Modify-Write Cycle
Read-write cycle time
t
RWC
126
150
180
ns
RAS to WE delay time
t
RWD
68
80
95
ns
15
CAS to WE delay time
t
CWD
31
35
45
ns
15
Column address to WE delay time
t
AWD
43
50
60
ns
15
OE command hold time
t
OEH
13
15
20
ns
Fast Page Mode Cycle
Fast page mode cycle time
t
PC
35
40
45
ns
CAS precharge time
t
CP
10
10
10
ns
Access time from CAS precharge
t
CPA
30
35
40
ns
7
RAS pulse width
t
RAS
50
200k
60
200k 70
200k
ns
CAS precharge to RAS Delay
t
RHPC
30
35
40
ns
AC Characteristics
(cont'd)
5)6)
16F
T
A
= 0 to 70 C,
V
CC
= 3.3 V
0.3 V,
t
T
= 5 ns
Parameter
Symbol
Limit Values
Unit
Note
-50
-60
-70
min.
max. min.
max. min.
max.
Semiconductor Group
9
HYB 3117800BSJ-50/-60/-70
2M x 8-DRAM
Fast Page Mode Read-Modify-Write Cycle
Fast page mode read-write cycle
time
t
PRWC
71
80
95
ns
CAS precharge to WE
t
CPWD
48
55
65
ns
CAS-before-RAS Refresh Cycle
CAS setup time
t
CSR
10
10
10
ns
CAS hold time
t
CHR
10
10
10
ns
RAS to CAS precharge time
t
RPC
5
5
5
ns
Write to RAS precharge time
t
WRP
10
10
10
ns
Write hold time referenced to RAS
t
WRH
10
10
10
ns
CAS-before-RAS Counter Test Cycle
CAS precharge time
t
CPT
35
40
40
ns
Test Mode
CAS hold time
t
CHRT
30
30
30
ns
Write command setup time
t
WTS
10
10
10
ns
Write command hold time
t
WTH
10
10
10
ns
Self Refresh Cycle
RAS pulse width
t
RASS
100k
100k
100k
ns
17
RAS precharge time
t
RPS
95
110
130
ns
17
CAS hold time
t
CHS
-50
-50
-50
ns
17
AC Characteristics
(cont'd)
5)6)
16F
T
A
= 0 to 70 C,
V
CC
= 3.3 V
0.3 V,
t
T
= 5 ns
Parameter
Symbol
Limit Values
Unit
Note
-50
-60
-70
min.
max. min.
max. min.
max.
Semiconductor Group
10
HYB 3117800BSJ-50/-60/-70
2M x 8-DRAM
Notes:
1) All voltages are referenced to VSS.
2) ICC1, ICC3, ICC4 and ICC6 depend on cycle rate.
3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open.
4) Address can be changed once or less while RAS = VIL. In the case of ICC4 it can be changed once or less
during a fast page mode cycle (tPC).
5) An initial pause of 200
s is required after power-up followed by 8 RAS cycles of which at least one cycle has
to be a refresh cycle, before proper device operation is achieved. In case of using internal refresh counter, a
minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.
6) AC measurements assume tT = 5 ns.
7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also
measured between VIH and VIL.
8) Measured with a load equivalent to 100 pF and at Voh=2.0 V (Ioh = -2mA) , Vol=0.8V (Iol=2mA).
9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a
reference point only: If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by
tCAC.
10)Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a
reference point only: If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by
tAA.
11)Either tRCH or tRRH must be satisfied for a read cycle.
12)tOFF (max.) and tOEZ (max.) define the time at which the outputs achieve the open-circuit condition and are
not referenced to output voltage levels.
13)Either tDZC or tDZO must be satisfied.
14)Either tCDD or tODD must be satisfied.
15)tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and the I/O pin
will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD
(min.), tAWD > tAWD (min.) and tCPWD > tCPWD (min.) , the cycle is a read-write cycle and I/O pins will
contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of
the I/O pins (at access time) is indeterminate.
16)These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge
in read-write cycles.
17)When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM
operation:
If row addresses are being refreshed on an evenly distributed manner over the refresh interval using CBR
refresh cycles, then only one CBR cycle must be performed immediately after exit from Self Refresh.
If row addresses are being refreshed in any other manner (ROR - Distributed/Burst; or CBR-Burst) over the
refresh interval, then a full set of row refreshes must be performed immediately before entry to and immediately
after exit from Self Refresh.
Semiconductor Group
11
HYB 3117800BSJ-50/-60/-70
2M x 8-DRAM
Read Cycle
Row
Column
Row
Valid Data Out
RAS
CAS
Address
WE
OE
I/O
(Inputs)
I/O
(Outputs)
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
t
RAS
t
RC
t
CSH
t
RAD
t
CAS
t
RP
t
RAH
t
CRP
t
RSH
t
RCD
t
RAL
t
ASR
t
CAH
t
ASC
t
ASR
t
RCH
t
RRH
t
RCS
t
AA
t
OEA
t
CLZ
t
CAC
t
OEZ
t
ODD
t
CDD
t
OFF
t
DZC
t
DZO
t
RAC
Hi Z
Hi Z
"H" or "L"
WL1
Semiconductor Group
12
HYB 3117800BSJ-50/-60/-70
2M x 8-DRAM
Write Cycle (Early Write)
RAS
CAS
Address
WE
OE
I/O
(Inputs)
I/O
(Outputs)
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
.
t
RAS
t
RC
t
CSH
t
RAD
t
CAS
t
RP
t
CRP
t
RSH
t
RCD
t
RAL
t
ASR
t
CAH
t
ASR
t
CWL
t
RWL
t
WP
t
ASC
t
WCH
Valid Data In
t
DS
t
DH
Hi Z
Column
Row
Row
t
RAH
t
WCS
"H" or "L"
WL2
Semiconductor Group
13
HYB 3117800BSJ-50/-60/-70
2M x 8-DRAM
Write Cycle (OE Controlled Write)
Valid Data
t
RWL
t
WP
t
OEH
t
ODD
t
CWL
t
DZO
t
OEA
t
CLZ
t
DS
t
OEZ
t
DH
t
RC
V
IH
V
IL
Row
t
DZC
"H" or "L"
Hi-Z
Hi-Z
Column
Row
t
ASC
t
RAD
t
RAL
t
CAH
t
RAH
RAS
CAS
Address
WE
OE
I/O
(Inputs)
I/O
(Outputs)
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
.
t
RAS
t
CSH
t
CAS
t
RP
t
CRP
t
RSH
t
RCD
t
ASR
t
ASR
WL3
Semiconductor Group
14
HYB 3117800BSJ-50/-60/-70
2M x 8-DRAM
Read-Write (Read-Modify-Write) Cycle
Row
Row
t
CSH
t
CAS
t
CRP
t
RWC
t
AWD
t
ASR
t
RP
t
RAS
t
RAH
t
CAH
I/O
(Outputs)
V
OH
V
OL
V
IH
V
IL
V
IH
V
IL
I/O
(Inputs)
OE
WE
V
IH
V
IL
t
ASR
Column
t
RCD
t
DH
t
RSH
t
RAD
t
CWD
t
OEH
t
RWD
t
RWL
t
CWL
t
CLZ
t
WP
t
RCS
t
AA
t
OEA
t
DS
t
DZC
t
DZO
t
ODD
t
CAC
t
OEZ
Valid
Data in
Data
Out
t
RAC
"H" or "L"
t
ASC
V
IH
V
IL
V
IH
V
IL
RAS
CAS
Address
V
IH
V
IL
WL4
Semiconductor Group
15
HYB 3117800BSJ-50/-60/-70
2M x 8-DRAM
Fast Page Mode Read Cycle
t
RASP
t
CAS
t
CAS
t
PC
t
CP
t
RCD
t
CSH
t
CAH
t
CAH
t
ASC
t
ASC
t
ASR
t
RAH
t
RAD
t
RCS
t
RCS
t
RCS
t
ASC
t
CAH
t
CAS
t
RSH
t
CRP
t
RP
t
ASR
t
RCH
t
CPA
t
OEA
t
OEA
t
AA
t
AA
t
DZC
t
DZC
t
CDD
t
RRH
t
CPA
t
OEA
t
AA
t
DZC
t
DZO
t
ODD
t
ODD
t
DZO
t
ODD
t
DZO
t
OFF
t
OEZ
t
OEZ
t
OFF
t
OEZ
t
CAC
t
CAC
t
CLZ
t
CLZ
t
CLZ
t
OFF
t
RAC
t
CAC
Valid
Data Out
Data Out
Data Out
Valid
Valid
Column
Column
Row
Row
RAS
I/O
(Outputs)
I/O
(Inputs)
OE
WE
Address
CAS
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
"H" or "L"
t
RHCP
t
RCH
V
OH
V
OL
Column
FPM1
Semiconductor Group
16
HYB 3117800BSJ-50/-60/-70
2M x 8-DRAM
Fast Page Mode Early Write Cycle
t
RAS
t
RP
t
RSH
t
CAS
t
CAS
t
CP
t
CRP
t
RAL
t
CAH
t
ASR
t
CWL
t
RWL
t
CAH
t
ASC
t
ASC
t
CWL
t
CWL
t
WCS
t
WCS
t
WCS
t
WCH
t
WP
t
WP
t
WCH
t
WP
t
WCH
t
RAD
t
CAS
t
RCD
t
PC
t
CAH
t
RAH
t
ASR
t
ASC
t
DH
t
DS
t
DS
t
DH
t
DH
t
DS
Column
Column
Column
Row
Valid
Data In
Valid
Valid
Data In
Data In
Column
HI-Z
RAS
I/O
(Outputs)
I/O
(Inputs)
OE
WE
Address
CAS
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
"H" or "L"
V
OH
V
OL
FPM2
Semiconductor Group
17
HYB 3117800BSJ-50/-60/-70
2M x 8-DRAM
Fast Page Mode Read-Modify-Write Cycle
t
CA
H
t
CP
t
DZC
t
DZ
O
t
RAC
t
CA
C
t
CL
Z
t
RC
S
t
AA
t
OEA
t
RC
D
t
RA
D
t
RA
H
t
ASR
t
AS
C
t
CAS
t
CA
S
t
PR
W
C
t
CW
D
t
CAH
t
AS
C
t
CAS
t
RSH
t
RP
t
CR
P
t
AS
R
t
CAH
t
AS
C
t
RAL
t
CW
D
t
RW
D
t
CW
L
t
CW
L
t
CW
D
t
AW
D
t
AW
D
t
WP
t
WP
t
CW
L
t
RW
L
t
AW
D
t
WP
t
OD
D
t
OE
H
t
DH
t
DS
t
CP
A
t
OE
Z
t
CL
Z
t
DZC
t
AA
t
CA
C
t
OEA
t
DS
t
OE
Z
t
DH
t
OEH
t
AA
t
OD
D
t
DZ
C
t
CP
A
t
OE
A
t
CL
Z
t
DS
t
DH
t
OEH
t
OD
D
RA
S
V
IH
V
IL
CA
S
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V OL
WE
OE
Address
I/
O
(Inputs
)
I/O
(Outputs)
D
a
ta
In
Da
ta
In
D
a
ta
I
n
Da
t
a
Ou
t
Ou
t
Da
ta
Da
ta
Ou
t
Ro
w
Co
l
u
mn
Address
Co
l
u
mn
Ro
w
t
RA
S
t
CS
H
Co
l
u
mn
t
CP
W
D
t
CPW
D
"
H
"
or "L
"
t
OE
Z
Semiconductor Group
18
HYB 3117800BSJ-50/-60/-70
2M x 8-DRAM
RAS-Only Refresh Cycle
t
CRP
t
RAH
t
RP
t
RAS
t
RC
t
ASR
t
ASR
t
RPC
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
Row
Row
HI-Z
Address
RAS
CAS
I/O
(Outputs)
"H" or "L"
WL9
Semiconductor Group
19
HYB 3117800BSJ-50/-60/-70
2M x 8-DRAM
CAS-Before-RAS Refresh Cycle
t
RP
t
RAS
t
RP
t
RC
t
CRP
t
CP
t
RPC
t
CHR
t
WRH
t
WRP
t
CSR
t
RPC
t
OFF
t
OEZ
t
CDD
t
ODD
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
HI-Z
"H" or "L"
RAS
I/O
(Outputs)
I/O
(Inputs)
OE
WE
CAS
V
OH
V
OL
WL10
Semiconductor Group
20
HYB 3117800BSJ-50/-60/-70
2M x 8-DRAM
Hidden Refresh Cycle (Read) Cycle
RAS
I/O
(Outputs)
I/O
(Inputs)
OE
WE
Address
CAS
t
RC
t
RC
t
RAS
t
RAS
t
RP
t
RP
t
CRP
t
CHR
t
RAD
t
CAH
t
ASC
t
RAH
t
ASR
t
ASR
t
RCS
t
RRH
t
AA
t
DZC
t
DZO
t
CAC
t
RAC
t
CLZ
t
OEZ
t
OFF
t
ODD
t
CDD
t
RCD
t
RSH
t
OEA
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
t
WRP
t
WRH
"H" or "L"
Valid Data Out
Row
Column
Row
HI-Z
V
OH
V
OL
WL11
Semiconductor Group
21
HYB 3117800BSJ-50/-60/-70
2M x 8-DRAM
Hidden Refresh Cycle (Early Write)
RAS
I/O
(Output)
I/O
(Input)
WE
Address
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
CAS
V
IH
V
IL
V
IH
V
IL
"H" or "L"
t
RC
t
RAS
t
RCD
t
RSH
t
RAD
t
CAH
t
WCS
t
WCH
t
WP
t
ASR
t
RAH
t
DS
t
DH
t
ASR
t
CRP
t
CHR
t
RP
t
RAS
t
RC
t
RP
t
ASC
Row
Row
Valid Data
HI-Z
Column
V
OH
V
OL
t
WRP
t
WRH
WL12
Semiconductor Group
22
HYB 3117800BSJ-50/-60/-70
2M x 8-DRAM
CAS before RAS Self Refresh Cycle
t
RPS
t
RASS
t
RP
t
CRP
t
CP
t
RPC
t
WRH
t
WRP
t
CSR
t
OFF
t
OEZ
t
CDD
t
ODD
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
HI-Z
"H" or "L"
RAS
I/O
(Outputs)
I/O
(Inputs)
OE
WE
CAS
V
OH
V
OL
t
CHS
WL13
Semiconductor Group
23
HYB 3117800BSJ-50/-60/-70
2M x 8-DRAM
CAS-Before-RAS Refresh Counter Test Cycle
t
CSR
t
ASR
t
ASC
t
CHR
t
CP
t
WRP
t
RAL
t
CAH
t
RSH
t
RP
t
RAS
t
CAS
t
RCS
t
CDD
t
CAC
t
AA
t
WRH
t
OEA
t
ODD
t
CLZ
t
DZC
t
DZO
t
OEZ
t
OFF
t
RWL
t
CWL
t
WCH
t
WCS
t
WRH
t
WRP
t
DS
t
DH
V
IH
V
IL
V
IH
V IL
V
IH
V IL
VOH
VOL
V
IH
V IL
V
IH
V IL
V
IH
V IL
V
IH
V IL
V
IH
V IL
V
IH
V IL
V
IH
V IL
RAS
I/O
(Inputs)
OE
WE
Address
CAS
I/O
(Outputs)
I/O
(Outputs)
I/O
(Inputs)
WE
OE
Column
Row
Data Out
Data In
HI-Z
Read Cycle:
Write Cycle:
t
RRH
t
RCH
Semiconductor Group
24
HYB 3117800BSJ-50/-60/-70
2M x 8-DRAM
Test Mode Entry
t
RC
t
RAS
t
RP
t
RPC
t
CRP
t
CHR
t
WTH
t
RPC
t
RP
t
CP
t
CSR
t
WTS
t
CDD
t
OFF
t
OEZ
t
ODD
I/O
(Outputs)
V
OH
V
OL
V
IH
V
IL
V
IH
V
IL
I/O
(Inputs)
OE
WE
V
IH
V
IL
CAS
RAS
V
IH
V
IL
V
IH
V
IL
"H" or "L"
HI-Z
Address
t
RAH
t
ASR
V
IH
V
IL
Row
WL15
HI-Z
Semiconductor Group
25
HYB 3117800BSJ-50/-60/-70
2M x 8-DRAM
Test Mode
As the HYB 3117800BSJ is organized internally as 1M x 16-bits, a test mode cycle using 2:1
compression can be used to improve test time. Note that in the 2M x 8 version the test time is
reduced by 1/2 for a N test pattern.
In a test mode "write" the data from each I/O pin is written into two 1M blocks simultaneously (all "1"
s or all "0" s). In test mode "read" each I/O output is used for indicating the test mode result. If the
internal two bits are equal, the I/O would indicate a "1". If they were not equal, the I/O would indicate
a "0". The WCBR cycle (WE, CAS before RAS) puts the device into test mode. To exit from test
mode, a "CAS before RAS refresh", "RAS only refresh" or "Hidden refresh" can be used. Refresh
during test mode operation can be performed by normal read cycles or by WCBR refresh cylces.
Row addresses A0 through A9 have to kept high to perform a testmode entry cycle. All other
addresses are don't care.
Semiconductor Group
26
HYB 3117800BSJ-50/-60/-70
2M x 8-DRAM
Package Outlines
Plastic Package P-SOJ-28-3 (400 mil)
(Small Outline J-lead, SMD)
1) Does not include plastic or metal protrusion of 0.15 max. per side
28x
0.18
1.27
0.81max
-0.13
0.51
0.18
1)
1)
-0.25
18.54
Index Marking
0.1
1
14
15
28
10.16
+0.13
9.4
11.18
+0.13
0.25
-
+
30
O
M
M
-
-
GPJ05699
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