Semiconductor Group

1998-10-01

16 MBit Synchronous DRAM
(second generation)

Advanced Information

The HYB 39S1640x/80x/16xAT are dual bank Synchronous DRAM's based on the die revisions "B"
and "C" and organized as 2 banks

2 MBit

4, 2 banks

1 MBit

8 and 2 banks

512 kBit

respectively. These synchronous devices achieve high speed data transfer rates up to 125 MHz by
employing a chip architecture that prefetches multiple bits and then synchronizes the output data to
a system clock. The chip is fabricated with SIEMENS advanced 16 MBit DRAM process technology.

The device is designed to comply with all JEDEC standards set for synchronous DRAM products,
both electrically and mechanically. All of the control, address, data input and output circuits are
synchronized with the positive edge of an externally supplied clock.

Operating the two memory banks in an interleaved fashion allows random access operation to occur
at higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to
125 MHz is possible depending on burst length, CAS latency and speed grade of the device.

Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single
3.3 V

0.3 V power supply and are available in TSOPII packages.

· High Performance:

· Single Pulsed RAS Interface

· Fully Synchronous to Positive Clock Edge

· 0 to 70

C operating temperature

· Dual Banks controlled by A11 (Bank Select)

· Programmable CAS Latency: 1, 2, 3

· Programmable Wrap Sequence: Sequential

or Interleave

· Programmable Burst Length:

1, 2, 4, 8 and full page for Sequential type
1, 2, 4, 8 for Interleave type

CAS latency = 3

-8

-10

Units

125

100

MHz

CK3

AC3

· Multiple Burst Read with Single Write

Operation

· Automatic and Controlled Precharge

Command

· Data Mask for Read/Write control (

· Dual Data Mask for byte control (

16)

· Auto Refresh (CBR) and Self Refresh

· Suspend Mode and Power Down Mode

· 4096 refresh cycles/64 ms

· Random Column Address every CLK

(1-N Rule)

· Single 3.3 V

0.3 V Power Supply

· LVTTL Interface versions

· Plastic Packages:

P-TSOPII-44-1 400 mil width (

P-TSOPII-50-1 400 mil width (

16)

HYB 39S16400/800/160AT-8/-10

HYB 39S16400/800/160AT-8/-10

16 MBit Synchronous DRAM

Semiconductor Group

1998-10-01

Ordering Information

Type

Ordering Code Package

Description

LVTTL-Version

HYB 39S16400AT-8 Q67100-Q1333 P-TSOPII-44-1 (400 mil) 125 MHz 2B

2 M

4 SDRAM

PC66 2-2-2

HYB 39S16400AT-10 Q67100-Q1323 P-TSOPII-44-1 (400 mil) 100 MHz 2B

2 M

4 SDRAM

PC66 2-2-2

HYB 39S16800AT-8 Q67100-Q1335 P-TSOPII-44-1 (400 mil) 125 MHz 2B

1 M

8 SDRAM

PC66 2-2-2

HYB 39S16800AT-10 Q67100-Q1327 P-TSOPII-44-1 (400 mil) 100 MHz 2B

1 M

8 SDRAM

PC66 2-2-2

HYB 39S16160AT-8 Q67100-Q1337 P-TSOPII-50-1 (400 mil) 125 MHz 2B

512 k

16 SDRAM

HYB 39S16160AT-10 Q67100-Q1331 P-TSOPII-50-1 (400 mil) 100 MHz 2B

512 k

16 SDRAM

Pin Names

CLK

Clock Input

Data Input/Output

CKE

Clock Enable

DQM, LDQM,
UDQM

Data Mask

Chip Select

Power (+ 3.3 V)

RAS

Row Address Strobe

Ground

CAS

Column Address Strobe

DDQ

Power for DQ's (+ 3.3 V)

Write Enable

SSQ

Ground for DQ's

A0 - A10

Address Inputs

Not connected

A11 (BS)

Bank Select

HYB 39S16400/800/160AT-8/-10

16 MBit Synchronous DRAM

Semiconductor Group

1998-10-01

Signal Pin Description

Pin

Type

Signal Polarity Function

CLK

Input

Pulse

Positive
Edge

The system clock input. All of the SDRAM inputs are
sampled on the rising edge of the clock.

CKE

Input

Level

Active
High

Activates the CLK signal when high and deactivates the
CLK signal when low, thereby initiates either the Power
Down mode, Suspend mode or the Self Refresh mode.

Input

Pulse

Active
Low

CS enables the command decoder when low and disables
the command decoder when high. When the command
decoder is disabled, new commands are ignored but
previous operations continue.

RAS
CAS
WE

Input

Pulse

Active
Low

When sampled at the positive rising edge of the clock,
CAS, RAS and WE define the command to be executed by
the SDRAM.

A0 - A10

Input

Level

During a Bank Activate command cycle, A0 - A10 defines
the row address (RA0 - RA10) when sampled at the rising
clock edge.
During a Read or Write command cycle, A0 - A9 defines
the column address (CA0 - CAn) when sampled at the
rising clock edge. CAn depends from the SDRAM
organisation.
4M

4 SDRAM CAn = CA9

8 SDRAM CAn = CA8

16 SDRAM CAn = CA7

In addition to the column address, A10 is used to invoke
autoprecharge operation at the end of the burst read or
write cycle. If A10 is high, autoprecharge is selected and
A11 defines the bank to be precharged (low = bank A,
high = bank B). If A10 is low, autoprecharge is disabled.
During a Precharge command cycle, A10 is used in
conjunction with A11 to control which bank(s) to
precharge. If A10 is high, both bank A and bank B will be
precharged regardless of the state of A11. If A10 is low,
then A11 is used to define which bank to precharge.

A11 (BS)

Input

Level

Selects which bank is to be active. A11 low selects bank A
and A11 high selects bank B.

DQx

Input
Output

Level

Data Input/Output pins operate in the same manner as on
conventional DRAMs.

HYB 39S16400/800/160AT-8/-10

16 MBit Synchronous DRAM

Semiconductor Group

1998-10-01

DQM
LDQM
UDQM

Input

Pulse

Active
High

The Data Input/Output mask places the DQ buffers in a
high impedance state when sampled high. In Read mode,
DQM has a latency of two clock cycles and controls the
output buffers like an output enable. In Write mode, DQM
has a latency of zero and operates as a word mask by
allowing input data to be written if it is low but blocks the
write operation if DQM is high.

Supply

Power and ground for the input buffers and the core logic.

DDQ

SSQ

Supply

Isolated power supply and ground for the output buffers to
provide improved noise immunity.

Signal Pin Description (cont'd)

Pin

Type

Signal Polarity Function

HYB 39S16400/800/160AT-8/-10

16 MBit Synchronous DRAM

Semiconductor Group

1998-10-01

Block Diagram for HYB 39S16400T (2 banks

4 M

4 SDRAM)

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11 (BS)

Address Buffers (12)

CLK Buffer

CLK

Row

Address

Counter

CS Buffer

RAS Buffer

CAS Buffer

WE Buffer

DQM Buffer

RAS

CAS

DQM

Command Decoder

Self

Refresh Clock

CKE Buffer

CKE

2048 x 1024

Memory Bank A

and DQ Gate

Sense Amplifiers

Row/Column

Select

Bank A

Predecode A

Sequential

Mode Register

Control

Bank A

Control

Predecode B

Bank B

Sequential

Row/Column

Bank B

Select

Row Decoder

Data Latches

and DQ Gate

Row Decoder

Memory Bank B

2048 x 1024

Sense Amplifiers

Data Input/Output Buffers

2048

DQ0

DQ1

DQ2

DQ3

Column Decoder

SPB02835

1024

HYB 39S16400/800/160AT-8/-10

16 MBit Synchronous DRAM

Semiconductor Group

1998-10-01

Block Diagram for HYB 39S16800T (2 banks

1 M

8 SDRAM)

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11 (BS)

Address Buffers (12)

CLK Buffer

CLK

Row

Address
Counter

CS Buffer

RAS Buffer

CAS Buffer

WE Buffer

DQM Buffer

RAS

CAS

DQM

Command Decoder

Self

Refresh Clock

CKE Buffer

CKE

2048 x 512

Memory Bank A

and DQ Gate

Sense Amplifiers

Row/Column

Select

Bank A

Predecode A

Sequential

Mode Register

Control

Bank A

Control

Predecode B

Bank B

Sequential

Row/Column

Bank B

Select

Row Decoder

Data Latches

and DQ Gate

Memory Bank B

2048 x 512

Sense Amplifiers

Data Input/Output Buffers

2048

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

Column Decoder

SPB02836

Row Decoder

512

HYB 39S16400/800/160AT-8/-10

16 MBit Synchronous DRAM

Semiconductor Group

1998-10-01

Block Diagram for HYB 39S16160T (2 banks

512 k

16 SDRAM)

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11 (BS)

Address Buffers (12)

CLK Buffer

CLK

Row

Address
Counter

CS Buffer

RAS Buffer

CAS Buffer

WE Buffer

DQM Buffer

RAS

CAS

UDQM

LDQM

Command Decoder

Self

Refresh Clock

CKE Buffer

CKE

2048 x 256

Memory Bank A

and DQ Gate

Sense Amplifiers

Row/Column

Select

Bank A

Predecode A

Sequential

Mode Register

Control

Bank A

Control

Predecode B

Bank B

Sequential

Row/Column

Bank B

Select

Row Decoder

Data Latches

and DQ Gate

Row Decoder

Memory Bank B

2048 x 256

Sense Amplifiers

Data Input/Output Buffers

2048

256

2048

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

Column Decoder

SPB02837

HYB 39S16400/800/160AT-8/-10

16 MBit Synchronous DRAM

Semiconductor Group

1998-10-01

Operation Definition

All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at
the positive edge of the clock. The following list shows the most important operation commands.

Mode Register

For application flexibility, a CAS latency, a burst length, and a burst sequence can be programmed
in the SDRAM mode register. The mode set operation must be done before any activate command
after the initial power up. Any content of the mode register can be altered by reexecuting the mode
set command. Both banks must be in precharged state and CKE must be high at least one clock
before the mode set operation. After the mode register is set, a Standby or NOP command is
required. Low signals of RAS, CAS, and WE at the positive edge of the clock activate the mode set
operation. Address input data at this timing defines parameters to be set as shown in the following
table.

Operation

RAS

CAS

(L/U)DQM

Standby, Ignore RAS, CAS, WE and Address

Row Address Strobe and Activating a Bank

Column Address Strobe and Read Command

Column Address Strobe and Write Command

Precharge Command

Burst Stop Command

Self Refresh Entry

Mode Register Set Command

Write Enable/Output Enable

Write Inhibit/Output Disable

No Operation (NOP)

HYB 39S16400/800/160AT-8/-10

16 MBit Synchronous DRAM

Semiconductor Group

1998-10-01

Address Input for Mode Set (Mode Register Operation)

SPD03138

A10

Burst Length

CAS Latency

Operation Mode

Address Bus (Ax)

Mode Register (Mx)

Operation Mode

M10

M11

Mode

Normal

with Single

Multiple Burst

Write

Reserve

Latency

CAS Latency

Reserve

Sequential Burst Addressing

Interleave Burst Addressing

2
3
4
5
6
7

4
5
6
7

6
7

Sequential

Type

Interleave

Burst Type

Full Page

Reserve

Burst Length

Sequential

Interleave

Length

Reserve

optional

HYB 39S16400/800/160AT-8/-10

16 MBit Synchronous DRAM

Semiconductor Group

1998-10-01

Read and Write Access Mode

When RAS is low and both CAS and WE are high at the positive edge of the clock, a RAS cycle
starts. According to address data, a word line of the selected bank is activated and all of sense
amplifiers associated to the word line are fired. A CAS cycle is triggered by setting RAS high and
CAS low at a clock timing after a necessary delay,

RCD

, from the RAS timing. WE is used to define

either a read (WE = H) or a write (WE = L) at this stage.

SDRAM provides a wide variety of fast access modes. In a single CAS cycle, serial data read or
write operations are allowed at up to a 125 MHz data rate. The numbers of serial data bits are the
burst length programmed at the mode set operation, i.e., one of 1, 2, 4, 8 and full page. Column
addresses are segmented by the burst length and serial data accesses are done within this
boundary. The first column address to be accessed is supplied at the CAS timing and the
subsequent addresses are generated automatically by the programmed burst length and its
sequence. For example, in a burst length of 8 with interleave sequence, if the first address is `2',
then the rest of the burst sequence is 3, 0, 1, 6, 7, 4, and 5.

Full page burst operation is only possible using the sequential burst type and page length is a
function of the I/O organisation and column addressing. Full page burst operation do not self
terminate once the burst length has been reached. In other words, unlike burst length of 2, 3 or 8,
full page burst continues until it is terminated using another command.

Similar to the page mode of conventional DRAM's, burst read or write accesses on any column
address are possible once the RAS cycle latches sense amplifiers. The maximum

RAS

or the refresh

interval time limits the number of random column accesses. A new burst access can be done even
before the previous burst ends. The interrupt operation at every clock cycles is supported. When the
previous burst is interrupted, the remaining addresses are overridden by the new address with the
full burst length. An interrupt which accompanies with an operation change from a read to a write is
possible by exploiting DQM to avoid bus contention.

When two banks are activated sequentially, interleaved bank read or write operations are possible.
With the programmed burst length, alternate access and precharge operations on two banks can
realize fast serial data access modes among many different pages. Once two banks are activated,
column to column interleave operation can be done between two different pages.

Refresh Mode

SDRAM has two refresh modes, a CAS-before-RAS (CBR) automatic refresh and a self refresh. All
of banks must be precharged before applying any refresh mode. An on-chip address counter
increments the word and the bank addresses and no bank information is required for both refresh
modes. The chip enters the automatic refresh mode, when RAS and CAS are held low and CKE and
WE are held high at a clock timing. The mode restores word line after the refresh and no external
precharge command is necessary. A minimum

time is required between two automatic

refreshes in a burst refresh mode. The same rule applies to any access command after the
automatic refresh operation.

The chip has an on-chip timer and the self refresh mode is available. It enters the mode when RAS,
CAS, and CKE are low and WE is high at a clock timing. All of external control signals including the
clock are disabled. Returning CKE to high enables the clock and initiates the refresh exit operation.
After the exit command, at least one

delay is required prior to any access command.

HYB 39S16400/800/160AT-8/-10

16 MBit Synchronous DRAM

Semiconductor Group

1998-10-01

DQM Function

DQM has two functions for data I/O read write operations. During reads, when it turns to high at a
clock timing, data outputs are disabled and become high impedance after two clock delay (DQM
Data Disable Latency

DQZ

). It also provides a data mask function for writes. When DQM is activated,

the write operation at the next clock is prohibited (DQM Write Mask Latency

DQW

= zero clocks).

Suspend Mode

During normal access mode, CKE is held high and CLK is enabled. When CKE is low, it freezes the
internal clock and extends data read and write operations. One clock delay is required for mode
entry and exit (Clock Suspend Latency

CSL

Power Down

In order to reduce standby power consumption, a power down mode is available. Bringing CKE low
enters the power down mode and all of receiver circuits are gated. All banks must be precharged
before entering this mode. One clock delay is required for mode entry and exit. The Power Down
mode does not perform any refresh operation.

Auto Precharge

Two methods are available to precharge SDRAMs. In an automatic precharge mode, the CAS
timing accepts one extra address, CA10, to determine whether the chip restores or not after the
operation. If CA10 is high when a Read Command is issued, the Read with Auto-Precharge function
is initiated. The SDRAM automatically enters the precharge operation one clock after the Read
Command is registered for CAS latencies of 1 and 2, and two clocks for CAS latencies of 3. If
CAS10 is high when a Write Command is issued, the Write with Auto-Precharge function is initiated.
The SDRAM automatically enters the precharge operation one clock delay form the last data-in for
CAS latencies of 1 and 2 and two clocks for CAS latencies of 3. This delay is referenced as

DPL

Precharge Command

If CA10 is low, the chip needs another way to precharge. In this mode, a separate precharge
command is necessary. When RAS and WE are low and CAS is high at a clock timing, it triggers the
precharge operation. Two address bits, A10 and A11, are used to define banks as shown in the
following list. The precharge command may be applied coincident with the last of burst reads for
CAS Latency = 1 and with the second to the last read data for CAS Latencies = 2 & 3. Writes
require a time

DPL

from the last burst data to apply the precharge command.

HYB 39S16400/800/160AT-8/-10

16 MBit Synchronous DRAM

Semiconductor Group

1998-10-01

Burst Termination

Once a burst read or write operation has been initiated, there are several methods in which to
terminate the burst operation prematurely. These methods include using another Read or Write
Command to interrupt an existing burst operation, use a Precharge Command to interrupt a burst
cycle and close the active bank, or using the Burst Stop Command to terminate the existing burst
operation but leave the bank open for future Read or Write Commands to the same page of the
active bank. When interrupting a burst with another Read or Write Command care must be taken to
avoid DQ contention. The Burst Stop Command, however, has the fewest restrictions making it the
easiest method to use when terminating a burst operation before it has been completed. If a Burst
Stop command is issued during a burst write operation, then any residual data from the burst write
cycle will be ignored. Data that is presented on the DQ pins before the Burst Stop Command is
registered will be written to the memory.

Power Up Procedure

All

and

DDQ

must reach the specified voltage no later than any of input signal voltages. An

initial pause of 200

s is required after power on. All banks have to be precharged and a minimum

of 2 auto-refresh cycles are required prior to the mode register set operation.

Bank Selection by Address Bits

A10

A11

Bank A only

Low

Bank B only

Low

High

Both A and B

High

Don't Care

HYB 39S16400/800/160AT-8/-10

16 MBit Synchronous DRAM

Semiconductor Group

1998-10-01

Absolute Maximum Ratings

Operating temperature range ........................................................................................ 0 to + 70

Storage temperature range..................................................................................... 55 to + 150

Input/output voltage .......................................................................... 0.5 to min (

+ 0.5, 4.6) V

Power supply voltage

DDQ

............................................................................. 1.0 to + 4.6 V

Power Dissipation ....................................................................................................................... 1 W

Data out current (short circuit) ................................................................................................ 50 mA

Note: Stresses above those listed under

Absolute Maximum Ratings

may cause permanent

damage of the device. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.

Recommended Operation and Characteristics for LV-TTL Versions

= 0 to 70

= 0 V;

DDQ

= 3.3 V

0.3 V

Parameter

Symbol

Limit Values

Unit

Notes

min.

max.

Input high voltage

2.0

+ 0.3

1, 2

Input low voltage

0.3

0.8

1, 2

Output high voltage (

OUT

= 2.0 mA)

2.4

Output low voltage (

OUT

= 2.0 mA)

0.4

Input leakage current, any input
(0 V <

DDQ

, all other inputs = 0 V)

I(L)

Output leakage current
(DQ is disabled, 0 V <

OUT

)

O(L)

Capacitance

= 0 to 70

= 3.3 V

0.3 V,

= 1 MHz

Parameter

Symbol max. Values

Unit

Input capacitance (A0 to A11)

Input capacitance (RAS, CAS, WE, CS, CLK, CKE, DQM)

Output capacitance (DQ)

REF

HYB 39S16400/800/160AT-8/-10

16 MBit Synchronous DRAM

Semiconductor Group

1998-10-01

Operating Currents

= 0 to 70

= 3.3 V

0.3 V

(Recommended Operating Conditions unless otherwise noted)

Parameter

Symbol Test Condition

CAS
Latency

-8

-10

Unit Note

max. max.

Operating current

CC1

Burst Length = 4

RC(MIN.)

CK(MIN.)

= 0 mA

2 bank interleave operation

1
2
3

80
115
125

65
90
100

mA
mA
mA

6, 7

Precharge
Standby current in
Power Down
Mode

CC2P

CKE

IL(MAX.)

CK(MIN.)

CC2PS

CKE

IL(MAX.)

= infinite

Precharge
Standby current in
Non-power down
Mode

CC2N

CKE

IH(MIN.)

CK(MIN.)

input signals

changed once in 3 cycles

CS = High

CC2NS

CKE

IH(MIN.)

= infinite,

input signals are stable

Active Standby
current in Power
Down Mode

CC3P

CKE

IL(MAX).

CK(MIN.)

CC3PS

CKE

IL(MAX.)

= infinite, input signals

are stable

Active Standby
current in Non-
power Down
Mode

CC3N

CKE

IH(MIN.)

CK(MIN.)

, changed once

in 3 cycles

CS = High

CC3NS

CKE

IH(MIN.)

= infinite, input signals

are stable

Burst Operating
current

CC4

Burst Length = full page

= infinite

CK(MIN.)

= 0 mA

2 banks activated

1
2
3

50
80
120

40
65
95

6, 7

Auto (CBR)
Refresh current

CC5

RC(MIN.)

1
2
3

75
95
115

60
75
90

mA
mA
mA

6, 7

Self Refresh

CC6

CKE

0.2 V

6, 7

HYB 39S16400/800/160AT-8/-10

16 MBit Synchronous DRAM

Semiconductor Group

1998-10-01

AC Characteristics

8, 9

= 0 to 70

= 0 V;

= 3.3 V

0.3 V,

= 1 ns

Parameter

Symbol

Limit Values

Unit

Note

-8

-10

min.

max.

min.

max.

Clock and Clock Enable

Clock Cycle time

CAS Latency = 3
CAS Latency = 2
CAS Latency = 1

8
12
24

10
15
30

ns
ns
ns

System frequency

CAS Latency = 3
CAS Latency = 2
CAS Latency = 1

125
83
41

100
66
33

MHz
MHz
MHz

Clock Access time

CAS Latency = 3
CAS Latency = 2
CAS Latency = 1

7
8
21

8
9
27

ns
ns
ns

Clock High Pulse width

3.5

Clock Low Pulse width

3.5

Transition time (rise and fall)

Setup and Hold Times

Command Setup time

2.5

Address Setup time

2.5

Data In Setup time

2.5

CKE Setup time

CKS

2.5

CKE Set-up time (Power down mode)

CKSP

2.5

CKE Set-up time (Self Refresh Exit)

CKSR

Command Hold time

Address Hold time

Data In Hold time

CKE Hold time

CKH

HYB 39S16400/800/160AT-8/-10

16 MBit Synchronous DRAM

Semiconductor Group

1998-10-01

Common Parameters

Row to Column Delay time

RCD

Row Active time

RAS

120k

Precharge time

Row Cycle time

120k

Bank to Bank delay time

RRD

CAS to CAS delay time (same bank)

CCD

CLK

Refresh Cycle

Self Refresh Exit time

SREX

2 CLK +

Refresh period (4096 cycles)

REF

Read Cycle

Data Out Hold time

Data Out to Low Impedance time

Data Out to High Impedance time

CAS Latency = 3
CAS Latency = 2
CAS Latency = 1

5
7
19

6
8
25

ns
ns
ns

DQM Data Out Disable Latency

DQZ

CLK

Write Cycle

Last Data-Input to Precharge
(Write Recovery Latency)

CL = 1, 2
CL = 3

DPL

1
2

CLK
CLK

DQM Write Mask Latency

DQW

CLK

AC Characteristics (cont'd)

8, 9

= 0 to 70

= 0 V;

= 3.3 V

0.3 V,

= 1 ns

Parameter

Symbol

Limit Values

Unit

Note

-8

-10

min.

max.

min.

max.

HYB 39S16400/800/160AT-8/-10

16 MBit Synchronous DRAM

Semiconductor Group

1998-10-01

Notes

All voltages are referenced to

may overshoot to

+ 2.0 V for pulse width of < 4 ns with 3.3 V.

may undershoot to

2.0 V for pulse width < 4.0 ns with 3.3 V. Pulse width measured at 50 % points with amplitude
measured peak to DC reference.

Under all conditions

DDQ

must be less than or equal to

The value of

REF

may be selected by the user to provide optimum noise margin in the system.

REF

has to be in the range between 0.43

DDQ

and 0.47

DDQ

and is expected to track

variations in

DDQ

may overshoot to

DDQ

+ 1.2 V for pulse width < 5 ns and

may undershoot to

SSQ

1.2 V for pulse width < 5 ns.

The specified values are valid when addresses are changed no more than three times during

RC(MIN.)

and when No Operation commands are registered on every rising clock edge during

RC(MIN.)

The specified values are valid when data inputs (DQ's) are stable during

RC(MIN.)

An initial pause of 200

s is required after power-up, then a Precharge All Banks command

must be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set
Operation can begin.

AC timing tests for LV-TTL versions have

= 0.4 V and

= 2.4 V with the timing referenced

to the 1.4 V crossover point. The transition time is measured between

and

. All AC

measurements assume

= 1 ns with the AC output load circuit shown in figure below.

10. If clock rising time is longer than 1 ns, (

/2 0.5) ns has to be added to this parameter.

11. If

is longer than 1 ns, a time (

1) ns has to be added to this parameter.

12. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh

commands must be given to "wake-up" the device.

13. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after

CKE returns high. Self Refresh Exit is not complete until a time period equal to

is satisfied

once the Self Refresh Exit command is registered.

14. Referenced to the time which the output achieves the open circuit condition, not to output

voltage levels.

HYB 39S16400/800/160AT-8/-10

16 MBit Synchronous DRAM

Semiconductor Group

1998-10-01

Clock Frequency and Latency

Parameter

Symbol

Speed Sort

Unit

-8

-10

Clock frequency

max.

125

100

MHz

Clock Cycle time

min.

CAS latency

min.

CLK

Row to Column delay

min.

RCD

CLK

RAS latency

min.

CLK

Row Active time

min.

RAS

CLK

max.

RAS

120

Row Precharge time

min.

CLK

Row Cycle time

min.

CLK

Last Data-In to Precharge (Write Recovery)

min.

DPL

CLK

Last Data-In to Active/Refresh

min.

DPL

CLK

Bank to Bank delay time

min.

RRD

CLK

CAS to CAS delay time

min.

CCD

CLK

Write latency

fixed

CLK

DQM Write Mask latency

fixed

DQW

CLK

DQM Data Disable latency

fixed

DQZ

CLK

Clock Suspend latency

fixed

CSL

CLK

HYB 39S16400/800/160AT-8/-10

16 MBit Synchronous DRAM

Semiconductor Group

1998-10-01

Package Outlines

GPX05941

18.41

±0.13

0.8

0.35

+0.1
-0.05

0.1

10.16

±0.13

±0.2

11.76

±0.1

0.5

44x

±0.05

0.15

-0.03

+0.06

15°

±5°

15°

±5°

6 max

2.5 max

Index Marking

Does not include dambar protrusion of 0.13 max per side

Does not include plastic protrusion of 0.25 max per side

Does not include plastic or metal protrusion of 0.15 max per side

16.8

0.8

21x

0.2

44x

Plastic Package P-TSOPII-44
(400 mil, 0.8 mm lead pitch)
Thin Small Outline Package, SMD

Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book "Package Information".

Dimensions in mm

SMD = Surface Mounted Device

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: Q67100-Q1323

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: Q67100-Q1323