Semiconductor Group
1
1M
32-Bit Dynamic RAM Module
(Hyper Page Mode - EDO Version)
HYM 321005S/GS-50/-60
Advanced Information
SIMM modules with 1 048 576 words by 32-bit organization
for PC main memory applications
Fast access and cycle time
50 ns access time
84 ns cycle time (-50 version)
60 ns access time
104 ns cycle time (-60 version)
Hyper page mode- EDO capability with
20 ns cycle time (-50 version)
25 ns cycle time (-60 version)
Single + 5 V (
10 %) supply
Low power dissipation
max 2200 mW active (-50 version)
max. 1980 mW active (-60 version)
CMOS 11
mW
standby
TTL
22 mW standby
CAS-before-RAS refresh, RAS-only-refresh, Hidden refresh
2 decoupling capacitors mounted on substrate
All inputs, outputs and clock fully TTL compatible
72 pin Single in-Line Memory Module
Utilizes two 1M
16 -DRAMs in SOJ-42 packages
1024 refresh cycles / 16 ms
Optimized for use in byte-write non-parity applications
Tin-Lead contact pad HYM 321005S
Gold-Lead contact pad HYM 321005GS
single sided module with 20.32 mm (800 mil) height
1
9.96
Semiconductor Group
2
HYM 321005S/GS-50/-60
1M
32-Bit EDO-Module
The HYM 321005S/GS-50/-60 is a 4 MByte EDO- DRAM module organized as 1 048 576 words by
32-bit in a 72-pin single-in-line package comprising two HYB 5118165BSJ 1M
16 EDO-DRAMs
in 400 mil wide SOJ-packages mounted together with two 0.2
F ceramic decoupling capacitors on
a PC board.
Each HYB 5118165BSJ is described in the data sheet and is fully electrically tested and processed
according to Siemens standard quality procedure prior to module assembly. After assembly onto
the board, a further set of electrical tests is performed.
The speed of the module can be detected by the use of presence detect pins.
The common I/O feature on the HYM 321005S/GS-50/-60 dictates the use of early write cycles.
Ordering Information
Type
Ordering Code
Package
Descriptions
HYM 321005S-50
Q67100-Q2062
L-SIM-72-10
EDO - DRAM module
(access time50 ns)
HYM 321005S-60
Q67100-Q2063
L-SIM-72-10
EDO - DRAM module
(access time 60 ns)
HYM 321005GS-50
Q67100-Q2064
L-SIM-72-10
EDO - DRAM module
(access time 50 ns)
HYM 321005GS-60
Q67100-Q2065
L-SIM-72-10
EDO - DRAM module
(access time 60 ns)
Semiconductor Group
3
HYM 321005S/GS-50/-60
1M
32-Bit EDO-Module
Pin Configuration
Pin Names
Presence Detect Pins
A0-A9
Address Inputs
DQ0-DQ31
Data Input/Output
CAS0 - CAS3
Column Address Strobe
RAS0, RAS2
Row Address Strobe
WE
Read/Write Input
V
CC
Power (+ 5 V)
V
SS
Ground
PD
Presence Detect Pin
N.C.
No Connection
-50
-60
PD0
V
SS
V
SS
PD1
V
SS
V
SS
PD2
V
SS
N.C.
PD3
V
SS
N.C.
VSS
1 DQ0
2
DQ16
3 DQ1
4
DQ17
5 DQ2
6
DQ18
7 DQ3
8
DQ19
9 VCC
10
N.C.
11 A0
12
A1
13 A2
14
A3
15 A4
16
A5
17 A6
18
N.C.
19 DQ4 20
DQ20
21 DQ5 22
DQ21
23 DQ6 24
DQ22
25 DQ7 26
DQ23
27 A7
28
N.C.
29 VCC 30
A8
31 A9
32
N.C.
33 RAS2 34
N.C.
35 N.C. 36
N.C.
37 N.C. 38
VSS
39 CAS0 40
CAS2
41 CAS3 42
CAS1
43 RAS0 44
N.C.
45 N.C. 46
WE
47 N.C. 48
DQ8
49 DQ24 50
DQ9
51 DQ25 52
DQ10
53 DQ26 54
DQ11
55 DQ27 56
DQ12
57 DQ28 58
VCC
59 DQ29 60
DQ13
61 DQ30 62
DQ14
63 DQ31 64
DQ15
65 N.C. 66
PD0
67 PD1 68
PD2
69 PD3 70
N.C.
71 VSS 72
Semiconductor Group
4
HYM 321005S/GS-50/-60
1M
32-Bit EDO-Module
Block Diagram
UCAS LCAS RAS
I/O1-I/O8
I/O9-I/O16
OE
RAS0
CAS0
CAS1
DQ8-DQ15
D1
UCAS LCAS RAS
I/O1-I/O8
I/O9-I/O16
OE
D2
RAS2
CAS2
CAS3
A0 - A9
WE
VCC
VSS
D1 , D2
D1 , D2
C1 , C2
DQ0-DQ7
DQ16-DQ23
DQ24-DQ31
Semiconductor Group
5
HYM 321005S/GS-50/-60
1M
32-Bit EDO-Module
Absolute Maximum Ratings
Operating temperature range .........................................................................................
0 to + 70 C
Storage temperature range......................................................................................
55 to + 125 C
Input/output voltage ........................................................................... 0.5 to min (Vcc + 0.5, 7.0) V
Power supply voltage......................................................................................................
1 to + 7 V
Power dissipation...................................................................................................................
2.52 W
Data out current (short circuit) ................................................................................................
50 mA
Note:
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
DC Characteristics
T
A
= 0 to 70 C,
V
SS
= 0 V,
V
CC
= 5 V
10 %;
t
T
= 2 ns
Parameter
Symbol
Limit Values
Unit Test
Condition
min.
max.
Input high voltage
V
IH
2.4
Vcc+0.5
V
1)
Input low voltage
V
IL
0.5
0.8
V
1)
Output high voltage (
I
OUT
= 5 mA)
V
OH
2.4
V
1)
Output low voltage (
I
OUT
= 4.2 mA)
V
OL
0.4
V
1)
Input leakage current
(0 V
V
IH
Vcc + 0.3V, all other pins = 0 V)
I
I(L)
10
10
A
1)
Output leakage current
(DO is disabled, 0 V
V
OUT
Vcc + 0.3V)
I
O(L)
10
10
A
1)
Average
V
CC
supply current:
-50 ns version
-60 ns version
(RAS, CAS, address cycling:
t
RC
=
t
RC
min.)
I
CC1
400
360
mA
mA
2) 3) 4)
2) 3) 4)
Standby
V
CC
supply current
(RAS = CAS =
V
IH
)
I
CC2
4
mA
Average
V
CC
supply current, during RAS-only
refresh cycles:
-50 ns version
-60 ns version
(RAS cycling, CAS =
V
I,H,
t
RC
=
t
RC
min.)
I
CC3
400
360
mA
mA
2) 4)
2) 4)
Average
V
CC
supply current,during hyper page
mode (EDO):
-50 ns version
-60 ns version
(RAS =
V
IL
, CAS, address cycling:
(
t
HPC
=
t
HPC
min.)
I
CC4
180
150
mA
mA
2) 3) 4)
2) 3) 4)
Semiconductor Group
6
HYM 321005S/GS-50/-60
1M
32-Bit EDO-Module
Capacitance
T
A
= 0 to 70 C;
V
CC
= 5 V
10 %;
f
= 1 MHz
Standby
V
CC
supply current
(RAS = CAS =
V
CC
0.2 V)
I
CC5
2
mA
1)
Average
V
CC
supply current, during CAS-
before-RAS refresh mode: -50 ns version
-60 ns version
(RAS, CAS cycling:
t
RC
=
t
RC
min.)
I
CC6
400
360
mA
mA
2) 4)
2) 4)
Parameter
Symbol
Limit Values
Unit
min.
max.
Input capacitance (A0 to A9)
C
I1
25
pF
Input capacitance (RAS0, RAS2)
C
I2
20
pF
Input capacitance (CAS0-CAS3)
C
I3
20
pF
Input capacitance (WE)
C
I4
25
pF
I/O capacitance (DQ0-DQ31)
C
IO1
15
pF
DC Characteristics (cont'd)
T
A
= 0 to 70 C,
V
SS
= 0 V,
V
CC
= 5 V
10 %;
t
T
= 2 ns
Parameter
Symbol
Limit Values
Unit Test
Condition
min.
max.
Semiconductor Group
7
HYM 321005S/GS-50/-60
1M
32-Bit EDO-Module
AC Characteristics
5)6)
T
A
= 0 to 70 C,
V
CC
= 5 V
10 %,
t
T
= 2 ns
Parameter
Symbol
Limit Values
Unit
Note
-50
-60
min.
max.
min.
max.
common parameters
Random read or write cycle time
t
RC
84
104
ns
RAS precharge time
t
RP
30
40
ns
RAS pulse width
t
RAS
50
10k
60
10k
ns
CAS pulse width
t
CAS
8
10k
10
10k
ns
Row address setup time
t
ASR
0
0
ns
Row address hold time
t
RAH
8
10
ns
Column address setup time
t
ASC
0
0
ns
Column address hold time
t
CAH
8
10
ns
RAS to CAS delay time
t
RCD
12
37
14
45
ns
RAS to column address delay time
t
RAD
10
25
12
30
ns
RAS hold time
t
RSH
13
15
ns
CAS hold time
t
CSH
40
50
ns
CAS to RAS precharge time
t
CRP
5
5
ns
Transition time (rise and fall)
t
T
1
50
1
50
ns
7
Refresh period
t
REF
16
16
ms
Read Cycle
Access time from RAS
t
RAC
50
60
ns
8, 9
Access time from CAS
t
CAC
13
15
ns
8, 9
Access time from column address
t
AA
25
30
ns
8,10
Column address to RAS lead time
t
RAL
25
30
ns
Read command setup time
t
RCS
0
0
ns
Read command hold time
t
RCH
0
0
ns
11
Read command hold time referenced to
RAS
t
RRH
0
0
ns
11
CAS to output in low-Z
t
CLZ
0
0
ns
8
Output buffer turn-off delay
t
OFF
0
13
0
15
ns
12
Semiconductor Group
8
HYM 321005S/GS-50/-60
1M
32-Bit EDO-Module
Early Write Cycle
Write command hold time
t
WCH
8
10
ns
Write command pulse width
t
WP
8
10
ns
Write command setup time
t
WCS
0
0
ns
13
Write command to RAS lead time
t
RWL
13
15
ns
Write command to CAS lead time
t
CWL
13
15
ns
Data setup time
t
DS
0
0
ns
14
Data hold time
t
DH
8
10
ns
14
Hyper Page Mode (EDO) Cycle
Hyper page mode (EDO) cycle time
t
HPC
20
25
ns
CAS precharge time
t
CP
8
10
ns
Access time from CAS precharge
t
CPA
27
32
ns
7
Output data hold time
t
COH
5
5
ns
RAS pulse width in hyper page mode
t
RAS
50
200k
60
200k ns
CAS precharge to RAS Delay
t
RHCP
27
32
ns
CAS before RAS Refresh Cycle
CAS setup time
t
CSR
10
10
ns
CAS hold time
t
CHR
10
10
ns
RAS to CAS precharge time
t
RPC
5
5
ns
Write to RAS precharge time
t
WRP
10
10
ns
Write hold time referenced to RAS
t
WRH
10
10
ns
AC Characteristics (cont'd)
5)6)
T
A
= 0 to 70 C,
V
CC
= 5 V
10 %,
t
T
= 2 ns
Parameter
Symbol
Limit Values
Unit
Note
-50
-60
min.
max.
min.
max.
Semiconductor Group
9
HYM 321005S/GS-50/-60
1M
32-Bit EDO-Module
Notes:
1) All voltages are referenced to
V
SS
.
Vil may undershoot to -2.0 V for pulse width of less than or equal to 4 ns. Pulse width is measured at 50%
points with amplitude measured peak to the DC reference.
2)
I
CC1
,
I
CC3
,
I
CC4
and
I
CC6
depend on cycle rate.
3)
I
CC1
and
I
CC4
depend on output loading. Specified values are obtained with the output open.
4) Address can be changed once or less while RAS = Vil. In case of ICC4 it can be changed once or less during
a hyper page mode (EDO) cycle.
5) An initial pause of 200
s is required after power-up followed by 8 RAS cycles of which at least one cycle has
to be a refresh cycle, before proper device operation is achieved. In case of using the internal refresh counter,
a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.
6) AC measurements assume
t
T
= 2 ns.
7)
V
I
H
(min.)
and
V
I
L (max.)
are reference levels for measuring timing of input signals. Transition times are also
measured between
V
I
H
and
V
I
L
.
8) Measured with the specified current load and 100 pF at Vol = 0.8 V and Voh = 2.0 V. Access time is determined
by the latter of t
RAC
, t
CAC
, t
AA
,t
CPA
. t
CAC
is measured from tristate.
.
9) Operation within the
t
RCD (max.)
limit ensures that
t
RAC (max.)
can be met.
t
RCD (max.)
is specified as a reference point
only. If
t
RCD
is greater than the specified
t
RCD (max.)
limit, then access time is controlled by
t
CAC
.
10) Operation within the
t
RAD (max.
)
limit ensures that
t
RAC (max.)
can be met.
t
RAD (max.)
is specified as a reference point
only. If
t
RAD
is greater than the specified
t
RAD (max.)
limit, then access time is controlled by
t
AA
.
11) Either
t
RCH
or
t
RRH
must be satisfied for a read cycle.
12)
t
OFF (max.)
define the time at which the output achieves the open-circuit conditions and are not referenced to
output voltage levels.
t
OFF
is referenced from the rising edge of RAS or CAS, whichever occurs last.
13)
t
WCS
is not a restrictive operating parameter. This is included in the data sheet as electrical characteristics only.
If
t
WCS
>
t
WCS (min.)
, the cycle is an early write cycle and data out pin will remain open-circuit (high impedance)
through the entire cycle.
14) These parameters are referenced to the CAS leading edge.
Semiconductor Group
10
HYM 321005S/GS-50/-60
1M
32-Bit EDO-Module
L-SIM-72-10
Module package
(single in-line memory module)
GLS05833
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