Semiconductor Group
1
8M
32-Bit EDO-DRAM Module
HYM328025S/GS-50/-60
SIMM modules with 8 388 608 words by 32-bit organization
for PC main memory applications
Fast access and cycle time
50 ns access time
84 ns cycle time (-50 version)
60 ns access time
104 ns cycle time (-60 version)
Hyper page mode (EDO) capability
20 ns cycle time (-50 version)
25 ns cycle time (-60 version)
Single + 5 V (
10 %) supply
Low power dissipation
max. 5280 mW active (-50 version)
max. 4840 mW active (-60 version)
CMOS 88 mW standby
TTL
176 mW standby
CAS-before-RAS refresh
RAS-only-refresh
Hidden-refresh
16 decoupling capacitors mounted on substrate
All inputs, outputs and clocks fully TTL compatible
72 pin Single in-Line Memory Module (L-SIM-72-15) with 25.40 mm height
Utilizes sixteen 4Mx4-DRAMs in SOJ packages
2048 refresh cycles / 32 ms
Optimized for use in byte-write non-parity applications
Tin-Lead contact pads (S- version)
Gold contact pads (GS -version)
9.96
Semiconductor Group
2
HYM328025S/GS-50/-60
8M
32-Bit EDO-Module
The HYM 328025S/GS-50/-60 is a 32 MByte DRAM module organized as 8 388 608 words by
32-bit in a 72-pin single-in-line package comprising sixteen HYB 5117405BJ 4M
4 DRAMs in 300
mil wide SOJ-packages mounted together with sixteen 0.2
F ceramic decoupling capacitors on a
PC board.
Each HYB 5117405BJ is described in the data sheet and is fully electrical tested and processed
according to SIEMENS standard quality procedure prior to module assembly. After assembly onto
the board, a further set of electrical tests is performed.
The speed of the module can be detected by the use of four presence detect pins.
The common I/O feature on the HYM 328025S/GS-60 dictates the use of early write cycles.
Ordering Information
Type
Ordering Code
Package
Description
HYM 328025S-50
on request
L-SIM-72-15
EDO-DRAM Module
(access time 50 ns)
HYM 328025S-60
Q67100-Q2330
L-SIM-72-15
EDO-DRAM Module
(access time 60 ns)
HYM 328025GS-50
Q67100-Q2098
L-SIM-72-15
EDO-DRAM Module
(access time 50 ns)
HYM 328025GS-60
Q67100-Q2099
L-SIM-72-15
EDO-DRAM Module
(access time 60 ns)
Semiconductor Group
3
HYM328025S/GS-50/-60
8M
32-Bit EDO-Module
Pin Configuration
VSS 1 DQ0 2
DQ16 3 DQ1 4
DQ17 5 DQ2 6
DQ18 7 DQ3 8
DQ19 9 VCC 10
N.C. 11 A0 12
A1 13 A2 14
A3 15 A4 16
A5 17 A6 18
A10 19 DQ4 20
DQ20 21 DQ5 22
DQ21 23 DQ6 24
DQ22 25 DQ7 26
DQ23 27 A7 28
N.C 29 VCC 30
A8 31 A9 32
RAS3 33 RAS2 34
N.C. 35 N.C. 36
N.C. 37 N.C. 38
VSS 39 CAS0 40
CAS2 41 CAS3 42
CAS1 43 RAS0 44
RAS1 45 N.C. 46
WE 47 N.C. 48
DQ8 49 DQ24 50
DQ9 51 DQ25 52
DQ10 53 DQ26 54
DQ11 55 DQ27 56
DQ12 57 DQ28 58
VCC 59 DQ29 60
DQ13 61 DQ30 62
DQ14 63 DQ31 64
DQ15 65 N.C. 66
PD0 67 PD1 68
PD2 69 PD3 70
N.C. 71 VSS 72
Pin Names
Presence Detect Pins
A0-A10
Address Inputs
DQ0-DQ31
Data Input/Output
CAS0 - CAS3
Column Address Strobe
RAS0- RAS3
Row Address Strobe
WE
Read/Write Input
V
CC
Power (+ 5 V)
V
SS
Ground
PD
Presence Detect Pin
N.C.
No Connection
-50
-60
PD0
N.C.
N.C.
PD1
V
SS
V
SS
PD2
V
SS
N.C.
PD3
V
SS
N.C.
Semiconductor Group
4
HYM328025S/GS-50/-60
8M
32-Bit EDO-Module
Block Diagram
CAS RAS
I/O1-I/O4
OE
CAS RAS
I/O1-I/O4
OE
CAS RAS
I/O1-I/O4
OE
CAS RAS
I/O1-I/O4
OE
CAS RAS
I/O1-I/O4
OE
CAS RAS
I/O1-I/O4
OE
CAS RAS
I/O1-I/O4
OE
CAS RAS
I/O1-I/O4
OE
CAS RAS
I/O1-I/O4
OE
CAS RAS
I/O1-I/O4
OE
CAS RAS
I/O1-I/O4
OE
CAS RAS
I/O1-I/O4
OE
CAS RAS
I/O1-I/O4
OE
CAS RAS
I/O1-I/O4
OE
CAS RAS
I/O1-I/O4
OE
CAS RAS
I/O1-I/O4
OE
RAS0
CAS0
DQ0-DQ3
DQ4-DQ7
CAS1
DQ8-DQ11
DQ12-DQ15
RAS2
CAS2
DQ16-DQ19
DQ20-DQ23
CAS3
DQ24-DQ27
DQ28-DQ31
RAS1
RAS3
D0
D3
D4
D7
D8
D11
D12
D15
D1
D2
D5
D6
D9
D10
D13
D14
A0 - A10
WE
VCC
VSS
D0 - D15
D0 - D15
C0 - C15
Semiconductor Group
5
HYM328025S/GS-50/-60
8M
32-Bit EDO-Module
Absolute Maximum Ratings
Operation temperature range .........................................................................................
0 to + 70 C
Storage temperature range.........................................................................................
55 to 125 C
Input/output voltage ............................................................................ 0.5V to min (Vcc+0.5, 7.0) V
Power supply voltage......................................................................................................
1 to + 7 V
Power dissipation...................................................................................................................
6.72 W
Data out current (short circuit) ................................................................................................
50 mA
Note:
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage of the device. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
DC Characteristics
T
A
= 0 to 70 C,
V
CC
= 5 V
10 %
Parameter
Symbol
Limit Values
Unit
Test
Condition
min.
max.
Input high voltage
V
IH
2.4
Vcc+0.5
V
1)
Input low voltage
V
IL
0.5
0.8
V
1)
Output high voltage (
I
OUT
= 5 mA)
V
OH
2.4
V
1)
Output low voltage (
I
OUT
= 4.2 mA)
V
OL
0.4
V
1)
Input leakage current
(0 V <
V
IN
< 6.5 V, all other pins = 0 V)
I
I(L)
20
20
A
1)
Output leakage current
(DO is disabled, 0 V <
V
OUT
< 5.5 V)
I
O(L)
10
10
A
1)
Average
V
CC
supply current
(RAS, CAS, address cycling,
t
RC
=
t
RC
min)
-50 version
-60 version
I
CC1
960
880
mA
mA
2) 3) 4)
Standby
V
CC
supply current
(RAS = CAS =
V
IH
)
I
CC2
32
mA
Average
V
CC
supply current
during RAS only refresh cycles
(RAS cycling, CAS =
V
IH
,
t
RC
=
t
RC
min)
-50 version
-60 version
I
CC3
960
880
mA
mA
2) 4)
Semiconductor Group
6
HYM328025S/GS-50/-60
8M
32-Bit EDO-Module
DC Characteristics
1)
(cont'd)
Capacitance
T
A
= 0 to 70 C,
V
CC
= 5 V
10 %,
f
= 1 MHz
Parameter
Symbol
Limit Values
Unit
Test
Condition
min.
max.
Average
V
CC
supply current
during hyper page mode (EDO)
(RAS =
V
IL
, CAS, address cycling,
t
PC
=
t
PC
min)
-50 version
-60 version
I
CC4
560
440
mA
mA
2) 3) 4)
Standby
V
CC
supply current
(RAS = CAS =
V
CC
0.2 V)
I
CC5
16
mA
1)
Average
V
CC
supply current
during CAS-before-RAS refresh mode
(RAS, CAS cycling,
t
RC
=
t
RC
min)
-50 version
-60 version
I
CC6
960
880
mA
mA
2) 4)
Parameter
Symbol
Limit Values
Unit
min.
max.
Input capacitance (A0 to A10,WE)
C
I1
120
pF
Input capacitance (RAS0 - RAS3)
C
I2
45
pF
Input capacitance (CAS0 - CAS3)
C
I3
40
pF
I/O capacitance
(DQ0-DQ31)
C
IO
25
pF
Semiconductor Group
7
HYM328025S/GS-50/-60
8M
32-Bit EDO-Module
AC Characteristics
5)6)
T
A
= 0 to 70 C,
V
CC
= 5 V
10 %,
t
T
= 2 ns
Parameter
Symbol
Limit Values
Unit
Note
-50
-60
min.
max.
min.
max.
common parameters
Random read or write cycle time
t
RC
84
104
ns
RAS precharge time
t
RP
30
40
ns
RAS pulse width
t
RAS
50
10k
60
10k
ns
CAS pulse width
t
CAS
8
10k
10
10k
ns
Row address setup time
t
ASR
0
0
ns
Row address hold time
t
RAH
8
10
ns
Column address setup time
t
ASC
0
0
ns
Column address hold time
t
CAH
8
10
ns
RAS to CAS delay time
t
RCD
12
37
14
45
ns
RAS to column address delay time
t
RAD
10
25
12
30
ns
RAS hold time
t
RSH
13
15
ns
CAS hold time
t
CSH
40
50
ns
CAS to RAS precharge time
t
CRP
5
5
ns
Transition time (rise and fall)
t
T
1
50
1
50
ns
7
Refresh period
t
REF
32
32
ms
Read Cycle
Access time from RAS
t
RAC
50
60
ns
8, 9
Access time from CAS
t
CAC
13
15
ns
8, 9
Access time from column address
t
AA
25
30
ns
8,10
Column address to RAS lead time
t
RAL
25
30
ns
Read command setup time
t
RCS
0
0
ns
Read command hold time
t
RCH
0
0
ns
11
Read command hold time referenced to
RAS
t
RRH
0
0
ns
11
CAS to output in low-Z
t
CLZ
0
0
ns
8
Output buffer turn-off delay
t
OFF
0
13
0
15
ns
12
Semiconductor Group
8
HYM328025S/GS-50/-60
8M
32-Bit EDO-Module
Early Write Cycle
Write command hold time
t
WCH
8
10
ns
Write command pulse width
t
WP
8
10
ns
Write command setup time
t
WCS
0
0
ns
13
Write command to RAS lead time
t
RWL
13
15
ns
Write command to CAS lead time
t
CWL
13
15
ns
Data setup time
t
DS
0
0
ns
14
Data hold time
t
DH
8
10
ns
14
Hyper Page Mode (EDO) Cycle
Hyper page mode (EDO) cycle time
t
HPC
20
25
ns
CAS precharge time
t
CP
8
10
ns
Access time from CAS precharge
t
CPA
27
32
ns
7
Output data hold time
t
COH
5
5
ns
RAS pulse width in hyper page mode
t
RAS
50
200k
60
200k ns
CAS precharge to RAS Delay
t
RHCP
27
32
ns
CAS before RAS Refresh Cycle
CAS setup time
t
CSR
10
10
ns
CAS hold time
t
CHR
10
10
ns
RAS to CAS precharge time
t
RPC
5
5
ns
Write to RAS precharge time
t
WRP
10
10
ns
Write hold time referenced to RAS
t
WRH
10
10
ns
AC Characteristics (cont'd)
5)6)
T
A
= 0 to 70 C,
V
CC
= 5 V
10 %,
t
T
= 2 ns
Parameter
Symbol
Limit Values
Unit
Note
-50
-60
min.
max.
min.
max.
Semiconductor Group
9
HYM328025S/GS-50/-60
8M
32-Bit EDO-Module
Notes:
1) All voltages are referenced to
V
SS
.
Vil may undershoot to -2.0 V for pulse width of less than or equal to 4 ns. Pulse width is measured at 50%
points with amplitude measured peak to the DC reference.
2)
I
CC1
,
I
CC3
,
I
CC4
and
I
CC6
depend on cycle rate.
3)
I
CC1
and
I
CC4
depend on output loading. Specified values are obtained with the output open.
4) Address can be changed once or less while RAS = Vil. In case of ICC4 it can be changed once or less during
a hyper page mode (EDO) cycle.
5) An initial pause of 200
s is required after power-up followed by 8 RAS cycles of which at least one cycle has
to be a refresh cycle, before proper device operation is achieved. In case of using the internal refresh counter,
a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.
6) AC measurements assume
t
T
= 2 ns.
7)
V
I
H
(min.)
and
V
I
L (max.)
are reference levels for measuring timing of input signals. Transition times are also
measured between
V
I
H
and
V
I
L
.
8) Measured with the specified current load and 100 pF at Vol = 0.8 V and Voh = 2.0 V. Access time is determined
by the latter of t
RAC
, t
CAC
, t
AA
,t
CPA
. t
CAC
is measured from tristate.
.
9) Operation within the
t
RCD (max.)
limit ensures that
t
RAC (max.)
can be met.
t
RCD (max.)
is specified as a reference point
only. If
t
RCD
is greater than the specified
t
RCD (max.)
limit, then access time is controlled by
t
CAC
.
10) Operation within the
t
RAD (max.
)
limit ensures that
t
RAC (max.)
can be met.
t
RAD (max.)
is specified as a reference point
only. If
t
RAD
is greater than the specified
t
RAD (max.)
limit, then access time is controlled by
t
AA
.
11) Either
t
RCH
or
t
RRH
must be satisfied for a read cycle.
12)
t
OFF (max.)
define the time at which the output achieves the open-circuit conditions and are not referenced to
output voltage levels.
t
OFF
is referenced from the rising edge of RAS or CAS, whichever occurs last.
13)
t
WCS
is not a restrictive operating parameter. This is included in the data sheet as electrical characteristics only.
If
t
WCS
>
t
WCS (min.)
, the cycle is an early write cycle and data out pin will remain open-circuit (high impedance)
through the entire cycle.
14) These parameters are referenced to the CAS leading edge.
Semiconductor Group
10
HYM328025S/GS-50/-60
8M
32-Bit EDO-Module
Semiconductor Group
11
HYM328025S/GS-50/-60
8M
32-Bit EDO-Module
Package Outline
Module Package, L-SIM-72-15
(Single in-Line Memory Module)
107.95
101.19
3.18
6.35
R 1.57
1.27
10.16
2.03
6.35
3.38
6.35
R1.57
Detail of Contacts
1.27
1.04
2.54 min
0.25 max
Tolerances : +/- 0.13 unless otherwise specified
95.25
+/- 0.05
+/- 0.05
+/- 0.05
+/- 0.05
1.27
+0.10
-0.08
25.40
8.89 max
file: LSIM7215.DRW/WMF
Dimensions in mm
GLS05859
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ZIP