Semiconductor Group
55
01.95
262 144 words by 4-bit organization
Fast access and cycle time
50 ns access time
95 ns cycle time (-50 version)
60 ns access time
110 ns cycle time (-60 version)
70 ns access time
130 ns cycle time (-70 version)
Fast page mode cycle time
35 ns (-50 version)
40 ns (-60 version)
45 ns (-70 version)
Low power dissipation
max. 495 mW active (-50 version)
max. 440 mW active (-60 version)
max. 385 mW active (-70 version)
max. 5.5 mW standby
max. 1.1 mW standby for L-version
Ordering Information
Type
Ordering Code
Package
Description
HYB 514256B-50
Q67100-Q1044
P-DIP-20-2
DRAM (access time 50ns)
HYB 514256B-60
Q67100-Q530
P-DIP-20-2
DRAM (access time 60 ns)
HYB 514256B-70
Q67100-Q433
P-DIP-20-2
DRAM (access time 70 ns)
HYB 514256BJ-50
Q67100-Q1054
P-SOJ-26/20-1
DRAM (access time 50 ns)
HYB 514256BJ-60
Q67100-Q536
P-SOJ-26/20-1
DRAM (access time 60 ns)
HYB 514256BJ-70
Q67100-Q537
P-SOJ-26/20-1
DRAM (access time 70 ns)
HYB 514256BL-50
on request
P-DIP-20-2
DRAM (access time 50 ns)
HYB 514256BL-60
Q67100-Q542
P-DIP-20-2
DRAM (access time 60 ns)
HYB 514256BL-70
Q67100-Q543
P-DIP-20-2
DRAM (access time 70 ns)
HYB 514256BJL-50
on request
P-SOJ-26/20-1
DRAM (access time 50 ns)
HYB 514256BJL-60
Q67100-Q608
P-SOJ-26/20-1
DRAM (access time 60 ns)
HYB 514256BJL-70
Q67100-Q607
P-SOJ-26/20-1
DRAM (access time 70 ns)
256 K
4-Bit Dynamic RAM
Low Power 256 K
4-Bit Dynamic RAM
Advanced Information
Single + 5 V (
10 %) supply with a built-in
V
BB
generator
Output unlatched at cycle end allows two-
dimensional chip selection
Read-modify-write, CAS-before-RAS
refresh, RAS-only refresh, hidden-refresh
and fast page mode capability
All inputs, outputs and clocks
TTL-compatible
512 refresh cycles/8 ms
512 refresh cycles/64 ms
for L-version only
Plastic Packages:
P-DIP-20-2,
P-SOJ-26/20-1
HYB 514256B/BJ-50/-60/-70
HYB 514256BL/BJL-50/-60/-70
Semiconductor Group
56
HYB 514256B/BL/BJ/BJL-50/-60/-70
256 K
4-DRAM
The HYB 514256B/BJ/BL/BJL is the new generation dynamic RAM organized as 262 144 words by
4-bit. The HYB 514256B/BJ/BL/BJL utilizes CMOS silicon gate process technology as well as
advanced circuit techniques to provide wide operating margins, both internally and for the system
user. Multiplexed address inputs permit the HYB 514256B/BJ/BL/BJL to be packaged in a standard
plastic P-DIP-20-2,or plastic P-SOJ-26/20-1. This package size provides high system bit densities
and is compatible with commonly used automatic testing and insertion equipment. System oriented
features include single + 5 V (
10 %) power supply, direct interfacing with high-performance logic
device families such as Schottky TTL. These HYB 514256BL/BJL are specially selected for battery
backup applications.
Pin Definitions and Functions
Pin No.
Function
A0-A8
Address Inputs
RAS
Row Address Strobe
OE
Output Enable
I/O1-I/O4
Data Input/Output
CAS
Column Address Strobe
WE
Read/Write Input
V
CC
Power Supply (+ 5 V)
V
SS
Ground (0 V)
N.C.
No Connection
Semiconductor Group
57
HYB 514256B/BL/BJ/BJL-50/-60/-70
256 K
4-DRAM
Pin Configuration
(top view)
P-SOJ-26/20-1
P-DIP-20-2
Semiconductor Group
58
HYB 514256B/BL/BJ/BJL-50/-60/-70
256 K
4-DRAM
Block Diagram
Semiconductor Group
59
HYB 514256B/BL/BJ/BJL-50/-60/-70
256 K
4-DRAM
Absolute Maximum Ratings
Operating temperature range .........................................................................................0 to + 70 C
Storage temperature range...................................................................................... 55 to + 150 C
Soldering temperature ............................................................................................................260 C
Soldering time .............................................................................................................................10 s
Input/output voltage ........................................................................................................ 1 to + 7 V
Power supply voltage...................................................................................................... 1 to + 7 V
Power dissipation..................................................................................................................... 0.6 W
Data out current (short circuit) ................................................................................................ 50 mA
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage of the device. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
DC Characteristics
T
A
= 0 to 70 C;
V
SS
= 0 V;
V
CC
= 5 V
10 %
Parameter
Symbol
Limit Values
Unit Test
Condition
min.
max.
Input high voltage
V
IH
2.4
6.5
V
1)
Input low voltage
V
IL
1.0
0.8
V
1)
Output high voltage (
I
OUT
= 5 mA)
V
OH
2.4
V
1)
Output low voltage (
I
OUT
= 4.2 mA)
V
OL
0.4
V
1)
Input leakage current, any input
(0 V
V
IN
6.5 V, all other pins = 0 V)
I
I(L)
10
10
A
1)
Output leakage current
(DO is disabled, 0 V
V
OUT
V
CC
)
I
O(L)
10
10
A
1)
Average
V
CC
supply current:
-50 version
-60 version
-70 version
(RAS, CAS, address cycling:
t
RC
=
t
RC
min.)
I
CC1
90
80
70
mA
mA
mA
2) 3)
2) 3)
2) 3)
Standby
V
CC
supply current (RAS = CAS =
V
IH
)
I
CC2
2
mA
Average
V
CC
supply current, RAS only mode:
-50 version
-60 version
-70 version
(RAS cycling: CAS =
V
IH
:
t
RC
=
t
RC
min.)
I
CC3
90
80
70
mA
mA
mA
2)
2)
2)
Semiconductor Group
60
HYB 514256B/BL/BJ/BJL-50/-60/-70
256 K
4-DRAM
Average
V
CC
supply current, fast page mode:
-60 version
-70 version
-50 version
(RAS =
V
IL
, CAS, address cycling:
t
PC
=
t
PC
min.)
I
CC4
70
60
50
mA
mA
mA
2) 3
2) 3)
2) 3)
Standby
V
CC
supply current
L-Version
(RAS = CAS =
V
CC
0.2 V)
I
CC5
1
200
mA
A
1)
1)
Average
V
CC
supply current, CAS-before-RAS
refresh mode:
-50 version
-60 version
-70 version
(RAS, CAS cycling:
t
RC
=
t
RC
min.)
I
CC6
90
80
70
mA
mA
mA
2)
2)
2)
For L-version only:
Battery backup current:
average power supply current,
battery backup mode:
(CAS = CAS before RAS cycling or 0.2 V,
OE =
V
CC
0.2 V
WE =
V
CC
0.2 V or 0.2 V,
A0 to A8 =
V
CC
0.2 V or 0.2 V,
I/O1 to I/O4 =
V
CC
0.2 V or 0.2 V or open,
t
RC
= 125
s,
t
RAS
=
t
RAS
min. ~ 1
s)
I
CC7
300
A
2)
DC Characteristics (cont'd)
T
A
= 0 to 70 C;
V
SS
= 0 V;
V
CC
= 5 V
10 %
Parameter
Symbol
Limit Values
Unit Test
Condition
min.
max.
Semiconductor Group
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256 K
4-DRAM
AC Characteristics
4) 13)
T
A
= 0 to 70 C;
V
CC
= 5 V
10 %;
t
T
= 5 ns
Parameter
Symbol
Limit Values
Unit
-50
-60
-70
min.
max.
min.
max.
min.
max.
Random read or write cycle
time
t
RC
95
110
130
ns
Read-modify-write cycle time
t
RWC
140
160
185
ns
Fast page mode cycle time
t
PC
35
40
45
ns
Fast page mode read-modify-
write cycle time
t
PRWC
80
90
100
ns
Access time from RAS
6) 11)
t
RAC
50
60
70
ns
Access time from CAS
6) 11)
t
CAC
15
15
20
ns
Access time from column
address
6) 12)
t
AA
25
30
35
ns
Access time from CAS
precharge
6) 12)
t
CPA
30
35
40
ns
CAS to output in low-Z
4)
t
CLZ
0
0
0
ns
Output buffer
turn-off delay
7)
t
OFF
0
15
0
20
0
20
ns
Transition time
(rise and fall)
5)
t
T
3
50
3
50
3
50
ns
RAS precharge time
t
RP
35
40
50
ns
RAS pulse width
t
RAS
50
10.000
60
10.000
70
10.000
ns
RAS pulse width
(fast page mode)
t
RASP
50
100.000 60
100.000 70
100.000 ns
RAS hold time
t
RSH
15
15
20
ns
CAS hold time
t
CSH
50
60
70
ns
CAS pulse width
t
CAS
15
10.000
15
10.000
20
10.000
ns
RAS hold time from CAS
precharge (Fast Page Mode)
t
RHCP
30
35
45
ns
CAS precharge to WE delay
time (FPM RMW)
t
CPWD
55
60
65
ns
RAS to CAS delay time
11)
t
RCD
20
35
20
45
20
50
RAS to column address delay
time
12)
t
RAD
15
25
15
30
15
35
ns
CAS to RAS precharge time
t
CRP
5
5
5
ns
CAS precharge time
t
CP
10
10
10
ns
Semiconductor Group
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HYB 514256B/BL/BJ/BJL-50/-60/-70
256 K
4-DRAM
Row address setup time
t
ASR
0
0
0
ns
Row address hold time
t
RAH
10
10
10
ns
Column address setup time
t
ASC
0
0
0
ns
Column address hold time
t
CAH
10
15
15
ns
Column address to RAS lead
time
t
RAL
25
30
35
ns
Read command setup time
t
RCS
0
0
0
ns
Read command hold time
8)
t
RCH
0
0
0
ns
Read command hold time
referenced to RAS
8)
t
RRH
0
0
0
ns
Write command hold time
t
WCH
10
10
15
ns
Write command pulse width
t
WP
10
10
15
ns
Write command to RAS lead
time
t
RWL
15
15
20
ns
Write command to CAS lead
time
t
CWL
15
15
20
ns
Data setup time
9)
t
DS
0
0
0
ns
Data hold time
9)
t
DH
10
15
15
ns
Refresh period
t
REF
8
8
8
ms
Refresh period
L-version
t
REF
64
64
ms
Write command setup time
10)
t
WCS
0
0
0
ns
CAS to WE delay time
10)
t
CWD
40
45
50
ns
RAS to WE delay time
10)
t
RWD
75
90
100
ns
Column address to WE delay
time
10)
t
AWD
50
60
65
ns
CAS setup time (CAS-before-
RAS cycle)
t
CSR
5
5
5
ns
CAS hold time (CAS-before-
RAS cycle)
t
CHR
10
15
15
ns
RAS to CAS precharge time
t
RPC
0
0
0
ns
AC Characteristics (cont'd)
4) 13)
T
A
= 0 to 70 C;
V
CC
= 5 V
10 %;
t
T
= 5 ns
Parameter
Symbol
Limit Values
Unit
-50
-60
-70
min.
max.
min.
max.
min.
max.
Semiconductor Group
63
HYB 514256B/BL/BJ/BJL-50/-60/-70
256 K
4-DRAM
CAS precharge time (CAS-
before-RAS counter test
cycle)
t
CPT
25
30
40
ns
OE access time
t
OEA
15
15
20
ns
RAS hold time referenced to
OE
t
ROH
10
10
10
ns
Output buffer turn-off delay
time from OE
t
OEZ
0
15
0
20
0
20
ns
Data to CAS low delay
14)
t
DZC
0
0
0
ns
CAS high to data delay
15)
t
DZO
0
0
0
OE high to data delay
15)
t
CDD
15
20
20
ns
OE to data delay
15)
t
ODD
15
20
20
ns
Capacitance
T
A
= 0 to 70 C;
V
CC
= 5 V
10 %;
f
= 1 MHz
Parameter
Symbol
Limit Values
Unit
min.
max.
Input capacitance (A0 to A8)
C
I1
5
pF
Input capacitance (RAS, CAS, WE, OE)
C
I2
7
pF
Output capacitance (I/O1 ... I/O4)
C
5O
7
pF
AC Characteristics (cont'd)
4) 13)
T
A
= 0 to 70 C;
V
CC
= 5 V
10 %;
t
T
= 5 ns
Parameter
Symbol
Limit Values
Unit
-50
-60
-70
min.
max.
min.
max.
min.
max.
Semiconductor Group
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HYB 514256B/BL/BJ/BJL-50/-60/-70
256 K
4-DRAM
Notes :
1) All voltages are referenced to
V
SS
.
2)
I
CC1
,
I
CC3
,
I
CC4
,
I
CC6
and
I
CC7
depend on cycle rate.
3)
I
CC1
and
I
CC4
depend on output loading. Specified values are measured with the output open.
4) An initial pause of 200
s is required after power-up followed by 8 RAS cycles before proper device operation
is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles
instead of 8 RAS cycles are required.
5)
V
IH
(min.) and
V
IL
(max.) are reference levels for measuring timing of input signals. Transition times are also
measured between
V
IH
and
V
IL
.
6) Measured with a load equivalent to 2 TTL loads and 100 pF.
7)
t
OFF
(max.) and
t
OEZ
(max.) define the time at which the output achieves the open-circuit conditions and is not
referenced to output voltage levels.
8) Either
t
RCH
or
t
RRH
must be satisfied for a read cycle.
9) These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge
in read-modify-write cycles.
10)
t
WCS
,
t
RWD
,
t
CWD
and
t
AWD
are not restrictive operating parameters. They are included in the data sheet as
electrical characteristics only. If
t
WCS
t
WCS
(min.), the cycle is an early write cycle and data out pin will remain
open circuit (high impedance) through the entire cycle; if
t
RWD
t
RWD
(min.),
t
CWD
t
CWD
(min.) and
t
AWD
t
AWD
(min.), the cycle is a read-modify-write cycle and I/O will contain data read from the selected cell. If neither of
the above sets of conditions is satisfied, the condition of I/O (at access time) is indeterminate.
11) Operation within the
t
RCD
(max.) limit insures that
t
RAC
(max.) can be met,
t
RCD
(max.) is specified as a reference
point only. If
t
RCD
is greater than the specified
t
RCD
(max.) limit, then access time is controlled by
t
CAC
.
12) Operation within the
t
RAD
(max.) limit insures that
t
RAC
(max.) can be met.
t
RAD
(max.) is specified as a reference
point only. If
t
RAD
is greater than the specified
t
RAD
(max.) limit, then access time is controlled by
t
AA
.
13) AC measurements assume
t
T
= 5ns.
14) Either
t
DZC
or
t
DZO
must be satisfied.
15) Either
t
CDD
or
t
ODD
must be satisfied.
Semiconductor Group
65
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256 K
4-DRAM
Waveforms
Read Cycle
Row
Address
Column
Address
Row
Address
Valid Data Out
RAS
CAS
A0 - A8
WE
OE
I/O1-I/O4
(Inputs)
I/O1-I/O4
(Outputs)
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
t
RAS
t
RC
t
CSH
t
RAD
t
CAS
t
RP
t
RAH
t
CRP
t
RSH
t
RCD
t
RAL
t
ASR
t
CAH
t
ASC
t
ASR
t
RCH
t
RRH
t
RCS
t
AA
t
OEA
t
CLZ
t
CAC
t
OEZ
t
ODD
t
CDD
t
OFF
t
DZC
t
DZO
t
RAC
Hi Z
Hi Z
"H" or "L"
Semiconductor Group
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HYB 514256B/BL/BJ/BJL-50/-60/-70
256 K
4-DRAM
Write Cycle (Early Write)
t
CWL
t
RWL
t
WP
t
ASC
t
WCH
Valid Data In
t
DS
t
DH
Hi Z
Column
Address
Address
Row
Row
Address
t
RAH
t
WCS
"H" or "L"
RAS
CAS
A0 - A8
WE
OE
I/O1-I/O4
(Inputs)
I/O1-I/O4
(Outputs)
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
.
t
RAS
t
RC
t
CSH
t
RAD
t
CAS
t
RP
t
CRP
t
RSH
t
RCD
t
RAL
t
ASR
t
CAH
t
ASR
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256 K
4-DRAM
Write Cycle (OE Controlled Write)
Valid Data
t
RWL
t
WP
t
OEH
t
ODD
t
CWL
t
DZO
t
OEA
t
CLZ
t
DS
t
OEZ
t
DH
t
RC
V
IH
V
IL
Row
Address
t
DZC
"H" or "L"
Hi-Z
Hi-Z
Column
Address
Address
Row
t
ASC
t
RAD
t
RAL
t
CAH
t
RAH
RAS
CAS
A0 - A8
WE
OE
I/O1-I/O4
(Inputs)
I/O1-I/O4
(Outputs)
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
.
t
RAS
t
CSH
t
CAS
t
RP
t
CRP
t
RSH
t
RCD
t
ASR
t
ASR
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256 K
4-DRAM
Read-Write (Read-Modify-Write) Cycle
Row
Address
Row
Address
t
CSH
t
CAS
t
CRP
t
RWC
t
AWD
t
ASR
t
RP
t
RAS
t
RAH
t
CAH
I/O1-I/O4
(Outputs)
V
OH
V
OL
V
IH
V
IL
V
IH
V
IL
I/O1-I/O4
(Inputs)
OE
WE
V
IH
V
IL
t
ASR
Column
Address
t
RCD
t
DH
t
RSH
t
RAD
t
CWD
t
OEH
t
RWD
t
RWL
t
CWL
t
CLZ
t
WP
t
RCS
t
AA
t
OEA
t
DS
t
DZC
t
DZO
t
ODD
t
CAC
t
OEZ
Valid
Data in
Data
Out
t
RAC
"H" or "L"
t
ASC
V
IH
V
IL
V
IH
V
IL
RAS
CAS
A0 - A8
V
IH
V
IL
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256 K
4-DRAM
Fast Page Mode Read-Modify-Write Cycle
t
CAH
t
CP
t
DZC
t
DZO
t
RAC
t
CAC
t
CLZ
t
RCS
t
AA
t
OEA
t
RCD
t
RAD
t
RAH
t
ASR
t
ASC
t
CAS
t
CAS
t
PRWC
t
CWD
t
CAH
t
ASC
t
CAS
t
RSH
t
RP
t
CRP
t
ASR
t
CAH
t
ASC
t
RAL
t
CWD
t
RWD
t
CWL
t
CWL
t
CWD
t
AWD
t
AWD
t
WP
t
WP
t
CWL
t
RWL
t
AWD
t
WP
t
ODD
t
OEH
t
DH
t
DS
t
CPA
t
OEZ
t
CLZ
t
DZC
t
AA
t
CAC
t
OEA
t
DS
t
OEZ
t
DH
t
OEH
t
AA
t
ODD
t
DZC
t
CPA
t
OEA
t
CLZ
t
DS
t
DH
t
OEH
t
ODD
RAS
V
IH
V
IL
CAS
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V OL
WE
OE
I/O1-I/O4
(Inputs)
I/O1-I/O4
(Outputs)
Data In
Data In
Data In
Data
Out
Out
Data
Data Out
Address
Row
Column
Address
Address
Column
Address
Row
Address
t
RASP
t
CSH
Column
t
CPWD
t
CPWD
"H" or "L"
A0-A8
t
OEZ
Semiconductor Group
70
HYB 514256B/BL/BJ/BJL-50/-60/-70
256 K
4-DRAM
Fast Page Mode Read Cycle
t
RASP
t
CAS
t
CAS
t
PC
t
CP
t
RCD
t
CSH
t
CAH
t
CAH
t
ASC
t
ASC
t
ASR
t
RAH
t
RAD
t
RCS
t
RCS
t
RCS
t
ASC
t
CAH
t
CAS
t
RSH
t
CRP
t
RP
t
ASR
t
RCH
t
CPA
t
OEA
t
OEA
t
AA
t
AA
t
DZC
t
DZC
t
CDD
t
RRH
t
CPA
t
OEA
t
AA
t
DZC
t
DZO
t
ODD
t
ODD
t
DZO
t
ODD
t
DZO
t
OFF
t
OEZ
t
OEZ
t
OFF
t
OEZ
t
CAC
t
CAC
t
CLZ
t
CLZ
t
CLZ
t
OFF
t
RAC
t
CAC
Valid
Data Out
Data Out
Data Out
Valid
Valid
Column
Address
Address
Addr
Address
Column
Row
Row
RAS
I/O1-I/O4
(Outputs)
I/O1-I/O4
(Inputs)
OE
WE
A0-A8
CAS
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
"H" or "L"
t
RHCP
t
RCH
V
OH
V
OL
Column
Address
Semiconductor Group
71
HYB 514256B/BL/BJ/BJL-50/-60/-70
256 K
4-DRAM
Fast Page Mode Early Write Cycle
t
RASP
t
RP
t
RSH
t
CAS
t
CAS
t
CP
t
CRP
t
RAL
t
CAH
t
ASR
t
CWL
t
RWL
t
CAH
t
ASC
t
ASC
t
CWL
t
CWL
t
WCS
t
WCS
t
WCS
t
WCH
t
WP
t
WP
t
WCH
t
WP
t
WCH
t
RAD
t
CAS
t
RCD
t
PC
t
CAH
t
RAH
t
ASR
t
ASC
t
DH
t
DS
t
DS
t
DH
t
DH
t
DS
Column
Address
Address
Address
Column
Row
Row
Addr
Valid
Data In
Valid
Valid
Data In
Data In
Column
Address
HI-Z
RAS
I/O1-I/O4
(Outputs)
I/O1-I/O4
(Inputs)
OE
WE
A0-A8
CAS
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
"H" or "L"
V
OH
V
OL
Semiconductor Group
72
HYB 514256B/BL/BJ/BJL-50/-60/-70
256 K
4-DRAM
RAS-Only Refresh Cycle
t
CRP
t
RAH
t
RP
t
RAS
t
RC
t
ASR
t
ASR
t
RPC
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
Row
Address
Row
Address
HI-Z
A0-A8
RAS
CAS
I/O1-I/O4
(Outputs)
"H" or "L"
Semiconductor Group
73
HYB 514256B/BL/BJ/BJL-50/-60/-70
256 K
4-DRAM
CAS-Before-RAS Refresh Cycle
t
RP
t
RAS
t
RP
t
RC
t
CRP
t
CP
t
RPC
t
CHR
t
WRH
t
WRP
t
CSR
t
RPC
t
OFF
t
OEZ
t
CDD
t
ODD
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
HI-Z
"H" or "L"
RAS
I/O1-I/O4
(Outputs)
I/O1-I/O4
(Inputs)
OE
WE
CAS
V
OH
V
OL
Semiconductor Group
74
HYB 514256B/BL/BJ/BJL-50/-60/-70
256 K
4-DRAM
Hidden Refresh Cycle (Read)
RAS
I/O1-I/O4
(Outputs)
I/O1-I/O4
(Inputs)
OE
WE
A0-A8
CAS
t
RC
t
RC
t
RAS
t
RAS
t
RP
t
RP
t
CRP
t
CHR
t
RAD
t
CAH
t
ASC
t
RAH
t
ASR
t
ASR
t
RCS
t
RRH
t
AA
t
DZC
t
DZO
t
CAC
t
RAC
t
CLZ
t
OEZ
t
OFF
t
ODD
t
CDD
t
RCD
t
RSH
t
OEA
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
t
WRP
t
WRH
"H" or "L"
Valid Data Out
Row
Address
Column
Address
Row
Addr
HI-Z
V
OH
V
OL
Semiconductor Group
75
HYB 514256B/BL/BJ/BJL-50/-60/-70
256 K
4-DRAM
Hidden Refresh Cycle (Early Write)
RAS
I/O1-I/O4
(Outputs)
I/O1-I/O4
(Inputs)
OE
WE
V
IH
V
IL
A0-A8
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
CAS
V
IH
V
IL
V
IH
V
IL
"H" or "L"
t
RC
t
RAS
t
RCD
t
RSH
t
RAD
t
CAH
t
WCS
t
WCH
t
WP
t
ASR
t
RAH
t
DS
t
DH
t
ASR
t
CRP
t
CHR
t
RP
t
RAS
t
RC
t
RP
t
ASC
Address
Row
Addr
Row
Address
Valid Data
HI-Z
Column
V
OH
V
OL
Semiconductor Group
76
HYB 514256B/BL/BJ/BJL-50/-60/-70
256 K
4-DRAM
"H" or "L"
t
CSR
t
ASR
t
ASC
t
CHR
t
CPT
t
WRP
t
RAL
t
CAH
t
RSH
t
RP
t
RAS
t
CAS
t
RCS
t
CDD
t
CAC
t
AA
t
WRH
t
OEA
t
ODD
t
CLZ
t
DZC
t
DZO
t
OEZ
t
OFF
t
RWL
t
CWL
t
WCH
t
WCS
t
WRH
t
WRP
t
DS
t
ODD
t
DH
t
WRH
t
WRP
t
OEZ
t
RWL
t
CWL
t
AWD
t
CWD
t
WP
t
RCS
t
CAC
t
OEA
t
OEH
t
AA
t
CLZ
t
DH
t
DZO
t
DS
t
DZC
t
CAC
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
OH
V
OL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
I/O1-I/O4
(Inputs)
RAS
I/O1-I/O4
(Inputs)
OE
WE
A0-A8
CAS
I/O1-I/O4
(Outputs)
I/O1-I/O4
(Outputs)
I/O1-I/O4
(Inputs)
WE
OE
WE
OE
I/O1-I/O4
(Outputs)
Column
Address
Row
Address
Data In
Valid Data Out
Valid
Data In
HI-Z
HI-Z
HI-Z
Read Cycle
Read-Modify-Write Cycle
Write Cycle
t
RRH
t
RCH
D.Out
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