Semiconductor Group
1
4M x 32-Bit Dynamic RAM Module
HYM 324020S/GS-50/-60
Advanced Information
4 194 304 words by 32-bit organization (alternative 8 388 608 words by 16-bit)
Fast access and cycle time
50 ns access time
90 ns cycle time (-50 version)
60 ns access time
110 ns cycle time (-60 version)
Fast page mode capability
35 ns cycle time (-50 version)
40 ns cycle time (-60 version)
Single + 5 V (
10 %) supply
Low power dissipation
max. 5280 mW active (HYM 324020S/GS-50)
max. 4840 mW active (HYM 324020S/GS-60)
CMOS 44 mW standby
TTL
88 mW standby
CAS-before-RAS refresh
RAS-only-refresh
Hidden-refresh
8 decoupling capacitors mounted on substrate
All inputs, outputs and clocks fully TTL compatible
72 pin Single in-Line Memory Module with 22.86 mm (900 mil) height
Utilizes eight 4Mx4-DRAMs in 300mil wide SOJ packages
2048 refresh cycles / 32 ms
Optimized for use in byte-write non-parity applications
Tin-Lead contact pads (S - version)
Gold contact pads (GS - version)
12.95
Semiconductor Group
2
HYM 324020S/GS-50/-60
4M x 32-Bit
The HYM 324020S/GS-50/-60 is a 16 MByte DRAM module organized as 4 194 304 words by
32-bit in a 72-pin single-in-line package comprising eight HYB 5117400BJ 4M x 4 DRAMs in 300
mil wide SOJ-packages mounted together with eight 0.2
F ceramic decoupling capacitors on a PC
board.
The HYM 324020S/GS-50/-60 can also be used as a 8 388 608 words by 16-bits dynamic RAM
module by means of connecting DQ0 and DQ16, DQ1 and DQ17, DQ2 and DQ18, ..., DQ15 and
DQ31, respectively.
Each HYB 5117400BJ is described in the data sheet and is fully electrical tested and processed
according to SIEMENS standard quality procedure prior to module assembly. After assembly onto
the board, a further set of electrical tests is performed.
The speed of the module can be detected by the use of four presence detect pins.
The common I/O feature on the HYM 324020S/GS-50/-60 dictates the use of early write cycles.
Ordering Information
Type
Ordering Code
Package
Description
HYM 324020S-50
on request
L-SIM-72-12
DRAM Module
(access time 50 ns)
HYM 324020S-60
Q67100-Q979
L-SIM-72-12
DRAM Module
(access time 60 ns)
HYM 324020GS-50
on request
L-SIM-72-12
DRAM Module
(access time 50 ns)
HYM 324020GS-60
Q67100-Q2005
L-SIM-72-12
DRAM Module
(access time 60 ns)
Semiconductor Group
3
HYM 324020S/GS-50/-60
4M x 32-Bit
Pin Configuration
VSS 1 DQ0 2
DQ16 3 DQ1 4
DQ17 5 DQ2 6
DQ18 7 DQ3 8
DQ19 9 VCC 10
N.C. 11 A0 12
A1 13 A2 14
A3 15 A4 16
A5 17 A6 18
A10 19 DQ4 20
DQ20 21 DQ5 22
DQ21 23 DQ6 24
DQ22 25 DQ7 26
DQ23 27 A7 28
N.C. 29 VCC 30
A8 31 A9 32
N.C. 33 RAS2 34
N.C. 35 N.C. 36
N.C. 37 N.C. 38
VSS 39 CAS0 40
CAS2 41 CAS3 42
CAS1 43 RAS0 44
N.C. 45 N.C. 46
WE 47 N.C. 48
DQ8 49 DQ24 50
DQ9 51 DQ25 52
DQ10 53 DQ26 54
DQ11 55 DQ27 56
DQ12 57 DQ28 58
VCC 59 DQ29 60
DQ13 61 DQ30 62
DQ14 63 DQ31 64
DQ15 65 N.C. 66
PD0 67 PD1 68
PD2 69 PD3 70
N.C. 71 VSS 72
Pin Names
Presence Detect Pins
A0-A10
Address Inputs for
HYM 324020S/GS
DQ0-DQ31
Data Input/Output
CAS0 - CAS3
Column Address Strobe
RAS0, RAS2
Row Address Strobe
WE
Read/Write Input
V
CC
Power (+ 5 V)
V
SS
Ground
PD
Presence Detect Pin
N.C.
No Connection
-50
-60
PD0
V
SS
V
SS
PD1
N.C.
N.C.
PD2
V
SS
N.C.
PD3
V
SS
N.C.
Semiconductor Group
4
HYM 324020S/GS-50/-60
4M x 32-Bit
Block Diagram
CAS RAS
I/O1-I/O4
OE
CAS RAS
I/O1-I/O4
OE
CAS RAS
I/O1-I/O4
OE
CAS RAS
I/O1-I/O4
OE
CAS RAS
I/O1-I/O4
OE
CAS RAS
I/O1-I/O4
OE
CAS RAS
I/O1-I/O4
OE
CAS RAS
I/O1-I/O4
OE
RAS0
CAS0
DQ0-DQ3
DQ4-DQ7
CAS1
DQ8-DQ11
DQ12-DQ15
RAS2
CAS2
DQ16-DQ19
DQ20-DQ23
CAS3
DQ24-DQ27
DQ28-DQ31
D0
D1
D2
D3
D4
D5
D6
D7
A0 - A10
WE
VCC
VSS
D0 - D7
D0 - D7
C0 - C7
Semiconductor Group
5
HYM 324020S/GS-50/-60
4M x 32-Bit
Absolute Maximum Ratings
Operation temperature range ......................................................................................... 0 to + 70 C
Storage temperature range......................................................................................... 55 to 125 C
Input/output voltage ............................................................................0.5V to min (Vcc+0.5, 7.0) V
Power supply voltage...................................................................................................... 1 to + 7 V
Power dissipation................................................................................................................... 6.72 W
Data out current (short circuit) ................................................................................................ 50 mA
Note:
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage of the device. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
DC Characteristics
T
A
= 0 to 70 C,
V
SS
= 0 V,
V
CC
= 5 V
10 %;
t
T
= 5 ns
Parameter
Symbol
Limit Values
Unit Test
Condition
min.
max.
Input high voltage
V
IH
2.4
Vcc+0.5
V
1)
Input low voltage
V
IL
0.5
0.8
V
1)
Output high voltage (
I
OUT
= 5 mA)
V
OH
2.4
V
1)
Output low voltage (
I
OUT
= 4.2 mA)
V
OL
0.4
V
1)
Input leakage current
(0 V
V
IH
Vcc + 0.3V, all other pins = 0 V)
I
I(L)
20
20
A
1)
Output leakage current
(DO is disabled, 0 V
V
OUT
Vcc + 0.3V)
I
O(L)
10
10
A
1)
Average
V
CC
supply current:
-50 ns version
-60 ns version
(RAS, CAS, address cycling:
t
RC
=
t
RC
min.)
I
CC1
960
880
mA
mA
2) 3) 4)
2) 3) 4)
Standby
V
CC
supply current
(RAS = CAS =
V
IH
)
I
CC2
16
mA
Average
V
CC
supply current, during RAS-only
refresh cycles:
-50 ns version
-60 ns version
(RAS cycling, CAS =
V
I,H,
t
RC
=
t
RC
min.)
I
CC3
960
880
mA
mA
2) 4)
2) 4)
Average
V
CC
supply current,
during fast page mode:
-50 ns version
-60 ns version
(RAS =
V
IL
, CAS, address cycling:
t
PC
=
t
PC
min.)
I
CC4
320
280
mA
mA
2) 3) 4)
2) 3) 4)
Semiconductor Group
6
HYM 324020S/GS-50/-60
4M x 32-Bit
Capacitance
T
A
= 0 to 70 C,
V
CC
= 5 V
10 %,
f
= 1 MHz
Standby
V
CC
supply current
(RAS = CAS =
V
CC
0.2 V)
I
CC5
8
mA
1)
Average
V
CC
supply current, during CAS-
before-RAS refresh mode: -50 ns version
-60 ns version
(RAS, CAS cycling:
t
RC
=
t
RC
min.)
I
CC6
960
880
mA
mA
2) 4)
2) 4)
Parameter
Symbol
Limit Values
Unit
min.
max.
Input capacitance (A0 to A10,WE)
C
I1
75
pF
Input capacitance (RAS0, RAS2)
C
I2
45
pF
Input capacitance (CAS0 - CAS3)
C
I3
25
pF
I/O capacitance
(DQ0-DQ31)
C
IO
15
pF
DC Characteristics (cont'd)
T
A
= 0 to 70 C,
V
SS
= 0 V,
V
CC
= 5 V
10 %;
t
T
= 5 ns
Parameter
Symbol
Limit Values
Unit Test
Condition
min.
max.
Semiconductor Group
7
HYM 324020S/GS-50/-60
4M x 32-Bit
AC Characteristics
5)6)
T
A
= 0 to 70 C,
V
CC
= 5 V
10 %,
t
T
= 5 ns
Parameter
Symbol
Limit Values
Unit
Note
-50
-60
min.
max.
min.
max.
common parameters
Random read or write cycle time
t
RC
90
110
ns
RAS precharge time
t
RP
30
40
ns
RAS pulse width
t
RAS
50
10k
60
10k
ns
CAS pulse width
t
CAS
13
10k
15
10k
ns
Row address setup time
t
ASR
0
0
ns
Row address hold time
t
RAH
8
10
ns
Column address setup time
t
ASC
0
0
ns
Column address hold time
t
CAH
10
15
ns
RAS to CAS delay time
t
RCD
18
37
20
45
RAS to column address delay time
t
RAD
13
25
15
30
ns
RAS hold time
t
RSH
13
15
ns
CAS hold time
t
CSH
50
60
ns
CAS to RAS precharge time
t
CRP
5
5
ns
Transition time (rise and fall)
t
T
3
50
3
50
ns
7
Refresh period
t
REF
32
32
ms
Read Cycle
Access time from RAS
t
RAC
50
60
ns
8, 9
Access time from CAS
t
CAC
13
15
ns
8, 9
Access time from column address
t
AA
25
30
ns
8,10
Column address to RAS lead time
t
RAL
25
30
ns
Read command setup time
t
RCS
0
0
ns
Read command hold time
t
RCH
0
0
ns
11
Read command hold time referenced to
RAS
t
RRH
0
0
ns
11
CAS to output in low-Z
t
CLZ
0
0
ns
8
Output buffer turn-off delay
t
OFF
0
13
0
15
ns
12
Semiconductor Group
8
HYM 324020S/GS-50/-60
4M x 32-Bit
Early Write Cycle
Write command hold time
t
WCH
8
10
ns
Write command pulse width
t
WP
8
10
ns
Write command setup time
t
WCS
0
0
ns
13
Write command to RAS lead time
t
RWL
13
15
ns
Write command to CAS lead time
t
CWL
13
15
ns
Data setup time
t
DS
0
0
ns
14
Data hold time
t
DH
10
10
ns
14
Fast Page Mode Cycle
Fast page mode cycle time
t
PC
35
40
ns
CAS precharge time
t
CP
10
10
ns
Access time from CAS precharge
t
CPA
30
35
ns
7
RAS pulse width
t
RAS
50
200k
60
200k ns
CAS precharge to RAS Delay
t
RHCP
30
35
ns
CAS-before-RAS Refresh Cycle
CAS setup time
t
CSR
10
10
ns
CAS hold time
t
CHR
10
10
ns
RAS to CAS precharge time
t
RPC
5
5
ns
Write to RAS precharge time
t
WRP
10
10
ns
Write hold time referenced to RAS
t
WRH
10
10
ns
AC Characteristics (cont'd)
5)6)
T
A
= 0 to 70 C,
V
CC
= 5 V
10 %,
t
T
= 5 ns
Parameter
Symbol
Limit Values
Unit
Note
-50
-60
min.
max.
min.
max.
Semiconductor Group
9
HYM 324020S/GS-50/-60
4M x 32-Bit
Notes:
1) All voltages are referenced to VSS.
2) ICC1, ICC3, ICC4 and ICC6 depend on cycle rate.
3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open.
4) Address can be changed once or less while RAS = VIL. In the case of ICC4 it can be changed once or less
during a fast page mode cycle (tPC).
5) An initial pause of 200
s is required after power-up followed by 8 RAS cycles of which at least one cycle has
to be a refresh cycle, before proper device operation is achieved. In case of using internal refresh counter, a
minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.
6) AC measurements assume tT = 5 ns.
7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also
measured between VIH and VIL.
8) Measured with a load equivalent to 2 TTL loads and 100 pF.
9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a
reference point only: If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by
tCAC.
10)Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a
reference point only: If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by
tAA.
11)Either tRCH or tRRH must be satisfied for a read cycle.
12)tOFF (max.) define the time at which the outputs achieve the open-circuit condition and are not referenced to
output voltage levels
.
13)tWCS is not a restrictive operating parameter. This is included in the data sheet as electrical characteristics
only. If tWCS > tWCS (min.), the cycle is an early write cycle and the I/O pin will remain open-circuit (high
impedance) through the entire cycle.
14)These parameters are referenced to the CAS leading edge.
Semiconductor Group
10
HYM 324020S/GS-50/-60
4M x 32-Bit
Package Outline
Module Package, L-SIM-72-12
(Single in-Line Memory Module)
GLS05835
107.95
101.19
3.18
6.35
R 1.57
1.27
10.16
2.03
6.35
3.38
6.35
R1.57
Detail of Contacts
1.27
1.04
2.54 min
0.25 max
Tolerances : +/- 0.13 unless otherwise specified
95.25
+/- 0.05
+/- 0.05
+/- 0.05
+/- 0.05
1.27
+0.10
-0.08
22.86
5.28 max
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