Edition 1998-02-01

This edition was realized using
the software system FrameMaker

Published by Siemens AG, Bereich
Halbleiter, Marketing-Kommunikation,
Balanstraße 73,
81541 München

Siemens AG 1998.

Attention please!

As far as patents or other rights of third
parties are concerned, liability is only
assumed for components, not for
applications, processes and circuits
implemented within components or
assemblies.

The information describes the type of
component and shall not be considered
as assured characteristics.

Terms of delivery and rights to change
design reserved.
For questions on technology, delivery
and prices please contact
the Semiconductor Group Offices in
Germany or the Siemens Companies and
Representatives worldwide
(see address list).

Due to technical requirements compo-
nents may contain dangerous substanc-
es. For information on the types in ques-
tion please contact your nearest
Siemens Office, Semiconductor Group.
Siemens AG is an approved CECC man-
ufacturer.

Packing

Please use the recycling operators
known to you. We can also help you get
in touch with your nearest sales office. By
agreement we will take packing material
back, if it is sorted. You must bear the
costs of transport.

For packing material that is returned to us
unsorted or which we are not obliged to
accept, we shall have to invoice you for
any costs incurred.

Components used in life-support de-
vices or systems must be expressly
authorized for such purpose!

Critical components

of the Semiconduc-

tor Group of Siemens AG, may only be
used in life-support devices or systems

with the express written approval of the
Semiconductor Group of Siemens AG.

1 A critical component is a component

used in a life-support device or system
whose failure can reasonably be
expected to cause the failure of that
life-support device or system, or to
affect its safety or effectiveness of that
device or system.

2 Life support devices or systems are

intended (a) to be implanted in the
human body, or (b) to support and/or
maintain and sustain human life. If
they fail, it is reasonable to assume
that the health of the user may be
endangered.

Data Classification

Maximum Ratings

Maximum ratings are absolute ratings; exceeding only one of these values may cause
irreversible damage to the integrated circuit.

Recommended Operating Conditions

Under this conditions the functions given in the circuit description are fulfilled. Nominal
conditions specify mean values expected over the production spread and are the
proposed values for interface and application. If not stated otherwise, nominal values will
apply at

=25°C and the nominal supply voltage.

Characteristics

The listed characteristics are ensured over the operating range of the integrated circuit.

Edition 1998-02-01

Published by Siemens AG, Semiconductor Group
Copyright

Terms of delivery and right to change design reserved.

SDA 9362
Revision History:

Current Version: 1998-02-01

Previous Version:

1997-04-01

Page
(in previous
Version)

Page
(in current
Version)

Subjects (major changes since last revision)

Nom./max. average current and max. standby current specified

Specification of charge current pump of PLL pin LF is unnecessary

SDA 9362

Table of Contents

Page

Semiconductor Group

1998-02-01

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.2

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.3

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.4

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.5

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

System Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.1

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.2

Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.3

Reset Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.4

Frequency Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.5

I²C-Bus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.5.1

I²C-Bus Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.5.2

I²C-Bus Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.5.3

I²C-Bus Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.5.4

Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.5.5

Explanation of Some Control Items . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.1

Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.2

Characteristics (Assuming Recommended Operating Conditions) . . . . . . . 32

Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5.1

VD- Output Voltage, 4/3-CRT and 16/9-Source . . . . . . . . . . . . . . . . . . . . . . 35

5.2

Function of H,V Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.3

Power On/Off Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

5.4

Standby Mode, RESN Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

P-MQFP-44-2

Semiconductor Group

1998-02-01

DDC-PLUS-Deflection Controller

SDA 9362

MOS

Type

Ordering Code

Package

SDA 9362

Q67101-H5173-A701

P-MQFP-44-2

Overview

1.1

Features

· Deflection - Protection - 16:9 / 4:3

C Bus alignment of all deflection parameters

· All EW-, V- and H-functions (incl.

· PW EHT compensation

· PH EHT compensation

· Compensation of H-phase deviation

(e.g. caused by white bar)

· Upper/lower EW-corner correction separately adjustable

· V-angle correction: Vertical frequent linear modulation of H-phase

· V-bow correction: Vertical frequent parabolic modulation of H-phase

· Three reduced V-scan modes (75 %, 66 %, 50 % V-size) selectable

· H- and V-blanking time adjustable

· Partial overscan adjustable to hide the cut off control measuring lines in the reduced

scan modes

· Stop/start of vertical deflection adjustable to fill out the 16/9 screen with different

letterbox formats without annoying overscan

· Dynamic PH EHT-compensation (white bar)

· Self adaptation of V-frequency/number of lines per field between 192 and 680 for each

possible line frequency

· Protection against EHT run away (X-rays protection)

· Protection against missing V-deflection (CRT-protection)

· Two digital outputs for general purpose, controlled by

C Bus

· Selectable softstart of the H-output stage

· P-MQFP-44-2 package

· 5 V supply voltage

SDA 9362

Semiconductor Group

1998-02-01

1.2

General Description

The SDA 9362 is a highly integrated deflection controller for CTV receivers with doubled
line and standard or doubled field frequencies. It controls among others an horizontal
driver circuit for a flyback line output stage, a DC coupled vertical sawtooth output stage
and an East-West raster correction circuit. All adjustable output parameters are

C Bus

controlled. Inputs are HSYNC, VSYNC and the line locked clock CLL.

1.3

Pin Configuration

Figure 1

UEP10259

TST4

1 2 3 4 5 6 7 8 9 10

32 31 30 29 28 27 26 25 24 23

HDEDEF

CLL

SDA

DD(D)

SS(D)

SCL

VBLE

HSYNC

SCP

E/W

DD(A)

REFP

REFN

SS(A)

IBEAM
SW2

DD(A)

HPROT

TST1

TST0

TEST

SW1

REFH

REFL

SS(A)

DD(D)

SS(D)

TST7

SS(D)

RESN

VPROT

VD+

VD-

VSYNC

SSD

TST5
TST6

DD(D)

SDA 9362

Semiconductor Group

1998-02-01

1.4

Pin Description

Pin No. Symbol

Type

Description

CLL

I/TTL

Clock input

Reference oscillator input, crystal

Reference oscillator output, crystal

SDA

C-Bus data

SCL

C-Bus clock

HSYNC

I/TTL

H-sync input

VBLE

Q/TTL

Vertical blanking output

SCP

Blanking signal with H- and color burst component
(V-component selectable by

C Bus)

DD(D)

Digital supply

SS(D)

Digital ground

VPROT

Watching external V-output stage
(input is the V-sawtooth from feedback resistor)

HPROT

Watching EHT (input is e.g. H-flyback)

DD(A)

Analog supply

SW2

Q/TTL

Output of an

C Bus controlled switch (Register 00

Bit D5)

IBEAM

Input for a beam current dependent signal for
stabilization of width, height and H-phase

SS(A)

Analog ground

REFN

Ground for

REFP

REFH

REFL

REFP

Reference voltage for IBEAM ADC, HPROT / VPROT
thresholds

DD(A)

Analog supply

E/W

Control signal output for East-West raster correction

VD+

Control signal output for DC coupled V-output stage

VD-

Like VD+

SS(A)

Analog ground

REFL

Reference voltages for E/W-DAC, V-DAC

REFH

REFL

Line flyback for H-delay compensation

SDA 9362

Semiconductor Group

1998-02-01

1.4

Pin Description (cont'd)

Pin No. Symbol

Type

Description

SW1

Q/TTL

Output of an

C Bus controlled switch (Register 00

Bit D3)

VSYNC

I/TTL

V-sync input

Control signal output for H driver stage

TEST

I/TTL

Switching normal operation (TEST = L) and test mode
(TEST = H: pin 34 is an additional test pin)

TST0

Test pin, to be grounded

TST1

Test pin, to be grounded

HDEDEF

I/TTL

Defines the default value of HDE

SSD

I/TTL

Disables soft start (H)

TST4

Test pin, to be grounded

TST5

Test pin, don't connect

TST6

Test pin, don't connect

DD(D)

Digital supply

SS(D)

Digital ground

TST7

Test pin, don't connect

SS(D)

Digital ground

PLL loop filter

DD(D)

Digital supply

RESN

I/TTL

Reset input, active low

SDA 9362

Semiconductor Group

1998-02-01

System Description

2.1

Functional Description

The main input signals are HSYNC with doubled horizontal frequency, VSYNC with
vertical frequencies of 50/100 Hz or 60/120 Hz and the line locked clock CLL.

The output signals control the horizontal as well as the vertical deflection stages and the
East-West raster correction circuit.

The H-output signal HD compensates the delays of the line output stage and its phase
can be modulated vertical frequent to remove horizontal distortions of vertical raster lines
(V-Bow, V-Angle). Time reference is the middle of the front and back edge of the line
flyback pulse. A positive HD pulse switches off the line output transistor. Maximal H-shift
is 2.25

Picture tubes with 4:3 or 16:9 aspect ratio can be used by adapting the raster to the
aspect ratio of the source signal.

The V-output sawtooth signals VD- and VD+ controls a DC coupled output stage and can
be disabled. Suitable blanking signals are delivered by the IC.

The East-West output signal E/W is a vertical frequent parabola of 4th order, enabling
an additional corner correction, separately for the upper and lower part.

Two

C Bus controlled digital outputs are available for general purpose.

The picture width and picture height compensation (PW/PH Comp) processes the beam
current dependent input signal IBEAM with effect to the outputs E/W and VD to keep
width and height constant and independent of brightness.

The alignment parameter Horizontal Shift Compensation enables to adjust the influence
of the input signal IBEAM on the horizontal phase.

The selectable start up circuit controls the energy supply of the H-output stage during the
receiver's run up time by smooth decreasing the line output transistors switching
frequency down to the normal operating value (softstart). HD starts with about 55 kHz
and converges within 85 ms to its final value. The high time is kept constant. The normal
operating pulse ratio H/L is 45/55. A watch dog function limits the period of the HD output
signal independent of the clock CLL to max 35.2

The protection circuit watches an EHT reference and the sawtooth of the vertical output
stage. H-output stage is switched off if the EHT succeeds a defined threshold or if the
V-deflection fails (refer to page 36). The function of this circuit is based on the internal
quartz oscillator and therefore independent of the input clock CLL.

HPROT:

Input

< V2

Continues blanking

> V1

HD disabled

< V1

Operating range

SDA 9362

Semiconductor Group

1998-02-01

VPROT:

Vertical sawtooth voltage

< V1 in first half of V-period or

> V2 in second half: HD disabled

The pin SCP delivers the composite blanking signal SCP. It contains burst (

), H-

blanking HBL (

HBL

) and selectable V-blanking (control bit SSC). The phase of the H-

blanking period can be varied by

C Bus. For the timing following settings are possible:

BD = 1 :

= 0

BD = 0, BSE = 0 (default value)

HBL

(H-flyback time)

BD = 0, BSE = 1(alignment range)

HBL

= (4

H-blanking-time + 1) / CLL

DBL

= (H-shift + 4

H-blanking-phase

-2

H-blanking-time + 43) / CLL

SSC = 0

VBL

during V-blanking period

SSC = 1

is always

HBL

Figure 3

BG-pulse width

54 / CLL

Delay to HSYNC

36 / CLL

UED10260

Input Signal
HSYNC

DBL

OHBL

SDA 9362

Semiconductor Group

1998-02-01

2.2

Circuit Description

The system clock for the SDA 9362 has to be generated externally (e.g. in the
SDA 9206) and applied to pin CLL. Its frequency must be always the line frequency
(defined by the horizontal time reference HSYNC) multiplied by 864. If no HSYNC signal
is available an internal horizontal synchronisation signal is derived from CLL (CLL
divided by 879).

The input signal at VSYNC is the vertical time reference. It has to pass a window
avoiding too short or long V-periods in the case of distorted or missing VSYNC pulses.
The window allows a VSYNC pulse only after a minimum number of lines from its
predecessor and sets an artificial one after a maximum number of lines. The window size
is programmable by

C Bus.

The beam current dependent input signal IBEAM is A/D converted and then digitally
processed. The A/D Converter requires a clock frequency twice the frequency of CLL
which is generated by an internal analog PLL with an external loop filter at pin LF.

Values which influence shape and amplitude of the output signals are transmitted as
reduced binary values to the SDA 9362 via

C Bus. A CPU which is designed for speed

reasons in a pipe line structure calculates in consideration of feedback signals (e.g.
IBEAM) values which exactly represent the output signals. These values control after
D/A conversion the external deflection and raster correction circuits. The CPU firmware
is stored in an internal ROM.

SDA 9362

Semiconductor Group

1998-02-01

2.3

Reset Modes

The circuit is only completely reset at power-on/off (timing diagram refer 5.3). If the pin
RESN has L-level or during standby operation some parts of the circuit are not affected
(timing diagram refer 5.4):

Note: Power-On-Reset state is deactivated after ca. 32 cycles of the X1/X2 oscillator

clock. RESN = Low and standby state are deactivated after ca. 42 cycles of the
CLL clock.

2.4

Frequency Ranges

The allowed deviation of all input line frequencies is max. ± 4.5 %.
n

Number of lines per frame

Interlaced

NI:

Non interlaced

Inactive if HPROT < V2 (typ. 2.4 V)

Can only be read after Power-On-Reset is finished

Power-On-Reset

External Reset
(pin RESN=0)

Standby Mode
(

C-Bit STDBY=1)

HD output

High

Active

H-protection

Inactive

Active

V-protection

Inactive

Active

C Interface (SDA,

SCL)

Tristate

Ready

C Register

..1B

Set to default values Set to default values Set to default values

C Register

, 48

Set to default values Not affected

Not affected

Status bit PONRES

Set to 1

Not affected

REFP

Not affected

REFH

REFL

Not affected

Inactive

CPU

Inactive

31.25 kHz

50 Hz
100 Hz

625 NI / 1250I
625 I

31.5 kHz

60 Hz
120 Hz

525 NI / 1050 I
525 I

SDA 9362

Semiconductor Group

1998-02-01

If NSA = 0 (subaddress 01

/D5

) number of lines per field is selfadaptable between 192

and 680 for each specified H-frequency.

2.5

C-Bus Control

2.5.1

C-Bus Address

2.5.2

C-Bus Format

write:

read:

Reading starts at the last write address n. Specification of a subaddress in reading mode
is not possible.

Start condition

Acknowledge

Stop condition

NA:

Not acknowledge

An automatical address increment function is implemented.

After switching on the IC, all bits are set to defined states (00

) (exception: HDE depends

on pin 33; see page 17)

1 0 0 0 1 1 0

S 1 0 0 0 1 1 0 0 A

Subaddress

Data Byte

A *****

S 1 0 0 0 1 1 0 1 A

Status byte

Data Byte n

A ***** NA P

SDA 9362

Semiconductor Group

1998-02-01

2.5.3

C-Bus Commands

see 2.5.5: Explanation of some control items

Control Item

Sub

addr

. D7 D6 D5 D4 D3 D2 D1 D0 Allowed

Range

Effective

Range

Can be

Disabled

by Bit

Default

Value if

Disabled

Unit

Deflection control 0

see below

Deflection control 1

see below

Vertical shift