Edition 1998-02-01

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Siemens AG 8.2.98.

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Data Classification

Maximum Ratings

Maximum ratings are absolute ratings; exceeding only one of these values may cause
irreversible damage to the integrated circuit.

Recommended Operating Conditions

Under this conditions the functions given in the circuit description are fulfilled. Nominal
conditions specify mean values expected over the production spread and are the
proposed values for interface and application. If not stated otherwise, nominal values will
apply at

= 25°C and the nominal supply voltage.

Characteristics

The listed characteristics are ensured over the operating range of the integrated circuit.

Edition 1998-02-01

Published by Siemens AG, Semiconductor Group
Copyright

Terms of delivery and right to change design reserved.

SDA 9255
Revision History:

Current Version: 1998-02-01

Previous Version:

1997-07-01

Page
(in previous
Version)

Page
(in current
Version)

Subjects (major changes since last revision)

Definition of N.C. pins

SDA 9255

Table of Contents

Page

Semiconductor Group

1998-02-01

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.2

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.3

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.4

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.5

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

System Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1

Input Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2

Output Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.3

Input Timing and Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.3.1

Delay of Vertical Input Synchronization Signal . . . . . . . . . . . . . . . . . . . . . . 11

2.3.2

Number of Active Lines of an Input Field . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.3.3

Number of Not Active Lines of an Input Field . . . . . . . . . . . . . . . . . . . . . . . . 12

2.3.4

Not Active Pixels of Input Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.4

Output Timing and Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.4.1

Number of Not Active Lines of Output Field . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.4.2

Number of Not Active Pixels of Output Field . . . . . . . . . . . . . . . . . . . . . . . . 15

2.4.3

VOUT, HOUT and HREF Signal Length . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.4.4

Output Synchronization Raster and Interlaced Output Signal . . . . . . . . . . . 16

2.5

Motion Adaptive Temporal Noise Reduction . . . . . . . . . . . . . . . . . . . . . . . . 17

2.6

Digital Vertical Zooming and Panning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.7

C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.7.1

C-Bus Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.7.2

C-Bus Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.7.3

C-Bus Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2.7.4

Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.1

Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.2

Characteristics (Assuming Recommended Operating Conditions) . . . . 34

Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.1

Input Timing of the SDA 9255 (HSINP = 0) . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.2

Output Timing of the SDA 9255 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

5.3

Internal Vertical Synchronization Signal (VSINP = 0) . . . . . . . . . . . . . . . . . 37

5.4

Example for Not Active Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

5.5

Example for Not Active Output Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

5.6

Example for Not Active Output Pixels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5.7

Timing for HOUT Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5.8

Timing for VOUT Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5.9

Timing for HREF Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

P-MQFP-64-1

Semiconductor Group

1998-02-01

SRC-Scan Rate Converter

SDA 9255

CMOS

Type

Ordering Code

Package

SDA 9255

Q67101-H5190

P-MQFP-64-1

Overview

1.1

Features

· 100/120 Hz interlaced scan conversion

· Data format 4:1:1

· On chip field memory

· Digital vertical zooming

· Digital vertical panning

· Motion adaptive temporal noise reduction, field based

· Still field

· Color difference input data representation 2's complement or unsigned

· Color difference output data representation 2's complement or unsigned

· Sync Generation for backend IC

C-Bus control (400 kHz)

· P-MQFP-64 package

· 5 V ± 5 % supply voltage

1.2

General Description

The SDA 9255 is a new component of the Siemens MEGAVISION

IC set. The

SDA 9255 comprises some of the functionalities of the MEGAVISION

IC's SDA 9220

(Memory Sync Controller) and SDA 9254 (Triple TV-SAM plus Noise Reduction) and can
therefore be used as a low cost digital featurebox.

SDA 9255

Semiconductor Group

1998-02-01

1.4

Pin Description

S: supply,

I: input,

O: output,

TTL: digital (TTL)

Pin No.

Name

Type

Description

2,8,24,26,41,55,
57

Supply voltage (

= 0 V)

9,25,40,56

Supply voltage (

= 5 V)

42,...,49

YIN0 ... 7

I/TTL

Data input Y (see data format)

36,...,39

UVIN4 ... 7

I/TTL

Data input UV (see data format)

SYNCEN

I/TTL

Synchronization enable input

RESET

I/TTL

System reset. The RESET input is low active.
In order to ensure correct operation a "Power
On Reset" must be performed. The RESET
pulse must have a minimum duration of two
clock periods of the system clock (LL2CLK).

HIN

I/TTL

H-Sync input

VIN

I/TTL

V-Sync input

SDA

I/O

C-Bus data line

SCL

C-Bus clock line

TESTIN

I/TTL

Test input, connect to

for normal operation

TESTEN

I/TTL

Test enable input, connect to

for normal

operation

13,...,10

UVOUT4 ... 7

O/TTL Data output UV (see data format)

7,...,3,1,64,63

YOUT0 ... 7

O/TTL Data output Y (see data format)

HREF

O/TTL Horizontal active video output

VOUT

O/TTL V-Sync output

HOUT

O/TTL H-Sync output

INTERLACED O/TTL Interlace signal for AC coupled vertical

deflection

58,51

LL2CLK

I/TTL

System clock

TEST

I/TTL

Test input, connect to

for normal operation

27,28,29,
52,53,54

TESTO 4...9

Do not connect, Pins have to be left open

14,15,16,17

TESTO 0...3

Not used output stages, do not connect to any
other driver,

; Pins can be left open

32,33,34,35

TESTI 0...3

Input stages (internal pull-down); Pins can be
left open

SDA 9255

Semiconductor Group

1998-02-01

System Description

The device generates at its output an opportune sequence of 100/120 Hz fields (

)

[50/60 Hz frames (

)] derived by processing the field A or B which is stored in one

internal field memory. The fields can be noise reduced and vertically zoomed.

Additionally the device generates a vertical sync pulse, a horizontal sync pulse and a
horizontal reference signal (horizontal active video output) in phase with the output data.
Furthermore an interlace signal for AC coupled vertical deflection is available.

2.1

Input Data Formats

The SDA 9255 accepts at the input side the following input format (relations of Y : (B-Y) :
(R-Y) : 4 : 1 : 1). The representation of the samples of the chrominance signal is
programmable as positive dual code (unsigned) or two's complement code (TWOIN,
TWOOUT, subaddress 00

, see description of

C Bus).

X: signal component,

A: sample number,

B: bit number

The amplitude resolution for each input signal component is 8 Bit, the maximum clock
frequency is 27 MHz.

Data
Pin

SDA 9255

YIN7

YIN6

YIN5

YIN4

YIN3

YIN2

YIN1

YIN0

UVIN7

UVIN6

UVIN5

UVIN4

SDA 9255

Semiconductor Group

1998-02-01

2.2

Output Data Formats

X: signal component,

A: sample number,

B: bit number

2.3

Input Timing and Parameter

The SDA 9255 has five input signals:

The SDA 9255 includes a V-Sync delay block.This is implemented to make sure that the
field identification is working correctly. This is briefly described below.

The phase relation of the incoming horizontal synchronization signal (HIN) and the
incoming data for HSINP = 0 and VSINP = 0 is shown in figure 7 (see chapter 5.1, Input
Timing of the SDA 9255 (HSINP = 0)). The SDA 9255 needs the synchronization
enable input (SYNCEN) which is used to gate HIN and VIN. This is implemented for
frontends which are working with 13.5 MHz and a large output delay time for H-Sync and

Data
Pin

YOUT7

YOUT6

YOUT5

YOUT4

YOUT3

YOUT2

YOUT1

YOUT0

UVOUT7

UVOUT6

UVOUT5

UVOUT4

HIN

Pin 23

Horizontal synchronization signal - low
or high active

VIN

Pin 22

Vertical synchronization signal - low or
high active

SYNCEN

Pin 30

Enable signal for HIN and VIN signal,
low active

YIN0 ... 7

Pin 42, 43, 44, 45, 46, 47 ,48, 49

Luminance input

UVIN4 ... 7 Pin 36, 37, 38, 39

Chrominance input

SDA 9255

Semiconductor Group

1998-02-01

V-Sync (e.g. Intermetall VPC3200A, output delay: 35 ns). For this application the half
system clock (13.5 MHz) from the frontend should be provided at this pin. In case the
frontend is working at 27.0 MHz with sync signals whose delay time are smaller than
25 ns, this input can be set to low level (SYNCEN =

) (e.g. Siemens SDA 9257,

SDA 9206, output delay: 25 ns).

Thus the falling edge of HIN signal is detected when the SYNCEN input is low. The
incoming HIN (and VIN) is sampled with the system clock (LL2CLK = 27.0 MHz). The
register value HSDLY and MCNAPIP (subaddress 0B

and 0C

, see description of

Bus) have to be adjusted in the way that the distance from the falling edge of the HIN to
the first active pixel is correct. The half, quarter and eighth system clock is also shown
in this diagram. They are generated inside the SDA 9255. The half system clock
(LL_CLK = 13.5 MHz) is used to sample the incoming YUV data and run some blocks
inside the SDA 9255. The quarter system clock (LH_CLK = 6.75 MHz) is used to run
some blocks inside the SDA 9255. The eighth system clock (LQ_CLK = 3.375 MHz) is
used to synchronize the 4:1:1 input data stream. The setting of the register HSDLY and
MCNAPIP is explained in chapter 1.

The SDA 9255 has a fixed number of active pixels per input line. It is fixed to 720
luminance pixels and 180 chrominance pixels.

2.3.1

Delay of Vertical Input Synchronization Signal

In order to have always the same raster of the vertical and horizontal synchronization
signal inside the SDA 9255 it is possible to shift the V-Sync signal. The subaddress 09

of the SDA 9255 (VSDLY, see description of

C Bus) controls the shift of the V-Sync.

The user has to know the input sync raster and then the user can adjust the VSDLY
register value in the way that the field identify circuit inside the SDA 9255 can work
properly. The adjustment of the V-Sync can be done in steps of 32 clock periods
(LL2CLK). Thus the delay is also dependent on the system clock frequency. The formula
to calculate the delay is shown below.

DELAY (VIN to VS_int) = (VSDLY

32 + 7 ... 11)

LL2CLK

where:

VIN:

Incoming V-Sync at pin 22; VSDLY: is the register value

VS_int:

Internal V-Sync

LL2CLK

System clock period (e.g 1/27.0 MHz = 37.04 ns)

The initial delay (7 ... 11 system clocks) is caused by flip-flops at the input. This delay is
not a fixed number, because a quarter of the system clock (LH_CLK) is used to set the
delay. The phase of the LH_CLK is dependent on the RESET and the SYNCEN
(see figure 7).

An example shows figure 9 (see chapter 5.3, Internal Vertical Synchronization Signal
(VSINP = 0)). In this example the falling edge of the VIN signal of field A is at 35

s and

the falling edge of the VS_int signal is at 16

s (both signals are related to the falling

SDA 9255

Semiconductor Group

1998-02-01

edge of the previous HS_int, compare chapter 1). Thus the sampling points of the field
identify circuit (marked in the diagram with ,,a" and ,,b") have uniform distances to the
falling edge of the VS_int.

The falling edge of the VIN signal of field B is at 3

s and the falling edge of the VS_int

signal is at 48

s (related to the falling edge of the previous HIN). Here the sampling

points have also uniform distances to the falling edge of the VS_int signal. The user
should adjust this value carefully. Dependent on the input mode of the frontend circuit
the integration time of the V-Sync can change. For non-standard signals, for instance, a
shorter integration time may be chosen. The internal V-Sync (VS_int) must have the
falling edge at line 2 for field A. All the other settings (NALIP ...) are dependent on this
internal V-Sync. The default setting of the VSDLY is 3A

. This corresponds to a delay of

about 69

s (58 (= 3A

)

37 ns), which suits for the clock sync generator

SDA 9257 and SDA 9206.

2.3.2

Number of Active Lines of an Input Field

The subaddress 0A

(AL, see description of

C Bus) is used to adjust the number of

active lines per input and output field. It is independent of the MODE10050 in
subaddress 00

. The register value AL has to be chosen in the following way:

2.3.3

Number of Not Active Lines of an Input Field

Due to the fact that the SDA 9255 stores only the active field in the field memory, it
requires the information of the start of the active field and the active line. A not-active-
line counter (NALIP, subaddress 0B

, see description of

C Bus) starts counting the

incoming H-Syncs when it detects a falling edge of the VS_int signal. If VS_int is adjusted
as recommended in the explanation of subaddress 09

then the calculation of the NALIP

value can be done in the following way:

NALIP = first active line of field A 5 (e.g. 23 5 = 18)

In figure 10 (see chapter 5.4, Example for Not Active Input Register) an example for
NALIP = 18 is shown. As you can see for field A 21 H-Syncs are counted and for field B
22 H-Syncs are counted. If NALIP is set to '0' line 5 is the first active line of field A and
line 318 the first active line of field B (318 5 = 313). The difference between first active
line of field B and field A should be:

= (No.lines per frame DIV 2) + 1; e.g.

= 625 DIV 2 + 1 = 313

Number of lines per field

-------------------------------------------------------------------------- e.g.

288

-------------------

143

;

SDA 9255

Semiconductor Group

1998-02-01

2.3.4

Not Active Pixels of Input Field

In the SDA 9255 an H-Sync delay circuit is implemented. The output of this block is the
HS_int. The distance of the incoming H-Sync (HIN, falling edge for HSINP = 0) and the
active data is adjustable by the HSDLY register value and the MCNAPIP register value
(subaddress 0B

and 0C

, see description of

C Bus). With the HSDLY register the

delay of the external (HIN) to the internal H-Sync (HS_int) is adjustable.

DELAY (HIN to HS_int) = (HSDLY

64 + 4)

LL2CLK

This internal H-Sync (HS_int) is fed to the memory control unit. The MCNAPIP (memory
controller not active pixel at input) is used to adjust the distance to the active line in steps
of one system clock period. So the MCNAPIP is used to set the phase of the internal
generated clocks LL_CLK, LH_CLK and LQ_CLK.

DELAY (HS_int to active data) = (MCNAPIP + 61)

LL2CLK

The total distance of the falling edge of the incoming H-Sync (HIN, falling edge for
HSINP = 0) to the active data of the line is:

DELAY (HIN to active data) = (HSDLY

64 + MCNAPIP + 65)

LL2CLK

In the formula above you can see that the first active pixel occurs 65 system clocks after
the falling edge of the HIN signal, if HSDLY and MCNAPIP are set to zero.

In the figure 7 (see chapter 5.1, Input Timing of the SDA 9255 (HSINP = 0)) the input
timing of the SDA 9255 is shown. The luminance and chrominance data are coming with
half the system clock speed (e.g. 13.5 MHz). The SDA 9255 accepts the YIN data every
second edge of the LL2CLK clock; in the SDA 9255 the luminance and chrominance
data are sampled with the rising edge of the internal LL_CLK, which is half the system
clock (e.g. 13.5 MHz). At the position of the first active pixel the phase of the half system
clock (LL_CLK = 13.5 MHz), the quarter system clock (LH_CLK = 6.75 MHz) and the
eighth system clock (LH_CLK = 3.375 MHz) is always as shown in the diagram. The
LL_CLK is used for sampling the incoming data. The LQ_CLK is used to synchronize the
4:1:1 data stream.

SDA 9255

Semiconductor Group

1998-02-01

2.4

Output Timing and Parameter

The SDA 9255 has six output signals:

There are different modes of output synchronization raster possible. The data output
signal of the SDA 9255 (YOUT, UVOUT and HREF) are fed to the digital-to-analog
converter. The timing of the output signals is given in figure 8 (see chapter 5.2, Output
Timing of the SDA 9255).

2.4.1

Number of Not Active Lines of Output Field

The register values NALOP and NAPOP are used to set the position of the active output
field on the screen. To do this the register value to align the not active lines (NALOP,
subaddress 0D

, see description of

C Bus) and the register value to align the not

active pixels (NAPOP, subaddress 0E

, see description of

C Bus) for the output

signal are available.

To change the vertical position of the picture on the screen the NALOP register can be
utilized. The NALOP register (not active lines for output) is used to adjust the number of
not active output lines in steps of two lines in case of 100/120 Hz interlaced and in steps
of four lines in case of 50/60 Hz proscan. To calculate the first active output line the
following formula can be used:

for MODE10050 = 0 ==> 100/120 Hz interlaced:

FAOPL = NALOP

2 + 3

for MODE10050 = 1 ==> 50/60 Hz proscan:

FAOPL = NALOP

4 + 5

where

FAOPL:

The first active output line

NAL_OP:

The maximum value for the first active line is 65 for 100/120 Hz and 129 for 50/60 Hz.

In figure 11 (see chapter 5.5, Example for Not Active Output Register) an example
for the setting of the NALOP register is shown. The synchronization output (HOUT,

HOUT

Pin 60

Horizontal synchronization signal - high
active

VOUT

Pin 61

Vertical synchronization signal - high active

HREF

Pin 62

Horizontal active video output

INTERLACED Pin 59

Interlace signal

YOUT0 ... 7

Pin 7, 6, 5, 4, 3, 1, 64, 63 Luminance output

UVOUT4 ... 7

Pin 13, 12, 11, 10

Chrominance output

SDA 9255

Semiconductor Group

1998-02-01

VOUT, HREF) signals are high active. In the example the register value is 10 and the
mode is '0' (100/120 Hz/interlaced).

FAOPL = NALOP

2 + 3 = 10

2 + 3 = 23

So line 23 is the first active output line.

For proper operation the number of not active lines at output side plus the number of
active lines have to be smaller than the total number of lines. The following formula
should be true.

NALOP

2 + AL

2 + 3

(No. of lines per frame) DIV 2 (e.g. 312)

where

AL:

NALOP:

2.4.2

Number of Not Active Pixels of Output Field

To change the horizontal position of the picture on the screen the NAPOP register value
can be utilized. The not active pixels for output register ( NAPOP ) is used to adjust the
number of not active output pixels of a line. The register value is multiplied by '4' and
has an initial value of 9 ... 12 (HSODLY = 0), depending on the MCNAPIP setting
(subaddress 0B

and 0C

, see description of

C Bus).

FAOPP = NAPOP

4 + 9 ... 12 HSODLY = 0

FAOPP = NAPOP

4 + (- 163) ... (- 160) ; HSODLY = 1

is equal to : FAOPP = NAPOP

4 + 9 ... 12 172

HSODLY

where

FAOPP:

The first active output pixel after rising edge of HOUT

NAPOP:

HSODLY:

The time from the rising edge of the HOUT signal to the first active output pixel can be
calculated in the following way:

NAPOP

= ( NAPOP

4 + 9 ... 12 )

LL2CLK

; HSODLY = 0

NAPOP

= (NAPOP

4 + (- 163) ... (-160))

LL2CLK

; HSODLY = 1

where

NAPOP

: Time from rising edge of HOUT to first active output pixel

LL2CLK

: System clock period (e.g. 1/27 MHz)

figure 12 (see chapter 5.6, Example for Not Active Output Pixels) shows the effect of
the register NAPOP.

SDA 9255

Semiconductor Group

1998-02-01

2.4.3

VOUT, HOUT and HREF Signal Length

The length of the output synchronization signals (HOUT, VOUT) is fixed. The HOUT
signal is active high with a length of 32 system clocks (27.0 MHz) which corresponds to
a length of 1.185

s. The VOUT signal is also active high with a length of 2 output lines.

So in case of PAL B/G the active high period of the VOUT lasts for 64

s (see figure 13,

Timing for HOUT Signal and figure 14, Timing for VOUT Signal).

The HOUT signal of the SDA 9255 can be delayed by a fixed value of 172 system clocks
(27.0 MHz) by setting the HSODLY bit of subaddress 0F

to '1'(see description of

C Bus). The number of active pixels per line is constant 720 pixels. The HREF output

signal (pin 62) indicates the active part of the output lines. The length is also constant
(720 system clocks). During the vertical and horizontal blanking period this signal is low.
The timing is shown in figure 15 (see chapter 5.9, Timing for HREF Signal). The
chrominance output format is like the output format as described in chapter 1.

2.4.4

Output Synchronization Raster and Interlaced Output Signal

The output synchronization and data raster in 100/120 Hz mode can be set by the
MODESYNC register value (subaddress 01

, see description of

C Bus). In case of

MODE10050 = 1 (50/60 Hz pro-scan mode) this register value has no effect.

The interlaced signal INTERLACED (pin 59) is a control signal which may be used to
control an AC coupled vertical deflection unit. If the MODESYNC register value
(subaddress 01

, see description of

C Bus) is set to AABB mode, where field 2 and

3 have to be shifted down (MODESYNC = 10). For this the interlaced register INTL
(subaddress 0D

and 0E

, see description of

C Bus) must be set to 0110. In figure

16 (see chapter 5.10, Example for INTERLACED Signal) an example for the INTL
register value is shown. Bit zero defines the output for the first field (field A); bit one
defines the output for the second field (field A); bit two defines the output of the third field
(field B); bit three defines the output of the fourth field (field B). So if the bit is set to zero
then the output is low and if the bit is set to one then the output is high. For DC coupled
vertical deflection the INTERLACED signal is not required.

SDA 9255

Semiconductor Group

1998-02-01

2.5

Motion Adaptive Temporal Noise Reduction

Figure 3
Block Diagram of Noise Reduction

The diagram above shows a block diagram of the motion adaptive noise reduction. The
noise reduction in the luminance path has the same structure as the noise reduction in
the chrominance path. Subaddresses 02

and 03

(NRKF0, NRKF1, NRKF2, NRKF3,

see description of

C Bus) are used to align the filter coefficients of the noise

reduction IIR filter. Four different k-factors NRKF0 ... 3 can be modified which are fed to
the multiplier of the IIR filter. Depending on the output of the motion detection for noise
reduction (MDFORNR) the corresponding k-factor NRKF0 ... 3 is used for the IIR filter
(see the table below).

EB10015

LUT

Address

MDFORNR

NRKF0
NRKF1
NRKF2
NRKF3

YIN/UVIN

Field

Memory

k-factor

SDA 9255

Semiconductor Group

1998-02-01

Table 1
MDFORNR and Corresponding k-Factor

For NRKF0 ... 3 values between 0 and 7 can be chosen. The following table shows the
theoretical amount of noise reduction dependent on the applied k-factor.

Table 2
Filter Coefficients Dependent on the k-Factor

The subaddresses 04

, 05

and 06

(MDNRTH0, MDNRTH1, MDNRTH2,

see description of

C Bus) are used to align the motion detection for noise reduction

(MDFORNR). The sensitivity of the motion detection is influenced by changing the
threshold levels of the motion values. A rough block diagram of the motion detection for
noise reduction is shown below.

MDFORNR

k-Factor

Mode

NRKF0

Still

NRKF1

Quasi still

NRKF2

Quasi motion

NRKF3

Motion

k-Factor

Amount of NR

0 dB

1.1 dB

2.2 dB

3.4 dB

4.8 dB

6.4 dB

8.5 dB

11.8 dB

SDA 9255

Semiconductor Group

1998-02-01

Figure 4
Block Diagram of Motion Detection for Noise Reduction

The input signals for the motion detection for noise reduction are the just incoming
luminance signal (YIN) and the already noise reduced luminance signal on one field
delay (DYIN). Both signals are fed to a subtractor, followed by a low pass filter. This filter
can be bypassed by setting the NRHF bit (see description subaddress 08

, Bit 0) to

'0'. The absolute value is calculated and given to a limiter block. The output signal is fed
to the threshold block, where the value is quantized by using the 3 threshold values
MDNRTH0, MDNRTH1 and MDNRTH2. The quantization characteristic of the threshold
block is shown by the following table and diagram.

Table 3
Quantization Table of MDFORNR

Input Value

Output

Mode

0 ... (TH0 1)

Still

TH0 ... (TH1 1)

Quasi still

TH1 ... (TH2 1)

Quasi motion

TH2 ... 31

Motion

Noise

Reduction

Memory

Field

YIN

DYIN

Filter

Low Pass

MUX

ABS

LIMITER

THRESHOLD

MUX

MDNRTH2

MDNRTH1

MDNRTH0

MDFORNR

NRHF

SNR

FNR

UEB10016

SDA 9255

Semiconductor Group

1998-02-01

2.6

Digital Vertical Zooming and Panning

The user can choose 17 different zoom factors and 37 pan factors. Every zoom factor
can be used without considering other register values, but on the other hand the pan
factor is very much dependent on the zoom factor. So be careful in choosing the pan
factor. In the following table the zoom factor (subaddress 0F

, see description of

C Bus) and the corresponding visual zoom of the input field is shown. In the third

column the required number of input lines is shown, when the number of displayed
output lines is 288. The fourth column shows the allowed value PAN value (subaddress
10

, see description of

C Bus) and the last column the PAN register value for vertical

centre position.

Table 5
Table of Zoom Factors and Panning Factors

Dependent on the zoom factor the SDA 9255 requires a certain number of input lines of
a field.

Zoom

Visual Zoom

NoIPL
(NoOPL = 288)

Panning Range
PAN

Centre Panning
PAN

288

1.03

279

0 ... 2

1.06

270

0 ... 4

1.10

261

0 ... 6

1.14

252

0 ... 9

1.18

243

0 ... 11

1.23

234

0 ... 13

1.28

225

0 ... 15

1.33

216

0 ... 18

1.39

207

0 ... 20

1.45

198

0 ... 22

1.52

189

0 ... 24

1.6

180

0 ... 27

1.68

171

0 ... 29

1.77

162

0 ... 31

1.88

153

0 ... 33

2.0

144

0 ... 36

SDA 9255

Semiconductor Group

1998-02-01

where

NoIPL:

Number of required input lines

NoOPL:

Number of generated output lines (AL

2) + 2

ZOOM:

In the third column of the table above the required number of input lines is shown, if the
generated number of output lines is 288 (AL = 143). In the last row you can see that for
the visual zoom factor of 2 half the number of input lines is necessary, which is of course
obvious.

As mentioned before, only zoom factors between '0' and '16' are allowed. If factors bigger
than 16 are chosen, they are set to '16'.

Panning is possible in steps of 4 input lines. So the first active input line which is used to
generate the first active output line can be calculated in the following way:

FAIPL = PAN

4 + 1

where

FAIPL:

First active input line to generate the first active output line

PAN:

With PAN = 0 the first active input line is line 1, as expected. In case of PAN = 1 the first
active input line is line 5, etc.

So the allowed register value for pan can be calculated from the last column of the table
above. In this example with 288 active lines and, for instance, zoom factor of '15', the
maximum pan factor is '2'. Pan = '3' is permitted which can be seen by this calculation:
3

4 + 279 = 291. The required number of input lines plus the panning lines is larger

than the actual number of input lines (288). A formula to calculate the maximum pan
factor is shown below.

After some rearranging of the formula we get this simple formula to calculate the
maximum register value of the pan factor.

where

NoIPL:

Number of required input lines

NoOPL:

Number of generated output lines (AL

2) + 2

NoIPL

NoOPL

ZOOM

-----------------------------------------

PAN

int

NoOPL

NoIPL

---------------------------------------------

PAN

int

NoOPL

---------------------

ZOOM

-------------------------------

SDA 9255

Semiconductor Group

1998-02-01

ZOOM:

PAN:

In the fourth column of table 5 the panning range is shown for NoOPL = 288.

If the pan factor is larger than specified in the previous equation, the last input line is used
for interpolation of the remaining lines. On the screen the last line is repeated.

2.7

C Bus

2.7.1

C-Bus Slave Address

2.7.2

C-Bus Format

The SDA 9255

C-Bus interface acts as a slave receiver and a slave transmitter and

provides three different access modes (write, read, continuous read). All modes run with
a subaddress auto increment. The interface supports the normal 100 kHz transmission
speed as well as the high speed 400 kHz transmission.

Write:

Start condition

Acknowledge

Stop condition

NA:

Not Acknowledge

Read:

Continuous Read:

The transmitted data are internally stored in registers. The master has to write a don't
care byte to the subaddress FF

(store command) to make the register values available

for the SDA 9255. To have a defined time step, where the data will be available, the data
are made valid with the incoming V-Sync or with the next SYNC_ST pulse, which is an
internal signal and indicates the start of a new output cycle of either four fields in 100/
120 Hz interlaced mode or two frames in 50/60 Hz proscan mode. The subaddresses,
where the data are made valid with the V-Sync (every 20 ms) are indicated in the
overview of the subaddresses with ,,V", where the data are made valid with the

1 0 1 1 1 1 0

1 0 1 1 1 1 0 0 A

Subaddress

Data Byte

*****

A P

S 1 0 1 1 1 1 0 0 A Subaddress A S 1 0 1 1 1 1 0 1 A Data Byte A

*****

Data Byte

*****

Data Byte

NA P

Write Address: BC

Read Address: BD

SDA 9255

Semiconductor Group

1998-02-01

SYNC_ST (every 40 ms) are indicated with ,,S". The

C-Bus status bits of the SDA 9255

(sub19

, Bit 7; sub1E

, Bit 7) reflect the state of the register values. If these bits are read

as '0' then the store command was sent, but the data aren't made available yet. If these
bits are '1' then the data were made valid and a new write or read cycle can start. The

C-Bus status bits have to be checked before writing or reading new data, otherwise

data can be lost by overwriting.

After switching on the IC, all bits of the SDA 9255 are set to defined states. In particular:

R/W:

R-Read Register,

W-Write Register,

R/W-Read and Write Register,

Take over:

V-take over with V-Sync,

S-take over with SYNC_ST

Subaddress Default

Value

R/W Take

Over

Subaddress Default

Value

R/W

Take
Over

R/W

... 18

not used

R/W

not used

R/W

... 1D

not used

R/W

... FE

not used

R/W

SDA 9255

Semiconductor Group

1998-02-01

2.7.3

C-Bus Commands

x = don't care

Subadd.
(Hex.)

Data Byte

MODE10050 1

FREEZE

TWOIN

TWOOUT

TVMODE1

TVMODE0

MODESYNC1 MODESYNC0

NRKF02

NRKF01

NRKF00

NRKF12

NRKF11

NRKF10

NRKF22

NRKF21

NRKF20

NRKF32

NRKF31

NRKF30

HSINP

VSINP

MDNRTH04 MDNRTH03 MDNRTH02 MDNRTH01 MDNRTH00 x

MDNRTH14 MDNRTH13 MDNRTH12 MDNRTH11 MDNRTH10 x

MDNRTH24 MDNRTH23 MDNRTH22 MDNRTH21 MDNRTH20 x

SNR

FNR1

FNR0

NRHF

VSDLY6

VSDLY5

VSDLY4

VSDLY3

VSDLY2

VSDLY1

VSDLY0

AL7

AL6

AL5

AL4

AL3

AL2

AL1

AL0

NALIP4

NALIP3

NALIP2

NALIP1

NALIP0

MCNAPIP6

MCNAPIP5

MCNAPIP4

MCNAPIP3

MCNAPIP2

MCNAPIP1

MCNAPIP0

HSDLY3

HSDLY2

HSDLY1

HSDLY0

NALOP4

NALOP3

NALOP2

NALOP1

NALOP0

INTL3

INTL2

INTL1

NAPOP6

NAPOP5

NAPOP4

NAPOP3

NAPOP2

NAPOP1

NAPOP0

INTL0

ZOOM4

ZOOM3

ZOOM2

ZOOM1

ZOOM0

HSODLY

PAN5

PAN4

PAN3

PAN2

PAN1

PAN0

VSTATUS

SSTATUS

SDA 9255

Semiconductor Group

1998-02-01

2.7.4

Detailed Description

Subaddress 00

Bit

Name

Function

MODE10050

Output mode switch:
0:

100/120 Hz (default value)

50/60 Hz

Should be set to 1

FREEZE

Still picture:
0:

Off (default value)

TWOIN

Chrominance input format:
0:

Unsigned input (0 ... 255)

2's complement input (-128 ... 127) (default value)

Inside the SDA 9255 the data are always processed as
unsigned data

TWOOUT

Chrominance output format:
0:

Unsigned output (0 ... 255)

2's complement output (-128 ... 127) (default
value)

D1 ... D0 TVMODE

Television system:
00:

NTSC (1716)

01:

Automatic PAL (n

32)

10:

Automatic NTSC (n

32 + 20)

11:

PAL (1728) (default value)

The SDA 9255 is designed for a line-locked system.
Therefore the number of system clock periods between two
H-Sync (HIN) must be constant. In PAL (1728) mode the
number of system clocks (~27.0 MHz) per input line is
assumed to be constant 1728. In case of NTSC (1716)
mode the number of system clock periods is assumed to be
constant 1716. In automatic mode (01 and 10) the number
of system clock periods (~27.0 MHz) per incoming line is
measured and used to calculate the outgoing line length. In
automatic PAL mode the number of system clock periods
between two H-Syncs must be n

32 (n = 1, 2, ..., 54, ...).

In automatic NTSC mode the number of system clock
periods between two H-Syncs must be
n

32 + 20 (n = 1, 2, ..., 53, ...).

SDA 9255

Semiconductor Group

1998-02-01

Subaddress 08

Bit

Name

Function

SNR

Switch for fixed value for motion detection for noise
reduction
0:

Off (default value)

D6 ... D5 FNR

Fixed value for motion detection for noise reduction
11:

(default value)

D4 ... D1

xxxx

NRHF

Switch for low pass filter for motion detection for noise
reduction
0:

Off

On (default value)

Subaddress 09

Bit

Name

Function

D7 ... D1 VSDLY

V-Sync input delay (default value 3A

)

Subaddress 0A

Bit

Name

Function

D7 ... D0 AL

(Number of active input lines per field 2) / 2
(default value 8F

)

Subaddress 0B

Bit

Name

Function

D7 ... D3 NALIP

Number of not active lines of input data (default value 12

)

D2 ... D0 MCNAPIP6 ... 4 Number of system clocks from internal HS_int to active

input data, Bit 6 to 4 (default value 4

)

SDA 9255

Semiconductor Group

1998-02-01

Subaddress 0C

Bit

Name

Function

D7 ... D4 MCNAPIP3 ... 0 Number of system clocks from internal HS_int to active input

data, bit 3 to 0 (default value A

)

D3 ... D0 HSDLY

H-Sync input delay (default value 2

)

Subaddress 0D

Bit

Name

Function

D7 ... D3 NALOP

Number of active lines at output (default value A

)

D2 ... D0 INTL3 ... 1

Interlace output for field Bit 3 to 1 (default value 0

)

Subaddress 0E

Bit

Name

Function

D7 ... D1 NAPOP

Number of not active pixels at output (default value 16

)

INTL0

Interlace output for field bit 0 (default value 0

)

Subaddress 0F

Bit

Name

Function

D7 ... D3 ZOOM

Zooming factor (default value 10

)

D2 ... D1

HSODLY

Delay of H-Sync output (default value 1

)

Subaddress 10

Bit

Name

Function

D7 ... D2 PAN

Panning of the output picture (default value 0

)

D1 ... D0

SDA 9255

Semiconductor Group

1998-02-01

Absolute Maximum Ratings

All voltages listed are referenced to ground (0 V,

) except where noted.

Note: Absolute Maximum Ratings are those values beyond which damage to the device

may occur. Functional operation under these conditions or at any other condition
beyond those indicated in the operational sections of this specification is not
implied.

Parameter

Symbol

Limit Values

Unit

Remark

min.

max.

Operating temperature

°C

Storage temperature

-65

125

°C

Junction temperature

125

°C

Soldering temperature

260

°C

Soldering time

Input voltage

-0.3

+ 0.3

Output voltage

-0.3

+ 0.3

Supply voltages

-0.3

Total power dissipation

1.2

ESD protection

-2

MIL STD 883C
method 3015.6,
100 pF, 1500

Latch-up protection

-100

100

All inputs/outputs

SDA 9255

Semiconductor Group

1998-02-01

3.1

Recommended Operating Conditions

Parameter

Symbol

Limit Values

Unit

Remark

min.

nom.

max.

Supply voltages

4.75

5.25

Ambient temperature

0 25

°C

All TTL Inputs

H-input voltage

2.0

L-input voltage

0.8

All TTL Outputs

H-output voltage

2.4

= -2.0 mA

L-output voltage

0.4

= 3.0 mA

INPUT/OUTPUT: SDA

L-output voltage

0.5

= max

Clock TTL Input LL2CLK

Clock frequency

1/T

MHz

see figure 19

Low time

High time

Rise time

TLH

Fall time

THL

C Bus (All values are referred to min (

) and max (

)),

SCL

= 400 KHz

H-input voltage

see figure 17

L-input voltage

1.5

see figure 18

SCL clock frequency

SCL

400

kHz

Inactive time before
start of transmission

BUF

1.3

Set-up time start
condition

SU; STA

0.6

Hold time start
condition

HD; STA

0.6

SCL low time

LOW

1.3

SCL high time

HIGH

0.6

Set-up time DATA

SU; DAT

100

Hold time DATA

HD; DAT

SDA 9255

Semiconductor Group

1998-02-01

3.1

Recommended Operating Conditions (cont'd)

3.2

Characteristics (Assuming Recommended Operating Conditions)

Parameter

Symbol

Limit Values

Unit

Remark

min.

nom.

max.

SDA/SCL rise times

300

SDA/SCL fall times

300

Set-up time stop
condition

SU; STO

0.6

Output valid from
clock

900

Input filter spike
suppression (SDA and
SCL pins)

L-output current

Parameter

Symbol

Limit Values

Unit

Remark

min.

max.

Average supply
current

200

All

pins, typ.

170 mA

All Digital Inputs (Including I/O Inputs)

Input capacitance

Input leakage current

I(L)

-10

TTL Inputs: YIN, UVIN (Referred to LL2CLK)

Set-up time

Input hold time

TTL Inputs: HIN, VIN, SYNCEN (Referred to LL2CLK)

Set-up time

Input hold time

TTL Outputs: YOUT, UVOUT, HOUT, VOUT, HREF, INTERLACED (Referred to
LL2CLK)

Hold time

Delay time

= 30 pF

Document Outline

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Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: Q67101-H5190