C515C Data Sheet

Revision History :

1997-07-01

Previous Releases :

09.96

Page

Subjects (changes since last revision)

4
19
52, 53
56, 57
62

SSC transfer rate at 10 MHz = 2.5 MHz
Figure reference corrected
Power saving modes : description of hardware power down mode added
Icc specification has been extended

SCLK

for Master Mode corrected

Edition 1997-07-01
Published by

Siemens AG,

Bereich Halbleiter, Marketing-
Kommunikation, Balanstraße 73,
81541 München

Siemens AG 1997.

Attention please!

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Critical components

of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems

with the express

written approval of the Semiconductor Group of Siemens AG.
1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the

failure of that life-support device or system, or to affect its safety or effectiveness of that device or system.

2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain hu-

man life. If they fail, it is reasonable to assume that the health of the user may be endangered.

Semiconductor Group

1997-07-01

8-Bit CMOS Microcontroller

Advance Information

C515C

Full upward compatibility with SAB 80C515A

64k byte on-chip ROM (external program execution is possible)

256 byte on-chip RAM

2K byte of on-chip XRAM

Up to 64K byte external data memory

Superset of the 8051 architecture with 8 datapointers

Up to 10 MHz external operating frequency (1

s instruction cycle time at 6 MHz external clock)

On-chip emulation support logic (Enhanced Hooks Technology

)

Current optimized oscillator circuit and EMI optimized design

Eight ports : 48+1 digital I/O lines, 8 analog inputs
Quasi-bidirectional port structure (8051 compatible)
Port 5 selectable for bidirectional port structure (CMOS voltage levels)

Full-CAN controller on-chip
256 register/data bytes are located in external data memory area
max.1 MBaud at 8-10 MHz operating frequency

Three 16-bit timer/counters
Timer 2 can be used for compare/capture functions

(further features are on next page)

Figure 1
C515C Functional Units

Enhanced Hooks Technology

is a trademark of Siemens AG

C515C

Semiconductor Group

1997-07-01

Features (continued) :

10-bit A/D converter with multiplexed inputs and built-in self calibration

Full duplex serial interface with programmable baudrate generator (USART)

SSC synchronous serial interface (SPI compatible)
Master and slave capable
Programmable clock polarity / clock-edge to data phase relation
LSB/MSB first selectable
2.5 MHz transfer rate at 10 MHz operating frequency

Seventeen interrupt vectors, at four priority levels selectable

Extended watchdog facilities
15-bit programmable watchdog timer
Oscillator watchdog

Power saving modes
Slow-down mode
Idle mode (can be combined with slow-down mode)
Software power-down mode with wake-up capability through INT0 pin
Hardware power-down mode

CPU running condition output pin

ALE can be switched off

Multiple separate VCC/VSS pin pairs

P-MQFP-80-1 package

Temperature Ranges :

SAB-C515C-8R

= 0 to 70

SAF-C515C-8R

= -40 to 85

SAH-C515C-8R

= -40 to 110

The C515C is an enhanced, upgraded version of the SAB 80C515A 8-bit microcontroller which
additionally provides a full CAN interface, a SPI compatible synchronous serial interface, extended
power save provisions, additional on-chip RAM, 64K of on-chip program memory, two new external
interrupts and RFI related improvements. With a maximum external clock rate of 10 MHz it achieves
a 600 ns instruction cycle time (1

s at 6 MHz). The C515C is mounted in a P-MQFP-80 package.

Note:

Versions for extended temperature ranges 40

C to 110

C (SAH-C515C-LM and SAH-

C515C-8RM) are available on request. The ordering number of ROM types (DXXXX
extensions) is defined after program release (verification) of the customer.

Ordering Information

Type

Ordering Code

Package

Description
(8-Bit CMOS microcontroller)

SAB-C515C-LM

Q67121-C1066

P-MQFP-80-1 for external memory (10 MHz)

SAF-C515C-LM

Q67121-C1058

P-MQFP-80-1 for external memory (10 MHz)

ext. temp. 40

C to 85

SAB-C515C-8RM

Q67121-DXXXX P-MQFP-80-1 with mask programmable ROM (10 MHz)

SAF-C515C-8RM

Q67121-DXXXX P-MQFP-80-1 with mask programmable ROM (10 MHz)

ext. temp. 40

C to 85

Semiconductor Group

1997-07-01

C515C

Table 1
Pin Definitions and Functions

Symbol

Pin Number

I/O*)

Function

P-MQFP-80

RESET

RESET

A low level on this pin for the duration of two machine
cycles while the oscillator is running resets the C515C. A
small internal pullup resistor permits power-on reset
using only a capacitor connected to VSS .

VAREF

Reference voltage

for the A/D converter

VAGND

Reference ground

for the A/D converter

P6.0-P6.7

12-5

Port 6

is an 8-bit unidirectional input port to the A/D converter.
Port pins can be used for digital input, if voltage levels
simultaneously meet the specifications high/low input
voltages and for the eight multiplexed analog inputs.

*) I = Input

O = Output

C515C

Semiconductor Group

1997-07-01

P3.0-P3.7

15-22

19
20
21

I/O

Port 3

is an 8-bit quasi-bidirectional I/O port with internal pullup
resistors. Port 3 pins that have 1's written to them are
pulled high by the internal pullup resistors, and in that
state can be used as inputs. As inputs, port 3 pins being

externally pulled low will source current (

, in the DC

characteristics) because of the internal pullup resistors.
Port 3 also contains the interrupt, timer, serial port and
external memory strobe pins that are used by various
options. The output latch corresponding to a secondary
function must be programmed to a one (1) for that
function to operate. The secondary functions are
assigned to the pins of port 3, as follows:
P3.0

RXD

Receiver data input (asynch.) or
data input/output (synch.) of serial
interface

P3.1

TXD

Transmitter data output (asynch.) or
clock output (synch.) of serial
interface

P3.2 INT0

External interrupt 0 input / timer 0
gate control input

P3.3 INT1

External interrupt 1 input / timer 1
gate control input

P3.4

Timer 0 counter input

P3.5

Timer 1 counter input

P3.6 WR

WR control output; latches the data
byte from port 0 into the external
data memory

P3.7 RD

RD control output; enables the
external data memory

*) I = Input

O = Output

Table 1
Pin Definitions and Functions (cont'd)

Symbol

Pin Number

I/O*)

Function

P-MQFP-80

Semiconductor Group

1997-07-01

C515C

P7.0 / INT7

I/O

Port 7

is an 1-bit quasi-bidirectional I/O port with internal pull-up
resistor. When a 1 is written to P7.0 it is pulled high by an
internal pull-up resistor, and in that state can be used as
input. As input, P7.0 being externally pulled low will
source current (

, in the DC characteristics) because of

the internal pull-up resistor. If P7.0 is used as interrupt
input, its output latch must be programmed to a one (1).
The secondary function is assigned to the port 7 pin as
follows:
P7.0

INT7 Interrupt 7 input

P1.0 - P1.7

31-24

27
26

25
24

I/O

Port 1

is an 8-bit quasi-bidirectional I/O port with internal pullup
resistors. Port 1 pins that have 1's written to them are
pulled high by the internal pullup resistors, and in that
state can be used as inputs. As inputs, port 1 pins being
externally pulled low will source current (

, in the DC

characteristics) because of the internal pullup resistors.
The port is used for the low-order address byte during
program verification. Port 1 also contains the interrupt,
timer, clock, capture and compare pins that are used by
various options. The output latch corresponding to a
secondary function must be programmed to a one (1) for
that function to operate (except when used for the
compare functions). The secondary functions are
assigned to the port 1 pins as follows:
P1.0

INT3 CC0

Interrupt 3 input / compare 0 output /
capture 0 input

P1.1

INT4 CC1

Interrupt 4 input / compare 1 output /
capture 1 input

P1.2

INT5 CC2

Interrupt 5 input / compare 2 output /
capture 2 input

P1.3

INT6 CC3

Interrupt 6 input / compare 3 output /
capture 3 input

P1.4

INT2

Interrupt 2 input

P1.5

T2EX

Timer 2 external reload / trigger
input

P1.6

CLKOUT

System clock output

P1.7

Counter 2 input

*) I = Input

O = Output

Table 1
Pin Definitions and Functions (cont'd)

Symbol

Pin Number

I/O*)

Function

P-MQFP-80

C515C

Semiconductor Group

1997-07-01

XTAL2

XTAL2
Input to the inverting oscillator amplifier and input to the
internal clock generator circuits.
To drive the device from an external clock source, XTAL2
should be driven, while XTAL1 is left unconnected.

Minimum and maximum high and low times as well as
rise/fall times specified in the AC characteristics must be
observed.

XTAL1

XTAL1
Output of the inverting oscillator amplifier.

P2.0-P2.7

38-45

I/O

Port 2
is an 8-bit quasi-bidirectional I/O port with internal pullup
resistors. Port 2 pins that have 1's written to them are
pulled high by the internal pullup resistors, and in that
state can be used as inputs. As inputs, port 2 pins being
externally pulled low will source current (

, in the DC

characteristics) because of the internal pullup resistors.
Port 2 emits the high-order address byte during fetches
from external program memory and during accesses to
external data memory that use 16-bit addresses
(MOVX @DPTR). In this application it uses strong
internal pullup resistors when issuing 1's. During
accesses to external data memory that use 8-bit
addresses (MOVX @Ri), port 2 issues the contents of
the P2 special function register.

CPUR

CPU running condition
This output pin is at low level when the CPU is running
and program fetches or data accesses in the external
data memory area are executed. In idle mode, hardware
and software power down mode, and with an active
RESET signal CPUR is set to high level.
CPUR can be typically used for switching external
memory devices into power saving modes.

*) I = Input

O = Output

Table 1
Pin Definitions and Functions (cont'd)

Symbol

Pin Number

I/O*)

Function

P-MQFP-80

Semiconductor Group

1997-07-01

C515C

PSEN

The Program Store Enable
output is a control signal that enables the external
program memory to the bus during external fetch
operations. It is activated every six oscillator periods,
except during external data memory accesses. The
signal remains high during internal program execution.

ALE

The Address Latch enable
output is used for latching the address into external
memory during normal operation. It is activated every six
oscillator periods, except during an external data
memory access. ALE can be switched off when the
program is executed internally.

External Access Enable
When held high, the C515C executes instructions always
from the internal ROM. When held low, the C515C
fetches all instructions from external program memory.

P0.0-P0.7

52-59

I/O

Port 0
is an 8-bit open-drain bidirectional I/O port.
Port 0 pins that have 1's written to them float, and in that
state can be used as high-impedance inputs.
Port 0 is also the multiplexed low-order address and data
bus during accesses to external program and data
memory. In this application it uses strong internal pullup
resistors when issuing 1's.
Port 0 also outputs the code bytes during program
verification in the C515C. External pullup resistors are
required during program verification.

P5.0-P5.7

67-60

I/O

Port 5
is an 8-bit quasi-bidirectional I/O port with internal pullup
resistors. Port 5 pins that have 1's written to them are
pulled high by the internal pullup resistors, and in that
state can be used as inputs. As inputs, port 5 pins being
externally pulled low will source current (

, in the DC

characteristics) because of the internal pullup resistors.
Port 5 can also be switched into a bidirectional mode, in
which CMOS levels are provided. In this bidirectional
mode, each port 5 pin can be programmed individually as
input or output.

*) I = Input

O = Output

Table 1
Pin Definitions and Functions (cont'd)

Symbol

Pin Number

I/O*)

Function

P-MQFP-80

C515C

Semiconductor Group

1997-07-01

HWPD

Hardware Power Down
A low level on this pin for the duration of one machine
cycle while the oscillator is running resets the C515C.
A low level for a longer period will force the part to power
down mode with the pins floating.

P4.0-P4.7

72-74, 76-80

72
73

74
76
77
78
79
80

I/O

Port 4
is an 8-bit quasi-bidirectional I/O port with internal pull-up
resistors. Port 4 pins that have 1's written to them are
pulled high by the internal pull-up resistors, and in that
state can be used as inputs. As inputs, port 4 pins being
externally pulled low will source current (

, in the DC

characteristics) because of the internal pull-up resistors.
P4 also contains the external A/D converter control pin,
the SSC pins, the CAN controller input/output lines, and
the external interrupt 8 input. The output latch
corresponding to a secondary functionmust be
programmed to a one (1) for that function to operate.
The alternate functions are assigned to port 4 as follows:
P4.0

ADST

External A/D converter start pin

P4.1

SCLK

SSC Master Clock Output /
SSC Slave Clock Input

P4.2

SRI

SSC Receive Input

P4.3

STO

SSC Transmit Output

P4.4

SLS

Slave Select Input

P4.5

INT8

External interrupt 8 input

P4.6

TXDC

Transmitter output of the CAN controller

P4.7

RXDC

Receiver input of the CAN controller

PE/SWD

Power saving mode enable / Start watchdog timer
A low level on this pin allows the software to enter the
power down, idle and slow down mode. In case the low
level is also seen during reset, the watchdog timer
function is off on default.
Use of the software controlled power saving modes is
blocked, when this pin is held on high level. A high level
during reset performs an automatic start of the watchdog
timer immediately after reset. When left unconnected this
pin is pulled high by a weak internal pull-up resistor.

*) I = Input

O = Output

Table 1
Pin Definitions and Functions (cont'd)

Symbol

Pin Number

I/O*)

Function

P-MQFP-80

Semiconductor Group

1997-07-01

C515C

VSSCLK

Ground (0 V) for on-chip oscillator
This pin is used for ground connection of the on-chip
oscillator circuit.

VCCCLK

Supply voltage for on-chip oscillator
This pin is used for power supply of the on-chip oscillator
circuit.

VCCE1
VCCE2

32
68

Supply voltage for I/O ports
These pins are used for power supply of the I/O ports
during normal, idle, and power-down mode.

VSSE1
VSSE2

35
70

Ground (0 V) for I/O ports
These pins are used for ground connections of the I/O
ports during normal, idle, and power-down mode.

VCC1

Supply voltage for internal logic
This pins is used for the power supply of the internal logic
circuits during normal, idle, and power down mode.

VSS1

Ground (0 V) for internal logic
This pin is used for the ground connection of the internal
logic circuits during normal, idle, and power down mode.

VCCEXT

Supply voltage for external access pins
This pin is used for power supply of the I/O ports and
control signals which are used during external accesses
(for Port 0, Port 2, ALE, PSEN, P3.6/WR, and P3.7/RD).

VSSEXT

Ground (0 V) for external access pins
This pin is used for the ground connection of the I/O ports
and control signals which are used during external
accesses (for Port 0, Port 2, ALE, PSEN, P3.6/WR, and
P3.7/RD).

N.C.

2, 71

Not connected
These pins should not be connected.

*) I = Input

O = Output

Table 1
Pin Definitions and Functions (cont'd)

Symbol

Pin Number

I/O*)

Function

P-MQFP-80

Semiconductor Group

1997-07-01

C515C

CPU

The C515C is efficient both as a controller and as an arithmetic processor. It has extensive facilities
for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program
memory results from an instruction set consisting of 44 % one-byte, 41 % two-byte, and 15% three-
byte instructions. With a 6 MHz crystal, 58% of the instructions are executed in 1

(

10 MHz :

600 ns).

Special Function Register PSW (Address D0H)

Reset Value : 00H

Bit

Function

Carry Flag
Used by arithmetic instruction.

Auxiliary Carry Flag
Used by instructions which execute BCD operations.

General Purpose Flag

RS1
RS0

Overflow Flag
Used by arithmetic instruction.

General Purpose Flag

Parity Flag
Set/cleared by hardware after each instruction to indicate an odd/even
number of "one" bits in the accumulator, i.e. even parity.

RS1

RS0

D0H

PSW

D7H

D6H

D5H

D4H

D3H

D2H

D1H

D0H

Bit No.

MSB

LSB

RS1

RS0

Function

Bank 0 selected, data address 00H-07H

Bank 1 selected, data address 08H-0FH

Bank 2 selected, data address 10H-17H

Bank 3 selected, data address 18H-1FH

Semiconductor Group

1997-07-01

C515C

Control of XRAM/CAN Controller Access

The XRAM in the C515C is a memory area that is logically located at the upper end of the external
memory space, but is integrated on the chip. Because the XRAM and the CAN controller is used in
the same way as external data memory the same instruction types (MOVX) must be used for
accessing the XRAM. Two bits in SFR SYSCON, XMAP0 and XMAP1, control the accesses to the
XRAM and the CAN controller.

Special Function Register SYSCON (Address B1H)

Reset Value : X010XX01B

Bit XMAP0 is hardware protected. If it is reset once (XRAM/CAN controller access enabled) it
cannot be set by software. Only a reset operation will set the XMAP0 bit again.

The XRAM/CAN controller can be accessed by read/write instructions (MOVX A,DPTR, MOVX
@DPTR,A), which use the 16-bit DPTR for indirect addressing. For accessing the XRAM or CAN
controller, the effective address stored in DPTR must be in the range of F700H to FFFFH.
The XRAM can be also accessed by read/write instructions (MOVX A,@Ri, MOVX @Ri,A), which
use only an 8-bit address (indirect addressing with registers R0 or R1). Therefore, a special page
register XPAGE which provides the upper address information (A8-A15) during 8-bit XRAM
accesses. The behaviour of Port 0 and P2 during a MOVX access depends on the control bits
XMAP0 and XMAP1 in register SYSCON and on the state of pin EA. Table 2 lists the various
operating conditions.

Bit

Function

XMAP1

XRAM/CAN controller visible access control
Control bit for RD/WR signals during XRAM/CAN Controller accesses. If
addresses are outside the XRAM/CAN controller address range or if
XRAM is disabled, this bit has no effect.
XMAP1 = 0 : The signals RD and WR are not activated during accesses to

the XRAM/CAN Controller

XMAP1 = 1 : Ports 0, 2 and the signals RD and WR are activated during

accesses to XRAM/CAN Controller. In this mode, address
and data information during XRAM/CAN Controller accesses
are visible externally.

XMAP0

Global XRAM/CAN controller access enable/disable control
XMAP0 = 0 : The access to XRAM and CAN controller is enabled.
XMAP0 = 1 : The access to XRAM and CAN controller is disabled (default

after reset). All MOVX accesses are performed via the
external bus. Further, this bit is hardware protected.

EALE

RMAP

B1H

SYSCON

Bit No.

MSB

LSB

XMAP1

PMOD

XMAP0

The function of the shaded bits is not described in this section.

C515C

Semiconductor Group

1997-07-01

Table 2
Behaviour of P0/P2 and RD/WR During MOVX Accesses

EA = 0

EA = 1

XMAP1, XMAP0

MOVX
@DPTR

DPTR
<
XRAM/CAN
address
range

a)P0/P2

Bus

b)RD/WR active
c)ext.memory
is used

a)P0/P2

Bus

b)RD/WR active
c)ext.memory
is used

a)P0/P2

Bus

b)RD/WR active
c)ext.memory
is used

a)P0/P2

Bus

b)RD/WR active
c)ext.memory
is used

a)P0/P2

Bus

b)RD/WR active
c)ext.memory
is used

a)P0/P2

Bus

b)RD/WR active
c)ext.memory
is used

DPTR

XRAMCAN
address
range

a)P0/P2

Bus

(RD/WR-Data)
b)RD/WR
inactive
c)XRAM is used

a)P0/P2

Bus

(RD/WR-Data)
b)RD/WR active
c)XRAM is used

a)P0/P2

Bus

b)RD/WR active
c) ext.memory
is used

a)P0/P2

I/0

b)RD/WR
inactive
c)XRAM is used

a)P0/P2

Bus

(RD/WR-Data)
b)RD/WR active
c)XRAM is used

a)P0/P2

Bus

b)RD/WR active
c) ext.memory
is used

MOVX
@ Ri

XPAGE
<
XRAMCAN
addr.page
range

a)P0

Bus

b)RD/WR active
c)ext.memory
is used

a)P0

Bus

b)RD/WR active
c)ext.memory
is used

a)P0

Bus

b)RD/WR active
c)ext.memory
is used

a)P0

Bus

b)RD/WR active
c)ext.memory
is used

a)P0

Bus

b)RD/WR active
c)ext.memory
is used

a)P0

Bus

b)RD/WR active
c)ext.memory
is used

XPAGE

XRAMCAN
addr.page
range

a)P0

Bus

(RD/WR-Data)
P2

b)RD/WR
inactive
c)XRAM is used

a)P0

Bus

(RD/WR-Data
only)
P2

b)RD/WR active

c)XRAM is used

a)P0

Bus

b)RD/WR active

c)ext.memory
is used

a)P2

P0/P2

b)RD/WR
inactive
c)XRAM is used

a)P0

Bus

(RD/WR-Data)
P2

b)RD/WR active

c)XRAM is used

a)P0

Bus

b)RD/WR active

c)ext.memory
is used

modes compatible to 8051/C501 family

Semiconductor Group

1997-07-01

C515C

Reset and System Clock

The reset input is an active low input at pin RESET. Since the reset is synchronized internally, the
RESET pin must be held low for at least two machine cycles (12 oscillator periods) while the
oscillator is running. A pullup resistor is internally connected to

to allow a power-up reset with

an external capacitor only. An automatic reset can be obtained when

is applied by connecting

the RESET pin to

via a capacitor. Figure 6 shows the possible reset circuitries.

Figure 6
Reset Circuitries

Figure 7 shows the recommended oscillator circiutries for crystal and external clock operation.

Figure 7
Recommended Oscillator Circuitries

C515C

Semiconductor Group

1997-07-01

Multiple Datapointers

As a functional enhancement to the standard 8051 architecture, the C515C contains eight 16-bit
datapointers instead of only one datapointer. The instruction set uses just one of these datapointers
at a time. The selection of the actual datapointer is done in the special function register DPSEL.
Figure 8 illustrates the datapointer addressing mechanism.

Figure 8
External Data Memory Addressing using Multiple Datapointers

DPH(83 )

DPL(82 )

DPTR0

DPTR7

DPSEL(92 )

DPSEL

Selected

Data-

pointer

DPTR 0

DPTR 1

DPTR 2

DPTR 3

DPTR 4

DPTR 5

DPTR 6

DPTR 7

MCD00779

External Data Memory

Semiconductor Group

1997-07-01

C515C

Enhanced Hooks Emulation Concept

The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative
way to control the execution of C500 MCUs and to gain extensive information on the internal
operation of the controllers. Emulation of on-chip ROM based programs is possible, too.

Each production chip has built-in logic for the supprt of the Enhanced Hooks Emulation Concept.
Therefore, no costly bond-out chips are necessary for emulation. This also ensure that emulation
and production chips are identical.

The Enhanced Hooks Technology

, which requires embedded logic in the C500 allows the C500

together with an EH-IC to function similar to a bond-out chip. This simplifies the design and reduces
costs of an ICE-system. ICE-systems using an EH-IC and a compatible C500 are able to emulate
all operating modes of the different versions of the C500 microcontrollers. This includes emulation
of ROM, ROM with code rollover and ROMless modes of operation. It is also able to operate in
single step mode and to read the SFRs after a break.

Figure 9
Basic C500 MCU Enhanced Hooks Concept Configuration

Port 0, port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks
Emulation Concept to control the operation of the device during emulation and to transfer
informations about the programm execution and data transfer between the external emulation
hardware (ICE-system) and the C500 MCU.

MCS03280

SYSCON

PCON
TCON

RESET

PSEN

ALE

Port

I/O Ports

Optional

Port 3

Port 1

C500

MCU

Interface Circuit

Enhanced Hooks

RPort 0

RPort 2

RTCON

RPCON

RSYSCON

TEA

TALE TPSEN

EH-IC

Target System Interface

ICE-System Interface

to Emulation Hardware

C515C

Semiconductor Group

1997-07-01

Special Function Registers

The registers, except the program counter and the four general purpose register banks, reside in
the special function register area. The special function register area consists of two portions : the
standard special function register area and the mapped special function register area. Two special
function registers of the C515C (PCON1 and DIR5) are located in the mapped special function
register area. For accessing the mapped special function register area, bit RMAP in special function
register SYSCON must be set. All other special function registers are located in the standard
special function register area which is accessed when RMAP is cleared ("0"). As long as bit RMAP
is set, mapped special function register area can be accessed. This bit is not cleared by hardware
automatically. Thus, when non-mapped/mapped registers are to be accessed, the bit RMAP must
be cleared/set by software, respectively each.

Special Function Register SYSCON (Address B1H)

Reset Value : 1010XX01B

The 59 special function registers (SFRs) in the standard and mapped SFR area include pointers
and registers that provide an interface between the CPU and the other on-chip peripherals. The
SFRs of the C515C are listed in table 3 and table 4. In table 3 they are organized in groups which
refer to the functional blocks of the C515C. The CAN-SFRs are also included in table 3. Table 4
illustrates the contents of the SFRs in numeric order of their addresses. Table 5 list the CAN-SFRs
in numeric order of their addresses.

Bit

Function

RMAP

Special function register map bit
RMAP = 0 : The access to the non-mapped (standard) special function

RMAP = 1 : The access to the mapped special function register area is

enabled.

RMAP

B1H

SYSCON

Bit No.

MSB

LSB

XMAP1

CLKP

PMOD

XMAP0

Semiconductor Group

1997-07-01

C515C

Table 3
Special Function Registers - Functional Blocks

Block

Symbol

Name

Address

Contents after
Reset

CPU

ACC
B
DPH
DPL
DPSEL
PSW
SP
SYSCON

Accumulator
B-Register
Data Pointer, High Byte
Data Pointer, Low Byte
Data Pointer Select Register
Program Status Word Register
Stack Pointer
System Control Register

E0H

F0H

83H
82H
92H
D0H

81H
B1H

00H
00H
00H
00H
XXXXX000B

00H
07H
X010XX01B

A/D-
Converter

ADCON0

ADCON1
ADDATH
ADDATL

A/D Converter Control Register 0
A/D Converter Control Register 1
A/D Converter Data Register High Byte
A/D Converter Data Register Low Byte

D8H

DCH
D9H
DAH

00H
0XXXX000B

00H
00XXXXXXB

Interrupt
System

IEN0

IEN1

IEN2
IP0

IP1
TCON

T2CON

SCON

IRCON

Interrupt Enable Register 0
Interrupt Enable Register 1
Interrupt Enable Register 2
Interrupt Priority Register 0
Interrupt Priority Register 1
Timer Control Register
Timer 2 Control Register
Serial Channel Control Register
Interrupt Request Control Register

A8H

B8H

9AH
A9H
B9H
88H

C8H

98H

C0H

00H
00H
XX00X00XB

00H
0X000000B

00H
00H
00H
00H

XRAM

XPAGE

SYSCON

Page Address Register for Extended on-chip
XRAM and CAN Controller
System Control Register

91H

B1H

00H

X010XX01B

Ports

P0
P1
P2
P3
P4
P5
DIR5
P6
P7
SYSCON

Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 5 Direction Register
Port 6, Analog/Digital Input
Port 7
System Control Register

80H

90H

A0H

B0H

E8H

F8H

1) 4)

DBH
FAH
B1H

FFH
FFH
FFH
FFH
FFH
FFH
FFH

XXXXXXX1B

X010XX01B

1) Bit-addressable special function registers
2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.
3) "X" means that the value is undefined and the location is reserved
4) This SFR is a mapped SFR. For accessing this SFR, bit PDIR in SFR IP1 must be set.

C515C

Semiconductor Group

1997-07-01

Serial
Channel

ADCON0

PCON

SBUF
SCON
SRELL
SRELH

A/D Converter Control Register 0
Power Control Register
Serial Channel Buffer Register
Serial Channel Control Register
Serial Channel Reload Register, low byte
Serial Channel Reload Register, high byte

D8H

87H
99H
98H

AAH
BAH

00H
00H
XXH

00H
D9H
XXXXXX11B

CAN
Controller

CR
SR
IR
BTR0
BTR1
GMS0
GMS1
UGML0
UGML1
LGML0
LGML1
UMLM0
UMLM1
LMLM0
LMLM1

MCR0
MCR1
UAR0
UAR1
LAR0
LAR1
MCFG
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7

Control Register
Status Register
Interrupt Register
Bit Timing Register Low
Bit Timing Register High
Global Mask Short Register Low
Global Mask Short Register High
Upper Global Mask Long Register Low
Upper Global Mask Long Register High
Lower Global Mask Long Register Low
Lower Global Mask Long Register High
Upper Mask of Last Message Register Low
Upper Mask of Last Message Register High
Lower Mask of Last Message Register Low
Lower Mask of Last Message Register High
Message Object Registers :
Message Control Register Low
Message Control Register High
Upper Arbitration Register Low
Upper Arbitration Register High
Lower Arbitration Register Low
Lower Arbitration Register High
Message Configuration Register
Message Data Byte 0
Message Data Byte 1
Message Data Byte 2
Message Data Byte 3
Message Data Byte 4
Message Data Byte 5
Message Data Byte 6
Message Data Byte 7

F700H
F701H
F702H
F704H
F705H
F706H
F707H
F708H
F709H
F70AH
F70BH
F70CH
F70DH
F70EH
F70FH

F7n0H

F7n1H

F7n2H

F7n3H

F7n4H

F7n5H

F7n6H

F7n7H

F7n8H

F7n9H

F7nAH

F7nBH

F7nCH

F7nDH

F7nEH

01H
XXH

XXH

UUH

0UUUUUUU

UUH

UUU11111

UUH

UUUUU000

UUH

UUUUU000

UUH

UUUUU000

UUUUUU00

XXH

a reset operation. "U" values are undefined (as "X") after a power-on reset operation

4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.
5) The notation "n" in the message object address definition defines the number of the related message object.

Table 3
Special Function Registers - Functional Blocks (cont'd)

Block

Symbol

Name

Address

Contents after
Reset

Semiconductor Group

1997-07-01

C515C

SSC
Interface

SSCCON
STB
SRB
SCF
SCIEN
SSCMOD

SSC Control Register
SSC Transmit Buffer
SSC Receive Register
SSC Flag Register
SSC Interrupt Enable Register
SSC Mode Test Register

93H

)

94H
95H
ABH

)

ACH
96H

07H
XXH

)

XXH

)

XXXXXX00B

00H

Timer 0/
Timer 1

TCON
TH0
TH1
TL0
TL1
TMOD

Timer 0/1 Control Register
Timer 0, High Byte
Timer 1, High Byte
Timer 0, Low Byte
Timer 1, Low Byte
Timer Mode Register

88H

8CH
8DH
8AH
8BH
89H

00H
00H
00H
00H
00H
00H

Compare/
Capture
Unit /
Timer 2

CCEN
CCH1
CCH2
CCH3
CCL1
CCL2
CCL3
CRCH
CRCL
TH2
TL2
T2CON

Comp./Capture Enable Reg.
Comp./Capture Reg. 1, High Byte
Comp./Capture Reg. 2, High Byte
Comp./Capture Reg. 3, High Byte
Comp./Capture Reg. 1, Low Byte
Comp./Capture Reg. 2, Low Byte
Comp./Capture Reg. 3, Low Byte
Com./Rel./Capt. Reg. High Byte
Com./Rel./Capt. Reg. Low Byte
Timer 2, High Byte
Timer 2, Low Byte
Timer 2 Control Register

C1H
C3H
C5H
C7H
C2H
C4H
C6H
CBH
CAH
CDH
CCH
C8H

00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H

Watchdog WDTREL

IEN0

IEN1

IP0

Watchdog Timer Reload Register
Interrupt Enable Register 0
Interrupt Enable Register 1
Interrupt Priority Register 0

86H
A8H

B8H

A9H

00H
00H
00H
00H

Power
Save
Modes

PCON

PCON1

Power Control Register
Power Control Register 1

87H
88H

00H
0XXXXXXXB

1) Bit-addressable special function registers
2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.
3) "X" means that the value is undefined and the location is reserved
4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.

Table 3
Special Function Registers - Functional Blocks (cont'd)

Block

Symbol

Name

Address

Contents after
Reset

C515C

Semiconductor Group

1997-07-01

Table 4
Contents of the SFRs, SFRs in numeric order of their addresses

Addr Register Content

after
Reset

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

80H

FFH

81H SP

07H

82H DPL

00H

83H DPH

00H

86H WDTREL 00H

WDT
PSEL

87H PCON

00H

SMOD PDS

IDLS

GF1

GF0

PDE

IDLE

88H

TCON

00H

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

88H

PCON1

0XXX-
XXXXB

EWPD

89H TMOD

00H

GATE

C/T

GATE

C/T

8AH TL0

00H

8BH TL1

00H

8CH TH0

00H

8DH TH1

00H

90H

FFH

CLK-
OUT

T2EX

INT2

INT6

INT5

INT4

INT3

91H XPAGE

00H

92H DPSEL

XXXX-
X000B

93H

SSCCON

07H

SCEN

TEN

MSTR

CPOL

CPHA

BRS2

BRS1

BRS0

94H STB

XXH

95H SRB

XXH

96H

SSCMOD

00H

LOOPB

TRIO

LSBSM

98H

SCON

00H

SM0

SM1

SM2

REN

TB8

RB8

99H SBUF

XXH

9AH IEN2

X00X-
X00XB

EX8

EX7

ESSC

ECAN

A0H

FFH

A8H

IEN0

00H

WDT

ET2

ET1

EX1

ET0

EX0

1) X means that the value is undefined and the location is reserved
2) Bit-addressable special function registers
3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.

Semiconductor Group

1997-07-01

C515C

A9H IP0

00H

OWDS WDTS

AAH SRELL

D9H

ABH SCF

XXXX-
XX00B

WCOL TC

ACH SCIEN

XXXX-
XX00B

WCEN TCEN

B0H

FFH

INT1

INT0

TxD

RxD

B1H SYSCON X010-

XX01B

PMOD EALE

RMAP

XMAP1 XMAP0

B8H

IEN1

00H

EXEN2 SWDT

EX6

EX5

EX4

EX3

EX2

EADC

B9H IP1

0X00-
0000B

PDIR

BAH SRELH

XXXX-
XX11B

C0H

IRCON

00H

EXF2

TF2

IEX6

IEX5

IEX4

IEX3

IEX2

IADC

C1H CCEN

00H

COCA
H3

COCAL
3

COCA
H2

COCAL
2

COCA
H1

COCAL
1

COCA
H0

COCAL
0

C2H CCL1

00H

C3H CCH1

00H

C4H CCL2

00H

C5H CCH2

00H

C6H CCL3

00H

C7H CCH3

00H

C8H

T2CON

00H

T2PS

I3FR

I2FR

T2R1

T2R0

T2CM

T2I1

T2I0

CAH CRCL

00H

CBH CRCH

00H

CCH TL2

00H

CDH TH2

00H

1) X means that the value is undefined and the location is reserved
2) Bit-addressable special function registers

Table 4
Contents of the SFRs, SFRs in numeric order of their addresses (cont'd)

Addr Register Content

after
Reset

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

C515C

Semiconductor Group

1997-07-01

D0H

PSW

00H

RS1

RS0

D8H

ADCON0 00H

CLK

ADEX

BSY

ADM

MX2

MX1

MX0

D9H ADDATH 00H

DAH ADDATL 00XX-

XXXXB

DBH P6

DCH ADCON1 0XXX-

X000B

ADCL

MX2

MX1

MX0

E0H

ACC

00H

E8H

00H

RXDC

TXDC

INT8

SLS

STO

SRI

SCLK

ADST

F0H

00H

F8H

FFH

F8H

DIR5

FFH

FAH P7

XXXX-
XXX1B

1) X means that the value is undefined and the location is reserved
2) Bit-addressable special function registers
3) This SFR is a mapped SFR. For accessing this SFR, bit PDIR in SFR IP1 must be set.

Table 4
Contents of the SFRs, SFRs in numeric order of their addresses (cont'd)

Addr Register Content

after
Reset

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Semiconductor Group

1997-07-01

C515C

Table 5
Contents of the CAN Registers in numeric order of their addresses

Addr.
n=1-FH

Register Content

after
Reset

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

F700H CR

01H

TEST

CCE

EIE

SIE

INIT

F701H SR

XXH

BOFF

EWRN

RXOK TXOK

LEC2

LEC1

LEC0

F702H IR

XXH

INTID

F704H BTR0

UUH

SJW

BRP

F705H BTR1

0UUU.
UUUUB

TSEG2

TSEG1

F706H GMS0

UUH

ID28-21

F707H GMS1

UUU1.
1111B

ID20-18

F708H UGML0

UUH

ID28-21

F709H UGML1

UUH

ID20-13

F70AH LGML0

UUH

ID12-5

F70BH LGML1

UUUU.
U000B

ID4-0

F70CH UMLM0

UUH

ID28-21

F70DH UMLM1

UUH

ID20-18

ID17-13

F70EH LMLM0

UUH

ID12-5

F70FH LMLM1

UUUU.
U000B

ID4-0

F7n0H MCR0

UUH

MSGVAL

TXIE

RXIE

INTPND

F7n1H MCR1

UUH

RMTPND

TXRQ

MSGLST

CPUUPD

NEWDAT

F7n2H UAR0

UUH

ID28-21

F7n3H UAR1

UUH

ID20-18

ID17-13

F7n4H LAR0

UUH

ID12-5

F7n5H LAR1

UUUU.
U000B

ID4-0

F7n6H MCFG

UUUU.
UU00B

DLC

DIR

XTD

1) The notation "n" in the address definition defines the number of the related message object.
2) "X" means that the value is undefined and the location is reserved. "U" means that the value is unchanged

by a reset operation. "U" values are undefined (as "X") after a power-on reset operation

C515C

Semiconductor Group

1997-07-01

F7n7H DB0

XXH

F7n8H DB1

XXH

F7n9H DB2

XXH

F7nAH DB3

XXH

F7nBH DB4

XXH

F7nCH DB5

XXH

F7nDH DB6

XXH

F7nEH DB7

XXH

by a reset operation. "U" values are undefined (as "X") after a power-on reset operation

Table 5
Contents of the CAN Registers in numeric order of their addresses (cont'd)

Addr.
n=1-FH

Register Content

after
Reset

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Semiconductor Group

1997-07-01

C515C

Digital I/O Ports

The C515C allows for digital I/O on 49 lines grouped into 6 bidirectional 8-bit ports and one 1-bit
port. Each port bit consists of a latch, an output driver and an input buffer. Read and write accesses
to the I/O ports P0 through P7 are performed via their corresponding special function registers P0
to P7. The port structure of port 5 of the C515C is especially designed to operate either as a quasi-
bidirectional port structure, compatible to the standard 8051-Family, or as a genuine bidirectional
port structure. This port operating mode can be selected by software (setting or clearing the bit
PMOD in the SFR SYSCON).

The output drivers of port 0 and 2 and the input buffers of port 0 are also used for accessing external
memory. In this application, port 0 outputs the low byte of the external memory address, time-
multiplexed with the byte being written or read. Port 2 outputs the high byte of the external memory
address when the address is 16 bits wide. Otherwise, the port 2 pins continue emitting the P2 SFR
contents.

Analog Input Ports

Ports 6 is available as input port only and provides two functions. When used as digital inputs, the
corresponding SFR P6 contains the digital value applied to the port 6 lines. When used for analog
inputs the desired analog channel is selected by a three-bit field in SFR ADCON0 or SFR ADCON1.
Of course, it makes no sense to output a value to these input-only ports by writing to the SFR P6.
This will have no effect.

lf a digital value is to be read, the voltage levels are to be held within the input voltage specifications
(

). Since P6 is not bit-addressable, all input lines of P6 are read at the same time by byte

instructions.

Nevertheless, it is possible to use port 6 simultaneously for analog and digital input. However, care
must be taken that all bits of P6 that have an undetermined value caused by their analog function
are masked.

C515C

Semiconductor Group

1997-07-01

Port Structure Selection of Port 5

After a reset operation of the C515C, the quasi-bidirectional 8051-compatible port structure is
selected. For selection of the bidirectional (CMOS) port 5 structure the bit PMOD of SFR SYSCON
must be set. Because each port 5 pin can be programmed as an input or an output, additionally,
after the selection of the bidirectional mode the direction register DIR5 of port 5 must be written.
This direction register is mapped to the port 5 register. This means, the port register address is
equal to its direction register address. Figure 10 illustrates the port- and direction register
configuration.

Figure 10
Port Register, Direction Register

Semiconductor Group

1997-07-01

C515C

Timer / Counter 0 and 1

Timer/Counter 0 and 1 can be used in four operating modes as listed in table 6 :

In the "timer" function (C/T = `0') the register is incremented every machine cycle. Therefore the
count rate is

OSC

/6.

In the "counter" function the register is incremented in response to a 1-to-0 transition at its
corresponding external input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a
falling edge the max. count rate is

OSC

/12. External inputs INT0 and INT1 (P3.2, P3.3) can be

programmed to function as a gate to facilitate pulse width measurements. Figure 11 illustrates the
input clock logic

Figure 11
Timer/Counter 0 and 1 Input Clock Logic

Table 6
Timer/Counter 0 and 1 Operating Modes

Mode

Description

TMOD

Timer/Counter Input Clock

internal

external (max)

8-bit timer/counter with a
divide-by-32 prescaler

OSC

/6 x 32

OSC

/12 x 32

16-bit timer/counter

OSC

/12

8-bit timer/counter with
8-bit autoreload

Timer/counter 0 used as one
8-bit timer/counter and one
8-bit timer / Timer 1 stops

MCS03117

OSC

C/T = 0

C/T = 1

Control

TR1

P3.5/T1

(TMOD)

P3.2/INT0

Timer 0/1
Input Clock

OSC

P3.4/T0

TR0

Gate

P3.3/INT1

C515C

Semiconductor Group

1997-07-01

Timer/Counter 2 with Compare/Capture/Reload

The timer 2 of the C515C provides additional compare/capture/reload features. which allow the
selection of the following operating modes:

Compare

: up to 4 PWM signals with 16-bit/600 ns resolution

Capture

: up to 4 high speed capture inputs with 600 ns resolution

Reload

: modulation of timer 2 cycle time

The block diagram in figure 12 shows the general configuration of timer 2 with the additional
compare/capture/reload registers. The I/O pins which can used for timer 2 control are located as
multifunctional port functions at port 1.

Figure 12
Timer 2 Block Diagram

Semiconductor Group

1997-07-01

C515C

Timer 2 Operating Modes

The timer 2, which is a 16-bit-wide register, can operate as timer, event counter, or gated timer. A
roll-over of the count value in TL2/TH2 from all 1's to all 0's sets the timer overflow flag TF2 in SFR
IRCON, which can generate an interrupt. The bits in register T2CON are used to control the timer
2 operation.

Timer Mode : In timer function, the count rate is derived from the oscillator frequency. A prescaler
offers the possibility of selecting a count rate of 1/6 or 1/12 of the oscillator frequency.

Gated Timer Mode : In gated timer function, the external input pin T2 (P1.7) functions as a gate to
the input of timer 2. lf T2 is high, the internal clock input is gated to the timer. T2 = 0 stops the
counting procedure. This facilitates pulse width measurements. The external gate signal is sampled
once every machine cycle.

Event Counter Mode : In the event counter function. the timer 2 is incremented in response to a 1-
to-0 transition at its corresponding external input pin T2 (P1.7). In this function, the external input is
sampled every machine cycle. Since it takes two machine cycles (12 oscillator periods) to recognize
a 1-to-0 transition, the maximum count rate is 1/6 of the oscillator frequency. There are no
restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled
at least once before it changes, it must be held for at least one full machine cycle.

Reload of Timer 2 : Two reload modes are selectable:
In mode 0, when timer 2 rolls over from all 1's to all 0's, it not only sets TF2 but also causes the timer
2 registers to be loaded with the 16-bit value in the CRC register, which is preset by software.
In mode 1, a 16-bit reload from the CRC register is caused by a negative transition at the correspon-
ding input pin P1.5/T2EX. This transition will also set flag EXF2 if bit EXEN2 in SFR IEN1 has been
set.

C515C

Semiconductor Group

1997-07-01

Timer 2 Compare Modes

The compare function of a timer/register combination operates as follows : the 16-bit value stored
in a compare or compare/capture register is compared with the contents of the timer register; if the
count value in the timer register matches the stored value, an appropriate output signal is generated
at a corresponding port pin and an interrupt can be generated.

Compare Mode 0

In compare mode 0, upon matching the timer and compare register contents, the output signal
changes from low to high. lt goes back to a low level on timer overflow. As long as compare mode
0 is enabled, the appropriate output pin is controlled by the timer circuit only and writing to the port
will have no effect. Figure 13 shows a functional diagram of a port circuit when used in compare
mode 0. The port latch is directly controlled by the timer overflow and compare match signals. The
input line from the internal bus and the write-to-latch line of the port latch are disconnected when
compare mode 0 is enabled.

Figure 13
Port Latch in Compare Mode 0

MCS02661

Latch

Port

CLK

Port

Read Pin

Read Latch

Port Circuit

Internal
Bus

Latch

Write to

Compare Reg.

Compare Register

Circuit

Comparator

Timer Register

Timer Circuit

Compare
Match

Overflow

Timer

16 Bit

Bit

Semiconductor Group

1997-07-01

C515C

Compare Mode 1

If compare mode 1 is enabled and the software writes to the appropriate output latch at the port, the
new value will not appear at the output pin until the next compare match occurs. Thus, it can be
choosen whether the output signal has to make a new transition (1-to-0 or 0-to-1, depending on the
actual pin-level) or should keep its old value at the time when the timer value matches the stored
compare value.

In compare mode 1 (see figure 14) the port circuit consists of two separate latches. One latch
(which acts as a "shadow latch") can be written under software control, but its value will only be
transferred to the port latch (and thus to the port pin) when a compare match occurs.

Figure 14
Compare Function in Compare Mode 1

MCS02662

Latch

Port

CLK

Read Pin

CLK

Shadow

Latch

Read Latch

Port Circuit

Internal
Bus

Latch

Write to

Compare Reg.

Compare Register

Circuit

Comparator

Timer Register

Timer Circuit

Compare
Match

Port

16 Bit

C515C

Semiconductor Group

1997-07-01

Serial Interface (USART)

The serial port is full duplex and can operate in four modes (one synchronous mode, three
asynchronous modes) as illustrated in table 7.

For clarification some terms regarding the difference between "baud rate clock" and "baud rate"
should be mentioned. In the asynchronous modes the serial interfaces require a clock rate which is
16 times the baud rate for internal synchronization. Therefore, the baud rate generators/timers have
to provide a "baud rate clock" (output signal in figure 15 to the serial interface which - there divided
by 16 - results in the actual "baud rate". Further, the abrevation f

OSC

refers to the oscillator frequency

(crystal or external clock operation).

The variable baud rates for modes 1 and 3 of the serial interface can be derived either from timer 1
or from a decdicated baud rate generator (see figure 15).

Table 7
USART Operating Modes

Mode

SCON

Description

SM0

SM1

Shift register mode, fixed baud rate
Serial data enters and exits through R

D; T

D outputs the shift

clock; 8-bit are transmitted/received (LSB first)

8-bit UART, variable baud rate
10 bits are transmitted (through T

D) or received (at R

9-bit UART, fixed baud rate
11 bits are transmitted (through T

D) or received (at R

9-bit UART, variable baud rate
Like mode 2

Semiconductor Group

1997-07-01

C515C

Figure 15
Block Diagram of Baud Rate Generation for the Serial Interface

Table 8 below lists the values/formulas for the baud rate calculation of the serial interface with its
dependencies of the control bits BD and SMOD.

Table 8
Serial Interface - Baud Rate Dependencies

Serial Interface
Operating Modes

Active Control Bits Baud Rate Calculation

SMOD

Mode 0 (Shift Register)

OSC

/ 6

Mode 1 (8-bit UART)
Mode 3 (9-bit UART)

Controlled by timer 1 overflow :
(2

SMOD

timer 1 overflow rate) / 32

Controlled by baud rate generator
(2

SMOD

OSC

) /

(32

baud rate generator overflow rate)

Mode 2 (9-bit UART)

0
1

OSC

/ 32

OSC

/ 16

C515C

Semiconductor Group

1997-07-01

SSC Interface

The C515C microcontroller provides a Synchronous Serial Channel unit, the SSC. This interface is
compatible to the popular SPI serial bus interface. Figure 16 shows the block diagram of the SSC.
The central element of the SSC is an 8-bit shift register. The input and the output of this shift register
are each connected via a control logic to the pin P4.2 / SRI (SSC Receiver In) and P4.3 / STO (SSC
Transmitter Out). This shift register can be written to (SFR STB) and can be read through the
Receive Buffer Register SRB.

Figure 16
SSC Block Diagram

The SSC has implemented a clock control circuit, which can generate the clock via a baud rate
generator in the master mode, or receive the transfer clock in the slave mode. The clock signal is
fully programmable for clock polarity and phase. The pin used for the clock signal is P4.1/ SCLK.
When operating in slave mode, a slave select input is provided which enables the SSC interface
and also will control the transmitter output. The pin used for this is P4.4 / SLS.

The SSC control block is responsible for controlling the different modes and operation of the SSC,
checking the status, and generating the respective status and interrupt signals.

Semiconductor Group

1997-07-01

C515C

CAN Controller

The on-chip CAN controller is the functional heart which provides all resources that are required to
run the standard CAN protocol (11-bit identifiers) as well as the extended CAN protocol (29-bit
identifiers). It provides a sophisticated object layer to relieve the CPU of as much overhead as
possible when controlling many different message objects (up to 15). This includes bus arbitration,
resending of garbled messages, error handling, interrupt generation, etc. In order to implement the
physical layer, external components have to be connected to the C515C.

The internal bus interface connects the on-chip CAN controller to the internal bus of the
microcontroller. The registers and data locations of the CAN interface are mapped to a specific 256
byte wide address range of the external data memory area (F700H to F7FFH) and can be accessed
using MOVX instructions. Figure 17 shows a block diagram of the on-chip CAN controller.

Figure 17
CAN Controller Block Diagram

C515C

Semiconductor Group

1997-07-01

The TX/RX Shift Register holds the destuffed bit stream from the bus line to allow the parallel
access to the whole data or remote frame for the acceptance match test and the parallel transfer of
the frame to and from the Intelligent Memory.

The Bit Stream Processor (BSP) is a sequencer controlling the sequential data stream between
the TX/RX Shift Register, the CRC Register, and the bus line. The BSP also controls the EML and
the parallel data stream between the TX/RX Shift Register and the Intelligent Memory such that the
processes of reception, arbitration, transmission, and error signalling are performed according to
the CAN protocol. Note that the automatic retransmission of messages which have been corrupted
by noise or other external error conditions on the bus line is handled by the BSP.

The Cyclic Redundancy Check Register (CRC) generates the Cyclic Redundancy Check code to
be transmitted after the data bytes and checks the CRC code of incoming messages. This is done
by dividing the data stream by the code generator polynomial.

The Error Management Logic (EML) is responsible for the fault confinement of the CAN device. Its
counters, the Receive Error Counter and the Transmit Error Counter, are incremented and
decremented by commands from the Bit Stream Processor. According to the values of the error
counters, the CAN controller is set into the states error

active

, error

passive

and busoff.

The Bit Timing Logic (BTL) monitors the busline input RXDC and handles the busline related bit
timing according to the CAN protocol. The BTL synchronizes on a

recessive

dominant

busline

transition at

Start of Frame

(hard synchronization) and on any further

recessive

dominant

busline

transition, if the CAN controller itself does not transmit a

dominant

bit (resynchronization). The BTL

also provides programmable time segments to compensate for the propagation delay time and for
phase shifts and to define the position of the Sample Point in the bit time. The programming of the
BTL depends on the baudrate and on external physical delay times.

The Intelligent Memory (CAM/RAM array) provides storage for up to 15 message objects of
maximum 8 data bytes length. Each of these objects has a unique identifier and its own set of
control and status bits. After the initial configuration, the Intelligent Memory can handle the
reception and transmission of data without further microcontroller actions.

Semiconductor Group

1997-07-01

C515C

10-Bit A/D Converter

The C515C includes a high performance / high speed 10-bit A/D-Converter (ADC) with 8 analog
input channels. It operates with a successive approximation technique and uses self calibration
mechanisms for reduction and compensation of offset and linearity errors. The A/D converter
provides the following features:

8 multiplexed input channels (port 6), which can also be used as digital inputs
10-bit resolution
Single or continuous conversion mode
Internal or external start-of-conversion trigger capability
Interrupt request generation after each conversion
Using successive approximation conversion technique via a capacitor array
Built-in hidden calibration of offset and linearity errors

The main functional blocks of the A/D converter are shown in figure 19.

The A/D converter uses basically two clock signals for operation : the input clock f

(=1/t

) and the

conversion clock f

ADC

(=1/t

ADC

). These clock signals are derived from the C515C system clock

OSC

which is applied at the XTAL pins. The input clock f

is equal to f

OSC

. The conversion clock

is limited to a maximum frequency of 2 MHz and therefore must be adapted to f

OSC

programming the conversion clock prescaler. The table in figure 18 shows the prescaler ratios and
the resulting A/D conversion times which must be selected for typical system clock rates.

Figure 18
A/D Converter Clock Selection

MCU System Clock
Rate (f

OSC

)

ADCL

Conversion Clock
f

ADC

[MHz]

2 MHz

4 MHz

6 MHz

1.5

8 MHz

10 MHz

1.25

Semiconductor Group

1997-07-01

C515C

Interrupt System

The C515C provides 17 interrupt sources with four priority levels. Seven interrupts can be
generated by the on-chip peripherals (timer 0, timer 1, timer 2, serial interface, A/D converter, SSC
interface, CAN controller), and ten interrupts may be triggered externally (P1.5/T2EX, P3.2/INT0,
P3.3/INT1, P1.4/INT2, P1.0/INT3, P1.1/INT4, P1.2/INT5, P1.3/INT6, P7.0/INT7, P4.5/INT8). The
wake-up from power-down mode interrupt has a special functionality which allows to exit from the
software power-down mode by a short low pulse at pin P3.2/INT0.

In the C515C the 17 interrupt sources are combined to six groups of two or three interrupt sources.
Each interrupt group can be programmed to one of the four interrupt priority levels. Figure 20 to 22
give a general overview of the interrupt sources and illustrate the interrupt request and control flags.

Semiconductor Group

1997-07-01

C515C

Table 9
Interrupt Source and Vectors

Interrupt Source

Interrupt Vector Address

Interrupt Request Flags

External Interrupt 0

0003H

IE0

Timer 0 Overflow

000BH

TF0

External Interrupt 1

0013H

IE1

Timer 1 Overflow

001BH

TF1

Serial Channel

0023H

RI / TI

Timer 2 Overflow / Ext. Reload

002BH

TF2 / EXF2

A/D Converter

0043H

IADC

External Interrupt 2

004BH

IEX2

External Interrupt 3

0053H

IEX3

External Interrupt 4

005BH

IEX4

External Interrupt 5

0063H

IEX5

External Interrupt 6

006BH

IEX6

Wake-up from power-down mode

007BH

CAN controller

008BH

External Interrupt 7

00A3H

External Interrupt 8

00ABH

SSC interface

0093H

TC / WCOL

C515C

Semiconductor Group

1997-07-01

Fail Save Mechanisms

The C515C offers two on-chip peripherals which monitor the program flow and ensure an automatic
"fail-safe" reaction for cases where the controller's hardware fails or the software hangs up:

A programmable watchdog timer (WDT) with variable time-out period from 512 microseconds

up to approx. 1.1 seconds at 6 MHz.

An oscillator watchdog (OWD) which monitors the on-chip oscillator and forces the

microcontroller into reset state in case the on-chip oscillator fails; it also provides the clock for
a fast internal reset after power-on.

Programmable Watchdog Timer

The watchdog timer in the C515C is a 15-bit timer, which is incremented by a count rate of

OSC

/6 up

OSC

/192. For programming of the watchdog timer overflow rate, the upper 7 bit of the watchdog

timer can be written. Figure 23 shows the block diagram of the watchdog timer unit.

Figure 23
Block Diagram of the Programmable Watchdog Timer

The watchdog timer can be started by software (bit SWDT) or by hardware through pin PE/SWD,
but it cannot be stopped during active mode of the C515C. If the software fails to refresh the running
watchdog timer an internal reset will be initiated on watchdog timer overflow. For refreshing of the
watchdog timer the content of the SFR WDTREL is transfered to the upper 7-bit of the watchdog
timer. The refresh sequence consists of two consequtive instructions which set the bits WDT and
SWDT each. The reset cause (external reset or reset caused by the watchdog) can be examined
by software (flag WDTS). It must be noted, however, that the watchdog timer is halted during the
idle mode and power down mode of the processor.

Semiconductor Group

1997-07-01

C515C

Oscillator Watchdog

The oscillator watchdog unit serves for four functions:

Monitoring of the on-chip oscillator's function

The watchdog supervises the on-chip oscillator's frequency; if it is lower than the frequency
of the auxiliary RC oscillator in the watchdog unit, the internal clock is supplied by the RC
oscillator and the device is brought into reset; if the failure condition disappears (i.e. the on-
chip oscillator has a higher frequency than the RC oscillator), the part executes a final reset
phase of typ. 1 ms in order to allow the oscillator to stabilize; then the oscillator watchdog reset
is released and the part starts program execution again.

Fast internal reset after power-on

The oscillator watchdog unit provides a clock supply for the reset before the on-chip oscillator
has started. The oscillator watchdog unit also works identically to the monitoring function.

Restart from the hardware power down mode.

If the hardware power down mode is terminated the oscillator watchdog has to control the
correct start-up of the on-chip oscillator and to restart the program. The oscillator watchdog
function is only part of the complete hardware power down sequence; however, the watchdog
works identically to the monitoring function.

Control of external wake-up from software power-down mode

When the software power-down mode is left by a low level at the P3.2/INT0 pin, the oscillator
watchdog unit assures that the microcontroller resumes operation (execution of the power-
down wake-up interrupt) with the nominal clock rate. In the power-down mode the RC
oscillator and the on-chip oscillator are stopped. Both oscillators are started again when
power-down mode is released. When the on-chip oscillator has a higher frequency than the
RC oscillator, the microcontroller starts operation after a final delay of typ. 1 ms in order to
allow the on-chip oscillator to stabilize.

C515C

Semiconductor Group

1997-07-01

Figure 24
Block Diagram of the Oscillator Watchdog

Power Saving Modes

The C515C provides two basic power saving modes, the idle mode and the power down mode.
Additionally, a slow down mode is available. This power saving mode reduces the internal clock
rate in normal operating mode and it can be also used for further power reduction in idle mode.

Idle mode

The CPU is gated off from the oscillator. All peripherals are still provided with the clock and
are able to work. Idle mode is entered by software and can be left by an interrupt or reset.

Power down mode

The operation of the C515C is completely stopped and the oscillator is turned off. This mode
is used to save the contents of the internal RAM with a very low standby current.
Software power down mode : Software power down mode is entered by software and can
be left by reset or by a short low pulse at pin P3.2/INT0.
Hardware power down mode : Hardware power down mode is entered when the pin HWPD
is put to low level.

Semiconductor Group

1997-07-01

C515C

Slow-down mode

The controller keeps up the full operating functionality, but its normal clock frequency is
internally divided by 32. This slows down all parts of the controller, the CPU and all
peripherals, to 1/32-th of their normal operating frequency. Slowing down the frequency
significantly reduces power consumption. The slow down mode can be combined with the idle
mode.

Table 10 gives a general overview of the entry and exit conditions of the power saving modes.

In the power down mode of operation,

can be reduced to minimize power consumption. It must

be ensured, however, that

is not reduced before the power down mode is invoked, and that

is restored to its normal operating level, before the power down mode is terminated.

If e.g. the idle mode is left through an interrupt, the microcontroller state (CPU, ports, peripherals)
remains preserved. If a power saving mode is left by a hardware reset, the microcontroller state is
disturbed and replaced by the reset state of the C515C.

Table 10
Power Saving Modes Overview

Mode

Entering
(2-Instruction
Example

Leaving by

Remarks

Idle mode

ORL PCON, #01H
ORL PCON, #20H

Ocurrence of an
interrupt from a
peripheral unit

CPU clock is stopped;
CPU maintains their data;
peripheral units are active (if
enabled) and provided with
clock

Hardware Reset

Software
Power-Down Mode

ORL PCON, #02H
ORL PCON, #40H

Hardware Reset

Oscillator is stopped;
contents of on-chip RAM and
SFR's are maintained;

Short low pulse at
pin P3.2/INT0

Hardware
Power-Down Mode

HWPD = low

HWPD = high

C515C is put into its reset state
and the oscillator is stopped;
ports become floating outputs

Slow Down Mode

ORL PCON,#10H

ANL PCON,#0EFH
or
Hardware Reset

Oscillator frequency is reduced
to 1/32 of its nominal frequency

C515C

Semiconductor Group

1997-07-01

Absolute Maximum Ratings

Ambient temperature under bias (

) ......................................................... 40 to 110

Storage temperature (

stg

) .......................................................................... 65

C to 150

Voltage on

pins with respect to ground (

) ....................................... 0.5 V to 6.5 V

Voltage on any pin with respect to ground (

) ......................................... 0.5 V to

+0.5 V

Input current on any pin during overload condition..................................... 10 mA to 10 mA
Absolute sum of all input currents during overload condition ..................... I 100 mA I
Power dissipation........................................................................................ TBD

Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent

damage of the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for longer
periods may affect device reliability. During overload conditions (

) the

Voltage on

pins with respect to ground (

) must not exceed the values defined by the

absolute maximum ratings.

Semiconductor Group

1997-07-01

C515C

DC Characteristics

= 5 V + 10%, 15%;

= 0 V

= 0 to 70

for the SAB-C515C-8R

= 40 to 85

for the SAF-C515C-8R

= 40 to 110

for the SAH-C515C-8R

Parameter

Symbol

Limit Values

Unit

Test Condition

min.

max.

Input low voltages
all except EA, RESET, HWPD
EA pin
RESET and HWPD pins
Port 5 in CMOS mode

IL1

IL2

ILC

0.5
0.5
0.5
0.5

0.2

0.1

0.2

0.3

0.2

+ 0.1

0.3

V
V
V
V

Input high voltages
all except XTAL2, RESET, and
HWPD)
XTAL2 pin
RESET and HWPD pins
Port 5 in CMOS mode

IH1

IH2

IHC

0.2

+ 0.9

0.7

0.6

0.7

+ 0.5

V
V
V
V

Output low voltages
Ports 1, 2, 3, 4, 5, 7 (incl. CMOS)
Port 0, ALE, PSEN, CPUR
P4.1, P4.3 in push-pull mode

OL1

OL3

0.45
0.45
0.45

V
V
V

= 1.6 mA

= 3.2 mA

= 3.75 mA

Output high voltages
Ports 1, 2, 3, 4, 5, 7

Port 0 in external bus mode,
ALE, PSEN, CPUR
Port 5 in CMOS mode
P4.1, P4.3 in push-pull mode

OH2

OHC

OH3

2.4
0.9

0.9

V
V
V
V
V
V

= 80

= 10

)

= 800

= 80

= 800

= 833

Logic 0 input current
Ports 1, 2, 3, 4, 5, 7

= 0.45 V

Logical 0-to-1 transition current
Ports 1, 2, 3, 4, 5, 7

650

= 2 V

Input leakage current
Port 0, EA, P6, HWPD, AIN0-7

0.45 <

Input low current
To RESET for reset
XTAL2
PE/SWD

LI2

LI3

LI4

100
15
20

= 0.45 V

Pin capacitance

= 1 MHz,

= 25

Overload current

8) 9)

C515C

Semiconductor Group

1997-07-01

Power Supply Current

1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the

of ALE

and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these
pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise
pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a schmitt-trigger,
or use an address latch with a schmitt-trigger strobe input.

2) Capacitive loading on ports 0 and 2 may cause the

on ALE and PSEN to momentarily fall below the

0.9

specification when the address lines are stabilizing.

(power-down mode) is measured under following conditions:

EA = RESET = Port 0 = Port 6 =

; XTAL1 = N.C.; XTAL2 =

; PE/SWD =

;

HWPD =

;

AGND

;

AREF

; all other pins are disconnected.

(hardware power-down mode) is independent of any particular pin connection.

(active mode) is measured with:

XTAL2 driven with

CLCH

CHCL

= 5 ns ,

+ 0.5 V,

0.5 V; XTAL1 = N.C.;

EA = PE/SWD = Port 0 = Port 6 =

; HWPD =

;

RESET =

; all other pins are disconnected.

(idle mode) is measured with all output pins disconnected and with all peripherals disabled;

XTAL2 driven with

CLCH

CHCL

= 5 ns,

+ 0.5 V,

0.5 V; XTAL1 = N.C.;

RESET =

; EA =

; Port0 =

; all other pins are disconnected;

(active mode with slow-down mode) is measured : TBD

(idle mode with slow-down mode) is measured : TBD

8) Overload conditions occur if the standard operating conditions are exceeded, ie. the voltage on any pin

exceeds the specified range (i.e.

+ 0.5 V or

- 0.5 V). The supply voltage

and

must

remain within the specified limits. The absolute sum of input currents on all port pins may not exceed 50 mA.

9) Not 100% tested, guaranteed by design characterization

10)The typical

values are periodically measured at

= +25 °C and

= 5 V but not 100% tested.

11)The maximum

values are measured under worst case conditions (

= 0 °C or -40 °C and

= 5.5 V)

Parameter

Symbol

Limit Values

Unit Test Condition

typ.

10)

max.

11)

Active mode

6 MHz
10 MHz

12.0
18.9

16.1
25.5

mA
mA

Idle mode

6 MHz
10 MHz

6.9
10.5

9.8
15

mA
mA

Active mode with
slow-down enabled

6 MHz
10 MHz

TBD
TBD

mA
mA

Idle mode with
slow-down enabled

6 MHz
10 MHz

TBD
TBD

mA
mA

Power-down mode

TBD

= 2

...

5.5 V

Semiconductor Group

1997-07-01

C515C

Figure 25
ICC Diagram

Power Supply Current Calculation Formulas

Note :

osc

is the oscillator frequency in MHz.

values are given in mA.

Parameter

Symbol

Formula

Active mode

CC typ

CC max

1.72

OSC

+ 1.72

2.33

OSC

+ 2.15

Idle mode

CC typ

CC max

0.9

OSC

+ 1.5

1.3

OSC

+ 2.0

Active mode with
slow-down enabled

CC typ

CC max

TBD
TBD

Idle mode with
slow-down enabled

CC typ

CC max

TBD
TBD

OSC

MCD03313

MHz

Active Mode

Idle Mode

CC max

CC typ

C515C

Semiconductor Group

1997-07-01

A/D Converter Characteristics

= 5 V + 10%, 15%;

= 0 V

= 0 to 70

for the SAB-C515C-8R

= 40 to 85

for the SAF-C515C-8R

= 40 to 110

for the SAH-C515C-8R

4 V

AREF

+0.1 V ;

-0.1 V

AGND

+0.2 V

Notes see next page.

Clock calculation table :

Further timing conditions : t

ADC

min = 500 ns

= 1 / f

OSC

= t

CLP

Parameter

Symbol

Limit Values

Unit

Test Condition

min.

max.

Analog input voltage

AIN

AGND

AREF

Sample time

16 x

8 x

Prescaler

Conversion cycle time

ADCC

96 x

48 x

Prescaler

Total unadjusted error

LSB

Internal resistance of
reference voltage source

AREF

ADC

/ 250

- 0.25

ADC

in [ns]

5) 6)

Internal resistance of
analog source

ASRC

/ 500

- 0.25

in [ns]

2) 6)

ADC input capacitance

AIN

Clock Prescaler
Ratio

ADCL

ADC

ADCC

8 x t

16 x t

96 x t

4 x t

8 x t

48 x t

Semiconductor Group

1997-07-01

C515C

Notes:

1) V

AIN

may exeed V

AGND

or V

AREF

up to the absolute maximum ratings. However, the conversion result in

these cases will be X000

or X3FF

, respectively.

2) During the sample time the input capacitance

AIN

can be charged/discharged by the external source. The

internal resistance of the analog source must allow the capacitance to reach their final voltage level within t

After the end of the sample time t

, changes of the analog input voltage have no effect on the conversion

result.

3) This parameter includes the sample time t

, the time for determining the digital result and the time for the

calibration. Values for the conversion clock t

ADC

depend on programming and can be taken from the table on

the previous page.

4) T

is tested at V

AREF

= 5.0 V, V

AGND

= 0 V, V

= 4.9 V. It is guaranteed by design characterization for all

other voltages within the defined voltage range.
If an overload condition occurs on maximum 2 not selected analog input pins and the absolute sum of input
overload currents on all analog input pins does not exceed 10 mA, an additional conversion error of 1/2 LSB
is permissible.

5) During the conversion the ADC's capacitance must be repeatedly charged or discharged. The internal

resistance of the reference source must allow the capacitance to reach their final voltage level within the
indicated time. The maximum internal resistance results from the programmed conversion timing.

6) Not 100% tested, but guaranteed by design characterization.

C515C

Semiconductor Group

1997-07-01

AC Characteristics

= 5 V + 10%, 15%;

= 0 V

= 0 to 70

for the SAB-C515C-8R

= 40 to 85

for the SAF-C515C-8R

= 40 to 110

for the SAH-C515C-8R

(

for port 0, ALE and PSEN outputs = 100 pF;

for all other outputs = 80 pF)

Program Memory Characteristics

Interfacing the C515C to devices with float times up to 35 ns is permissible. This limited bus contention will not
cause any damage to port 0 drivers.

Parameter

Symbol

Limit Values

Unit

10-MHz clock

Duty Cycle

0.4 to 0.6

Variable Clock

1/CLP = 2 MHz to

10 MHz

min.

max.

min.

max.

ALE pulse width

LHLL

CLP - 40

Address setup to ALE

AVLL

TCL

Hmin

-25

Address hold after ALE

LLAX

TCL

Hmin

-25

ALE to valid instruction in

LLIV

113

2 CLP - 87

ALE to PSEN

LLPL

TCL

Lmin

-20

PSEN pulse width

PLPH

115

CLP+
TCL

Hmin

-30

PSEN to valid instruction in

PLIV

CLP+
TCL

Hmin

- 65

Input instruction hold after PSEN

PXIX

Input instruction float after PSEN

PXIZ

TCL

Lmin

-10

Address valid after PSEN

PXAV

TCL

Lmin

- 5

Address to valid instruction in

AVIV

180

2 CLP +
TCL

Hmin

-60

Address float to PSEN

AZPL

Semiconductor Group

1997-07-01

C515C

External Data Memory Characteristics

Parameter

Symbol

Limit Values

Unit

10-MHz

clock

Duty Cycle

0.4 to 0.6

Variable Clock

1/CLP= 2 MHz to 10 MHz

min.

max.

min.

max.

RD pulse width

RLRH

230

3 CLP - 70

WR pulse width

WLWH

230

3 CLP - 70

Address hold after ALE

LLAX2

CLP

- 15

RD to valid data in

RLDV

150

2 CLP+
TCL

Hmin

- 90

Data hold after RD

RHDX

Data float after RD

RHDZ

CLP - 20

ALE to valid data in

LLDV

267

4 CLP - 133

Address to valid data in

AVDV

285

4 CLP +
TCL

Hmin

-155

ALE to WR or RD

LLWL

190

CLP +
TCL

Lmin

- 50

CLP+
TCL

Lmin

+ 50

Address valid to WR

AVWL

103

2 CLP - 97

WR or RD high to ALE high

WHLH

TCL

Hmin

- 25

TCL

Hmin

+ 25

Data valid to WR transition

QVWX

TCL

Lmin

- 35

Data setup before WR

QVWH

218

3 CLP +
TCL

Lmin

- 122

Data hold after WR

WHQX

TCL

Hmin

- 27

Address float after RD

RLAZ

C515C

Semiconductor Group

1997-07-01

Note: The 10 MHz values in the tables are given as an example for a typical duty cycle variation of

the oscillator clock from 0.4 to 0.6.

SSC Interface Characteristics

Parameter

Symbol

Limit Values

Unit

min.

max.

Clock Cycle Time : Master Mode

Slave Mode

SCLK

0.4
1.0

Clock high time

SCH

360

Clock low time

SCL

360

Data output delay

100

Data output hold

Data input setup

100

Data input hold

100

TC bit set delay

DTC

8 CLP

External Clock Drive at XTAL2

Parameter

Symbol

CPU Clock = 10 MHz

Duty cycle 0.4 to 0.6

Variable CPU Clock

1/CLP = 2 to 10 MHz

Unit

min.

max.

min.

max.

Oscillator period

CLP

100

500

High time

TCL

CLP-TCL

Low time

TCL

CLP-TCL

Rise time

Fall time

Oscillator duty cycle

0.4

0.6

40 / CLP

1 - 40 / CLP

Clock cycle

TCL

CLP * DC

min

CLP * DC

max

Semiconductor Group

1997-07-01

C515C

Figure 30
SSC Timing

Notes : Shown is the data/clock relationship for CPOL=CPHA=1. The timing diagram is valid

for the other cases accordingly.

In the case of slave mode and CPHA=0, the output delay for the MSB applies to the
falling edge of SLS (if transmitter is enabled).

In the case of master mode and CPHA=0, the MSB becomes valid after the data has
been written into the shift register, i.e. at least one half SCLK clock cycle before the
first clock transition.

MCT02417

SCLK

STO

SRI

SCL

MSB

LSB

MSB

LSB

SCH

SCLK

~ ~

DTC

C515C

Semiconductor Group

1997-07-01

Figure 33
AC Testing: Input, Output Waveforms

Figure 34
AC Testing : Float Waveforms

Figure 35
Recommended Oscillator Circuits for Crystal Oscillator

AC Inputs during testing are driven at

- 0.5 V for a logic '1' and 0.45 V for a logic '0'.

Timing measurements are made at

IHmin

for a logic '1' and

ILmax

for a logic '0'.

0.45 V

0.2

-0.1

+0.9

0.2

Test Points

MCT00039

-0.5 V

For timing purposes a port pin is no longer floating when a 100 mV change from load voltage
occurs and begins to float when a 100 mV change from the loaded

level occurs.

20 mA

MCT00038

Load

-0.1 V

+0.1 V

Load

Timing Reference

Points

-0.1 V

+0.1 V

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