Edition 1997-10-01
Published by

Siemens AG,

Bereich Halbleiter, Marketing-
Kommunikation, Balanstraße 73,
81541 München

Siemens AG 1997.

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C540U/C541U Data Sheet
Revision History :

1997-10-01

Previous Releases :

none (Original Version)

Page / Chapters

Subjects (changes since last revision)

Semiconductor Group

1997-10-01

8-Bit CMOS Microcontroller

Advance Information

C540U
C541U

Enhanced 8-bit C500 CPU
Full software/toolset compatible to standard 80C51/80C52 microcontrollers

12 MHz external operating frequency
500 ns instruction cycle

Built-in PLL for USB synchronization

On-chip OTP program memory
C540U : 4K byte
C541U : 8K byte
Alternatively up to 64K byte external program memory
Optional memory protection

On-chip USB module
Compliant to USB specification
Full speed or low speed operation
Five endpoints : one bidirectional control endpoint

four versatile programmable endpoints

Registers are located in special function register area
On-chip USB transceiver

I/O

MCA03373

OTP Prog. Memory

RAM

CPU

I/O

256 x 8

C540U : 4 k x 8
C541U : 8 k x 8

Watchdog

Oscillator

Timer

Watchdog

SSC

USB

Module

USB Transceiver

Power

Saving
Modes

On-Chip Emulation Support Module

Port 3

Port 2

Port 1

Port 0

The shaded units are not available in the C540U.

D+

D-

Semiconductor Group

1997-10-01

C540U
C541U

Features (cont'd) :

Up to 64K byte external data memory

256 byte on-chip RAM

Four parallel I/O ports
P-LCC-44 package :

three 8-bit ports and one 6-bit port

P-SDIP-52 package : four 8-bit ports
LED current drive capability for 3 pins (10 mA)

Two 16-bit timer/counters (C501 compatible)

SSC synchronous serial interface (SPI compatible) (only C541U)
Master and slave capable
Programmable clock polarity / clock-edge to data phase relation
LSB/MSB first selectable
1.5 MBaud transfer rate at 12 MHz operating frequency

7 interrupt sources (2 external, 5 internal with 2 USB interrupts) selectable at 2 priority levels

Enhanced fail safe mechanisms
Programmable watchdog timer (only C541U)
Oscillator watchdog

Power saving modes
idle mode
software power down mode with wake-up capability through INT0 pin or USB

On-chip emulation support logic (Enhanced Hooks Technology

)

P-LCC-44 and P-SDIP-52 packages

Power supply voltage range : 4.0V to 5.5V

Temperature Range :

SAB-C540U

= 0 to 70

SAB-C541U

= 0 to 70

Table 1
Ordering Information

Type

Ordering Code

Package

Description
(8-Bit CMOS microcontroller)

SAB-C540U-EN

Q67126-C2042

P-LCC-44-2

8-Bit CMOS microcontroller (12 MHz)

SAB-C540U-EP

Q67120-C2043

P-SDIP-52-1

8-Bit CMOS microcontroller (12 MHz)

SAB-C541U-1EN

Q67126-C2001

P-LCC-44-2

8-Bit CMOS microcontroller (12 MHz)

SAB-C541U-1EP

Q67120-C2021

P-SDIP-52-1

8-Bit CMOS microcontroller (12 MHz)

Semiconductor Group

1997-10-01

C540U
C541U

Figure 2
Logic Symbol

Additional Literature

For further information about the C540U/C541U the following literature is available :

Title

Ordering Number

C540U/C541U 8-Bit CMOS Microcontroller User's Manual

B158-H????-X-X-7600

C500 Microcontroller Family
Architecture and Instruction Set User's Manual

B158-H6987-X-X-7600

C500 Microcontroller Family - Pocket Guide

B158-H6986-X-X-7600

PSEN

RESET

ALE

XTAL2

XTAL1

8-Bit Digital I / O

Port

P-LCC-44 : 6-Bit Digital I / O

8-Bit Digital I / O

Port

C540U

MCL03374

P-SDIP-52 : 8-Bit Digital I / O

C541U

D-

D+

Semiconductor Group

1997-10-01

C540U
C541U

Figure 3
Pin Configuration P-LCC-44 Package

(top view)

P1.2 / SCLK

P0.4 / AD4

P0.5 / AD5

P0.6 / AD6

P0.7 / AD7

1 44 43 42 41 40

18 19 20 21 22 23 24 25 26 27 28

P3.1 / DADD

P3.2 / INT0

P3.3 / INT1

P3.4 / T0

P3.5 / T1

P3.6 / WR

P3.7 / RD

XTAL2

XTAL1

P1.3 / SRI

P3.0 / LED2

RESET

P2.0 / A8

P2.1 / A9

P2.2 / A10

P2.3 / A11

P2.4 / A12

P2.5 / A13

P2.6 / A14

P2.7 / A15

PSEN

ALE

P1.4 / STO

C540U
C541U

MCP03343

P1.1 / LED1

P1.0 / LED0

D-

D+

SSU

CCU

P1.5 / SLS

P0.0 / AD0

P0.1 / AD1

P0.2 / AD2

P0.3 / AD3

This pin functionality ist not available for the C540U.

Semiconductor Group

1997-10-01

C540U
C541U

Figure 4
Pin Configuration P-SDIP-52 Package

(top view)

N.C.

P0.0 / AD0

P0.1 / AD1

P0.2 / AD2

P0.3 / AD3

P0.4 / AD4

P0.5 / AD5

P0.6 / AD6

P0.7 / AD7

P1.4 / STO

P1.7

ALE

PSEN

N.C.

P2.7 / A15

P2.6 / A14

P2.5 / A13

P2.4 / A12

P2.3 / A11

P2.2 / A10

P2.1 / A9

P2.0 / A8

N.C.

CCU

SSU

D+

D-

N.C.

P1.0 / LED0

P1.1 / LED1

P1.2 / SCLK

RESET

P3.0 / LED2

P1.3 / SRI

P1.6

P3.1 / DADD

P3.2 / INT0

P3.3 / INT1

P3.4 / T0

P3.5 / T1

P3.6 / WR

P3.7 / RD

XTAL2

XTAL1

MCP03344

This pin functionality ist not available for the C540U.

P1.5 / SLS

C540U
C541U

Semiconductor Group

1997-10-01

C540U
C541U

Table 2
Pin Definitions and Functions

Symbol

Pin Numbers

I/O*) Function

P-LCC-44

P-SDIP-52

D+

I/O

USB D+ Data Line

The pin D+ can be directly connected to USB cable
(transceiver is integrated on-chip).

D-

I/O

USB D- Data Line

The pin D- can be directly connected to USB cable
(transceiver is integrated on-chip).

P1.0 - P1.4

5 - 7,
12, 34, 44

5
6
7

12
34
44

7 - 9, 14, 41,
51, 15, 40

7
8
9

13
41
51
15
40

I/O

Port 1

is an 6-bit (P-LCC-44) or 8-bit (P-SDIP-52) quasi-
bidirectional I/O port with internal pullup resistors.
Port 1 pins that have 1's written to them are pulled
high by the internal pullup resistors, and in that
state can be used as inputs. As inputs, port 1 pins

being externally pulled low will source current (

in the DC characteristics) because of the internal
pullup resistors.
Port 1 also contains two outputs with LED drive
capability as well as the four pins of the SSC
(C541U only). The output latch corresponding to a
secondary function must be programmed to a one
(1) for that function to operate (except when used
for the compare functions). The secondary
functions are assigned to the port 1 pins as follows :
P1.0 / LED0 LED0 output
P1.1 / LED1 LED1 output
P1.2 / SCLK SSC Master Clock Output /

SSC Slave Clock Input (C541U only)

P1.3 / SRI

SSC Receive Input (C541U only)

P1.4 / STO

SSC Transmit Output (C541U only)

P1.5 / SLS

SSC Slave Select Inp. (C541U only)

P1.6 (P-SDIP-52

only)

P1.7

(P-SDIP-52 only)

RESET

RESET

A high level on this pin for the duration of two
machine cycles while the oscillator is running
resets the C540U/C541U. A small internal pulldown
resistor permits power-on reset using only a

capacitor connected to V

*) I = Input

O = Output

Semiconductor Group

1997-10-01

C540U
C541U

P3.0 - P3.7

11, 13 - 19 13, 16 - 22

I/O

Port 3

is an 8-bit quasi-bidirectional I/O port with internal
pullup resistors. Port 3 pins that have 1's written to
them are pulled high by the internal pullup resistors,
and in that state can be used as inputs. As inputs,
port 3 pins being externally pulled low will source
current (

, in the DC characteristics) because of

the internal pullup resistors. Port 3 also contains
the interrupt, timer, serial port and external memory
strobe pins that are used by various options. The
output latch corresponding to a secondary function
must be programmed to a one (1) for that function
to operate. The secondary functions are assigned
to the pins of port 3, as follows:
P3.0 / LED2

LED2 output

P3.1 / DADD

Device attached input

P3.2 / INT0

External interrupt 0 input /
timer 0 gate control input

P3.3 / INT1

External interrupt 1 input /
timer 1 gate control input

P3.4 / T0

Timer 0 counter input

P3.5 / T1

Timer 1 counter input

P3.6 / WR

WR control output; latches the
data byte from port 0 into the
external data memory

P3.7 / RD

RD control output; enables the
external data memory

XTAL2

XTAL2

is the output of the inverting oscillator amplifier.
This pin is used for the oscillator operation with
crystal or ceramic resonator.

XTAL1

XTAL1

is the input to the inverting oscillator amplifier and
input to the internal clock generator circuits.
To drive the device from an external clock source,
XTAL1 should be driven, while XTAL2 is left

unconnected.

Minimum and maximum high and

low times as well as rise/fall times specified in the
AC characteristics must be observed.

*) I = Input

O = Output

Table 2
Pin Definitions and Functions (cont'd)

Symbol

Pin Numbers

I/O*) Function

P-LCC-44

P-SDIP-52

Semiconductor Group

1997-10-01

C540U
C541U

P2.0 - P2.7

24 - 31

28 - 35

I/O

Port 2

is an 8-bit quasi-bidirectional I/O port with internal
pullup resistors. Port 2 pins that have 1's written to
them are pulled high by the internal pullup resistors,
and in that state can be used as inputs. As inputs,
port 2 pins being externally pulled low will source
current (

, in the DC characteristics) because of

the internal pullup resistors.
Port 2 emits the high-order address byte during
fetches from external program memory and during
accesses to external data memory that use 16-bit
addresses (MOVX @DPTR). In this application it
uses strong internal pullup resistors when issuing
1's. During accesses to external data memory that
use 8-bit addresses (MOVX @Ri), port 2 issues the
contents of the P2 special function register.

PSEN

The

Program Store Enable

output is a control signal that enables the external
program memory to the bus during external fetch
operations. It is activated every six oscillator
periods except during external data memory
accesses. The signal remains high during internal
program execution.

ALE

The

Address Latch enable

output is used for latching the address into external
memory during normal operation. It is activated
every six oscillator periods except during an
external data memory access.

External Access Enable

When held high, the C540U/C541U executes
instructions from the internal ROM as long as the

PC is less than 1000H for the C540U or less than
2000H for the C541U. When held low, the C540U/
C541U fetches all instructions from external
program memory. For the C540U-L/C541U-L this
pin must be tied low.

*) I = Input

O = Output

Table 2
Pin Definitions and Functions (cont'd)

Symbol

Pin Numbers

I/O*) Function

P-LCC-44

P-SDIP-52

Semiconductor Group

1997-10-01

C540U
C541U

P0.0 - P0.7

44 - 36

50 - 43

I/O

Port 0

is an 8-bit open-drain bidirectional I/O port. Port 0
pins that have 1's written to them float, and in that
state can be used as high-impedance inputs. Port 0
is also the multiplexed low-order address and data
bus during accesses to external program and data
memory. In this application it uses strong internal
pullup resistors when issuing 1's.

CCU

Supply voltage

for the on-chip USB transceiver circuitry.

SSU

Ground

(0V)

for the on-chip USB transceiver circuitry.

8, 23

10, 26

Supply voltage

for ports and internal logic circuitry during normal,
idle, and power down mode.

9, 22

11, 25

Ground

(0V)

for ports and internal logic circuitry during normal,
idle, and power down mode.

*) I = Input

O = Output

Table 2
Pin Definitions and Functions (cont'd)

Symbol

Pin Numbers

I/O*) Function

P-LCC-44

P-SDIP-52

Semiconductor Group

1997-10-01

C540U
C541U

Figure 5
Block Diagram of the C540U/C541U

XTAL2

Oscillator Watchdog

OSC & Timing

CPU

Progr. Watchdog

Timer (C541U only)

Timer 0

Timer 1

SSC (SPI) Interface

(C541U only)

PLL

Transceiver

USB

Module

Interrupt Unit

RAM

256 x 8

OTP Memory

4k x 8 (C540U)
8k x 8 (C541U)

Port 3

Port 2

Port 1

Port 0

Emulation

Support

Logic

C540U
C541U

Port 0
8-Bit Digit. I/O

Port 1
6- / 8-Bit Digit. I/O

Port 2
8-Bit Digit. I/O

Port 3
8-Bit Digit. I/O

XTAL1

ALE

RESET

PSEN

D+

D-

P-LCC-44 : 6-Bit Port; P-SDIP-52 : 8-Bit Port

MCB03345

Semiconductor Group

1997-10-01

C540U
C541U

CPU

The C540U/C541U is efficient both as a controller and as an arithmetic processor. It has extensive
facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of
program memory results from an instruction set consisting of 44 % one-byte, 41 % two-byte, and
15% three- byte instructions. With a 12 MHz crystal, 58% of the instructions are executed in 500ns.

Special Function Register PSW (Address D0H)

Reset Value : 00H

Bit

Function

Carry Flag
Used by arithmetic instruction.

Auxiliary Carry Flag
Used by instructions which execute BCD operations.

General Purpose Flag

RS1
RS0

Register Bank Select Control Bits
These bits are used to select one of the four register banks.

Overflow Flag
Used by arithmetic instruction.

General Purpose Flag

Parity Flag
Set/cleared by hardware after each instruction to indicate an odd/even
number of "one" bits in the accumulator, i.e. even parity.

RS1

RS0

D0H

PSW

D7H

D6H

D5H

D4H

D3H

D2H

D1H

D0H

Bit No.

MSB

LSB

RS1

RS0

Function

Bank 0 selected, data address 00H-07H

Bank 1 selected, data address 08H-0FH

Bank 2 selected, data address 10H-17H

Bank 3 selected, data address 18H-1FH

Semiconductor Group

1997-10-01

C540U
C541U

Memory Organization

The C540U/C541U CPU manipulates operands in the following four address spaces:

8 or 4 KByte on-chip OTP program memory
Totally up to 64 Kbyte internal/external program memory
up to 64 Kbyte of external data memory
256 bytes of internal data memory
a 128 byte special function register area

Figure 6 illustrates the memory address spaces of the C540U/C541U.

Figure 6
C540U/C541U Memory Map Memory Map

External

Internal

(EA = 1)

(EA = 0)

External

FFFF

2000 1)

1FFF 1)

0000

External

FFFF

0000

Function

Special

RAM

Internal

RAM

Internal

Addr.

Indirect

Addr.

Direct

"Code Space"

"External Data Space"

"Internal Data Space"

MCD03375

1) For the C504U the int. / ext. program memory boundary is at 0FFF / 1000 .

Semiconductor Group

1997-10-01

C540U
C541U

Reset and System Clock

The reset input is an active high input at pin RESET. Since the reset is synchronized internally, the
RESET pin must be held high for at least two machine cycles (12 oscillator periods) while the
oscillator is running. A pulldown resistor is internally connected to

to allow a power-up reset with

an external capacitor only. An automatic reset can be obtained when

is applied by connecting

the RESET pin to

via a capacitor. Figure 7 shows the possible reset circuitries.

Figure 7
Reset Circuitries

RESET

MCD03376

C540U

RESET

C541U

C540U

C541U

C540U

Semiconductor Group

1997-10-01

C540U
C541U

The oscillator and clock generation circuitry of the C540U/C541U is shown in figure 5-8. The crystal
oscillator generates the system clock for the microcontroller. The USB module can be provided with
the following clocks :

Full speed operation : 48 MHz with a data rate of 12 Mbit/s
Low speed operation : 6 MHz with a data rate of 1.5 Mbit/s

The low speed clock is generated by a dividing the system clock by 2. The full speed clock is
generated by a PLL, which multiplies the system clock by a fix factor of 4. This PLL can be enabled
or disabled by bit PCLK of SFR DCR. Depending on full or low speed operation of the USB bit
SPEED of SFR has to be set or cleared for the selection of the USB clock. Bit UCLK is a general
enable bit for the USB clock.

Figure 8
Block Diagram of the Clock Generation Circuitry

Crystal

Oscillator

XTAL1

12 MHz

6 MHz

Enable

PCLK

12 MHz

XTAL2

by 2

Divider

PLL

x 4

48 MHz

DCR.0

SPEED
DCR.7

UCLK
DCR.1

to USB

Module

System Clock
of the
Microcontroler

C540U / C541U

1
0

MCB03377

Semiconductor Group

1997-10-01

C540U
C541U

Enhanced Hooks Emulation Concept

The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative
way to control the execution of C500 MCUs and to gain extensive information on the internal
operation of the controllers. Emulation of on-chip ROM based programs is possible, too.

Each production chip has built-in logic for the supprt of the Enhanced Hooks Emulation Concept.
Therefore, no costly bond-out chips are necessary for emulation. This also ensure that emulation
and production chips are identical.

The Enhanced Hooks Technology

, which requires embedded logic in the C500 allows the C500

together with an EH-IC to function similar to a bond-out chip. This simplifies the design and reduces
costs of an ICE-system. ICE-systems using an EH-IC and a compatible C500 are able to emulate
all operating modes of the different versions of the C500 microcontrollers. This includes emulation
of ROM, ROM with code rollover and ROMless modes of operation. It is also able to operate in
single step mode and to read the SFRs after a break.

Figure 10
Basic C500 MCU Enhanced Hooks Concept Configuration

Port 0, port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks
Emulation Concept to control the operation of the device during emulation and to transfer
informations about the programm execution and data transfer between the external emulation
hardware (ICE-system) and the C500 MCU.

1 "Enhanced Hooks Technology" is a trademark and patent of Metalink Corporation licensed to Siemens.

MCS02647

SYSCON

PCON
TCON

RESET

PSEN

ALE

Port 0

Port 2

I/O Ports

Optional

Port 3

Port 1

C500

MCU

Interface Circuit

Enhanced Hooks

RPort 0

RPort 2

RTCON

RPCON

RSYSCON

TEA

TALE TPSEN

EH-IC

Target System Interface

ICE-System Interface

to Emulation Hardware

Semiconductor Group

1997-10-01

C540U
C541U

Special Function Registers

The registers, except the program counter and the four general purpose register banks, reside in
the special function register area. The special function register area consists of two portions: the
standard special function register area and the mapped special function register area. One special
function register of the C540U/C541U (PCON1) is located in the mapped special function register
area. All other SFRs are located in the standard special function register area.

For accessing PCON1 in the mapped special function register area, bit RMAP in special function
register SYSCON must be set.

Special Function Register SYSCON (Address B1H)

Reset Value : XX10XXXXB

As long as bit RMAP is set, a mapped special function register can be accessed. This bit is not
cleared by hardware automatically. Thus, when non-mapped/mapped registers are to be accessed,
the bit RMAP must be cleared/set by software, respectively each.

The registers, except the program counter and the four general purpose register banks, reside in
the special function register area. All SFRs with addresses where address bits 0-2 are 0 (e.g. 80H,
88H, 90H, 98H, ..., F8H, FFH) are bitaddressable.
The 75 special function registers (SFRs) in the SFR area include pointers and registers that provide
an interface between the CPU and the other on-chip peripherals. The SFRs of the C540U/C541U
are listed in table 3 to table 4. In table 3 they are organized in groups which refer to the functional
blocks of the C540U/C541U. Table 4 and table 4 illustrate the contents of the SFRs in numeric
order of their addresses.

Bit

Function

RMAP

Special function register map bit
RMAP = 0 : The access to the non-mapped (standard) special function

RMAP = 1 : The access to the mapped special function register area

(PCON1) is enabled.

EALE

RMAP

B1H

SYSCON

Bit No.

MSB

LSB

The functions of the shaded bits are not described in this section.

Semiconductor Group

1997-10-01

C540U
C541U

Table 3
Special Function Registers - Functional Blocks

Block

Symbol

Name

Address

Contents after
Reset

CPU

ACC
B
DPH
DPL
PSW
SP
VR0
VR1
VR2
SYSCON

Accumulator
B Register
Data Pointer, High Byte
Data Pointer, Low Byte
Program Status Word Register
Stack Pointer
Version Register 0
Version Register 1
Version Register 2
System Control Register

E0H

F0H

83H
82H
D0H

81H
FCH
FDH
FEH
B1H

00H
00H
00H
00H
00H
07H
C5H
C1H
YYH

XX10XXXXB

Interrupt
System

IEN0
IEN1
IP0
IP1
ITCON

Interrupt Enable Register 0
Interrupt Enable Register 1
Interrupt Priority Register 0
Interrupt Priority Register 1
External Interrupt Trigger Condition Register

A8H

A9H
B8H

B9H

)

9AH

0XXX0000B

XXXXX000B

XXXX0000B

XXXXX000B

XXXX1010B

Ports

P0
P1
P2
P3

Port 0
Port 1
Port 2
Port 3

80H

90H

A0H

B0H

FFH
FFH
FFH
FFH

Timer 0 /
Timer 1

TCON
TH0
TH1
TL0
TL1
TMOD

Timer 0/1 Control Register
Timer 0, High Byte
Timer 1, High Byte
Timer 0, Low Byte
Timer 1, Low Byte
Timer Mode Register

88H

8CH
8DH
8AH
8BH
89H

00H
00H
00H
00H
00H
00H

SSC
Interface
(C541U
only)

SSCCON
STB
SRB
SCF
SCIEN
SSCMOD

SSC Control Register
SSC Transmit Buffer
SSC Receive Register
SSC Flag Register
SSC Interrupt Enable Register
SSC Mode Test Register

93H

94H
95H
ABH

)

ACH
96H

07H
XXH

XXH

XXXXXX00B

00H

Watchdog
(C541U
only)

WDCON
WDTREL

Watchdog Timer Control Register
Watchdog Timer Reload Register

C0H

86H

XXXX0000B

00H

1) Bit-addressable special function registers
2) "X" means that the value is undefined and the location is reserved
3) The content of this SFR varies with the actual of the step C540U/C541U (eg. 01

for the first step)

4) This SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be
set.

Semiconductor Group

1997-10-01

C540U
C541U

Pow.
Sav.
Modes

PCON
PCON1

Power Control Register
Power Control Register 1

87H
88H

X00X0000B

0XX0XXXXB

USB
Module

EPSEL
USBVAL
ADROFF
GEPIR
DCR
DPWDR
DIER
DIRR
FNRL
FNRH
EPBCn

EPBSn

EPIEn

EPIRn

EPBAn

EPLENn

USB Endpoint Select Register
USB Data Register
USB Address Offset Register
USB Global Endpoint Interrupt Request Reg.
USB Device Control Register
USB Device Power Down Register
USB Device Interrupt Control Register
USB Device Interrupt Request Register
USB Frame Number Register, Low Byte
USB Frame Number Register, High Byte
USB Endpoint n Buffer Control Register
USB Endpoint n Buffer Status Register
USB Endpoint n Interrupt Enable Register
USB Endpoint n Interrupt Request Register
USB Endpoint n Base Address Register
USB Endpoint n Buffer Length Register

D2H
D3H
D4H
D6H
C1H
C2H
C3H
C4H
C6H
C7H
C1H
C2H
C3H
C4H
C5H
C6H

80H
00H
00H

00H
000X0000B
00H
00H
00H
XXH
00000XXXB
00H
20H
00H
10H

00H
0XXXXXXXB

1) These register are multiple registers (n=0-4) with the same SFR address; selection of register "n" is done by
SFR EPSEL.
2) The reset value of ADROFF is valid only if USBVAL has not been read or written since the last hardware reset.
3) The reset value of EPIR0 is 11

Table 3
Special Function Registers - Functional Blocks (cont'd)

Block

Symbol

Name

Address

Contents after
Reset

Semiconductor Group

1997-10-01

C540U
C541U

Table 4
Contents of the SFRs, SFRs in numeric order of their addresses

Addr Register Reset

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

80H

FFH

81H SP

07H

82H DPL

00H

83H DPH

00H

86H

WDTREL 00H

WDT
PSEL

87H PCON

X00X-
0000B

PDS

IDLS

GF1

GF0

PDE

IDLE

88H

TCON

00H

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

88H

2) 3)

PCON1

0XX0-
XXXXB

EWPD

89H TMOD

00H

GATE

C/T

GATE

C/T

8AH TL0

00H

8BH TL1

00H

8CH TH0

00H

8DH TH1

00H

90H

FFH

SLS

STO

SRI

SCLK

LED1

LED0

93H

SSCCON

07H

SCEN

TEN

MSTR

CPOL

CPHA

BRS2

BRS1

BRS0

94H

STB

XXH

95H

SRB

XXH

96H

SSCMOD

00H

LOOPB

TRIO

LSBSM

9AH ITCON

XXXX-
1010B

I1ETF

I1ETR

I0ETF

I0ETR

A0H

FFH

A8H

IEN0

0XXX-
0000B

ET1

EX1

ET0

EX0

A9H IEN1

XXXX-
X000B

EUDI

EUEI

ESSC

ABH

SCF

XXXX-
XX00B

WCOL TC

Semiconductor Group

1997-10-01

C540U
C541U

ACH

SCIEN

XXXX-
XX00B

WCEN TCEN

B0H

FFH

INT1

INT0

DADD

LED2

B1H SYSCON XX10-

XXXXB

EALE

RMAP

B8H

IP0

XXXX-
0000B

PT1

PX1

PT0

PX0

B9H IP1

XXXX-
0000B

PUDI

PUEI

PSSC

C0H

WDCON

XXXX-
0000B

OWDS WDTS

WDT

SWDT

C1H to C7H

USB Device and Endpoint Register definition see table 3-4

D0H

PSW

00H

RS1

RS0

D2H EPSEL

80H

EPS7

EPS2

EPS1

EPS0

D3H USBVAL 00H

D4H ADROFF 00H

AO5

AO4

AO3

AO2

AO1

AO0

D6H GEPIR

00H

EPI4

EPI3

EPI2

EPI1

EPI0

E0H

ACC

00H

F0H

00H

FCH

3) 5)

VR0

C5H

FDH

3) 5)

VR1

C1H

FEH

3) 5)

VR2

1) X means that the value is undefined and the location is reserved
2) Bit-addressable special function registers
3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.
4) This SFR respectively bit is only available in the C541U.
5) These are read-only registers
6) The content of this SFR varies with the actual of the step C517A (e.g. 01

for the first step)

7) The reset value of ADROFF is valid only if USBVAL has not been read or written since the last hardware reset.

Table 4
Contents of the SFRs, SFRs in numeric order of their addresses (cont'd)

Addr Register Reset

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Semiconductor Group

1997-10-01

C540U
C541U

Table 5
Contents of the USB Device and Endpoint Registers (Addr. C1H to C7H)

Addr Register Reset

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

EPSEL = 1XXX.XXXXB Device Registers
C1H DCR

000X.
0000B

SPEED

SWR

SUSP

DINIT

RSM

UCLK

PCLK

C2H DPWDR 00H

TPWD

RPWD

C3H DIER

00H

SE0IE

DAIE

DDIE

SBIE

SEIE

STIE

SUIE

SOFIE

C4H DIRR

00H

SE0I

DAI

DDI

SBI

SEI

STI

SUI

SOFI

C5H reserved
C6H FNRL

XXH

FNR7

FNR6

FNR5

FNR4

FNR3

FNR2

FNR1

FNR0

C7H FNRH

0000.
0XXXB

FNR10

FNR9

FNR8

EPSEL = 0XXX.X000B

Endpoint 0 Registers

C1H EPBC0

00H

STALL0 0

GEPIE0

SOFDE0 INCE0

DBM0

C2H EPBS0

20H

UBF0

CBF0

DIR0

ESP0

SETRD0

SETWR0

CLREP0 DONE0

C3H EPIE0

00H

AIE0

NAIE0

RLEIE0

DNRIE0

NODIE0 EODIE0 SODIE0

C4H EPIR0

11H

ACK0

NACK0

RLE0

DNR0

NOD0

EOD0

SOD0

C5H EPBA0

00H

PAGE0

A06

A05

A04

A03

C6H EPLEN0 0XXX.

XXXXB

L06

L05

L04

L03

L02

L01

L00

C7H reserved
EPSEL = 0XXX.X001B

Endpoint 1 Registers

C1H EPBC1

00H

STALL1 0

GEPIE1

SOFDE1 INCE1

DBM1

C2H EPBS1

20H

UBF1

CBF1

DIR1

ESP1

SETRD1

SETWR1

CLREP1 DONE1

C3H EPIE1

00H

AIE1

NAIE1

RLEIE1

DNRIE1

NODIE1 EODIE1 SODIE1

C4H EPIR1

10H

ACK1

NACK1

RLE1

DNR1

NOD1

EOD1

SOD1

C5H EPBA1

00H

PAGE1

A16

A15

A14

A13

C6H EPLEN1 0XXX.

XXXXB

L16

L15

L14

L13

L12

L11

L10

C7H reserved

Semiconductor Group

1997-10-01

C540U
C541U

EPSEL = 0XXX.X010B

Endpoint 2 Registers

C1H EPBC2

00H

STALL2 0

GEPIE2

SOFDE2 INCE2

DBM2

C2H EPBS2

20H

UBF2

CBF2

DIR2

ESP2

SETRD2

SETWR2

CLREP2 DONE2

C3H EPIE2

00H

AIE2

NAIE2

RLEIE2

DNRIE2

NODIE2 EODIE2 SODIE2

C4H EPIR2

10H

ACK2

NACK2

RLE2

DNR2

NOD2

EOD2

SOD2

C5H EPBA2

00H

PAGE2

A62

A52

A42

A32

C6H EPLEN2 0XXX.

XXXXB

L62

L52

L42

L32

L22

L12

L02

C7H reserved
EPSEL = 0XXX.X011B

Endpoint 3 Registers

C1H EPBC3

00H

STALL3 0

GEPIE3

SOFDE3 INCE3

DBM3

C2H EPBS3

20H

UBF3

CBF3

DIR3

ESP3

SETRD3

SETWR3

CLREP3 DONE3

C3H EPIE3

00H

AIE3

NAIE3

RLEIE3

DNRIE3

NODIE3 EODIE3 SODIE3

C4H EPIR3

10H

ACK3

NACK3

RLE3

DNR3

NOD3

EOD3

SOD3

C5H EPBA3

00H

PAGE3

A63

A52

A43

A33

C6H EPLEN3 0XXX.

XXXXB

L63

L53

L43

L33

L23

L13

L03

C7H reserved
EPSEL = 0XXX.X100B

Endpoint 4 Registers

C1H EPBC4

00H

STALL4 0

GEPIE4

SOFDE4 INCE4

DBM4

C2H EPBS4

20H

UBF4

CBF4

DIR4

ESP4

SETRD4

SETWR4

CLREP4 DONE4

C3H EPIE4

00H

AIE4

NAIE4

RLEIE4

DNRIE4

NODIE4 EODIE4 SODIE4

C4H EPIR4

10H

ACK4

NACK4

RLE4

DNR4

NOD4

EOD4

SOD4

C5H EPBA4

00H

PAGE4

A64

A54

A44

A34

C6H EPLEN4 0XXX.

XXXXB

L64

L54

L44

L34

L24

L14

L04

C7H reserved

Table 5
Contents of the USB Device and Endpoint Registers (Addr. C1H to C7H) (cont'd)

Addr Register Reset

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Semiconductor Group

1997-10-01

C540U
C541U

Digital I/O Ports

The C540U/C541U in the P-SDIP-52 package has four 8-bit I/O ports. In the P-LCC-44 package
port 1 is a 6-bit I/O port only. Port 0 is an open-drain bidirectional I/O port, while ports 1 to 3 are
quasi-bidirectional I/O ports with internal pullup resistors. That means, when configured as inputs,
ports 1 to 3 will be pulled high and will source current when externally pulled low. Port 0 will float
when configured as input.

The output drivers of port 0 and 2 and the input buffers of port 0 are also used for accessing external
memory. In this application, port 0 outputs the low byte of the external memory address, time
multiplexed with the byte being written or read. Port 2 outputs the high byte of the external memory
address when the address is 16 bits wide. Otherwise, the port 2 pins continue emitting the P2 SFR
contents. In this function, port 0 is not an open-drain port, but uses a strong internal pullup FET.

Two port lines of port 1 (P1.0/LED0, P1.1/LED1) and one port line of port 3 (P3.0/LED2) have the
capability of driving external LEDs in the output low state.

Semiconductor Group

1997-10-01

C540U
C541U

Timer / Counter 0 and 1

Timer/Counter 0 and 1 can be used in four operating modes as listed in table 6 :

In the "timer" function (C/T = `0') the register is incremented every machine cycle. Therefore the
count rate is

OSC

/6.

In the "counter" function the register is incremented in response to a 1-to-0 transition at its
corresponding external input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a
falling edge the max. count rate is

OSC

/12. External inputs INT0 and INT1 (P3.2, P3.3) can be

programmed to function as a gate to facilitate pulse width measurements. Figure 11 illustrates the
input clock logic.

Figure 11
Timer/Counter 0 and 1 Input Clock Logic

Table 6
Timer/Counter 0 and 1 Operating Modes

Mode

Description

TMOD

Input Clock

internal

external (max)

8-bit timer/counter with a
divide-by-32 prescaler

OSC

/6x32

OSC

/12x32

16-bit timer/counter

OSC

/12

8-bit timer/counter with
8-bit autoreload

Timer/counter 0 used as one
8-bit timer/counter and one
8-bit timer
Timer 1 stops

MCS03117

OSC

C/T = 0

C/T = 1

Control

TR1

P3.5/T1

(TMOD)

P3.2/INT0

Timer 0/1
Input Clock

OSC

P3.4/T0

TR0

Gate

P3.3/INT1

Semiconductor Group

1997-10-01

C540U
C541U

SSC Interface (C541U only)

The C541U microcontroller provides a Synchronous Serial Channel unit, the SSC. This interface is
compatible to the popular SPI serial bus interface. Figure 12 shows the block diagram of the SSC.
The central element of the SSC is an 8-bit shift register. The input and the output of this shift register
are each connected via a control logic to the pin P1.3 / SRI (SSC Receiver In) and P1.4 / STO (SSC
Transmitter Out). This shift register can be written to (SFR STB) and can be read through the
Receive Buffer Register SRB.

Figure 12
SSC Block Diagram

The SSC has implemented a clock control circuit, which can generate the clock via a baud rate
generator in the master mode, or receive the transfer clock in the slave mode. The clock signal is
fully programmable for clock polarity and phase. The pin used for the clock signal is P1.2/ SCLK.
When operating in slave mode, a slave select input is provided which enables the SSC interface
and also will control the transmitter output. The pin used for this is P1.5 / SLS.

The SSC control block is responsible for controlling the different modes and operation of the SSC,
checking the status, and generating the respective status and interrupt signals.

Clock Divider

Clock Selection

Receive Buffer Register

Int. Enable Reg.

Control Register

. . .

OSC

Shift Register

STB

SRB

Control

Logic

P1.2 / SCLK

P1.3 / SRI

P1.4 / STO

P1.5 / SLS

SCIEN

SSCCON

SCF

Status Register

Control Logic

Interrupt

Internal Bus

MCB03379

Semiconductor Group

1997-10-01

C540U
C541U

USB Module

The USB module in the C540U/C541U handles all transactions between the serial USB bus and the
internal (parallel) bus of the microcontroller. The USB module includes several units which are
required to support data handling with the USB bus : the on-chip USB bus transceiver, the USB
memory with two pages of 128 bytes each, the memory management unit (MMU) for USB and CPU
memory access control, the UDC device core for USB protocol handling, the microcontroller
interface with the USB specific special function registers and the interrupt control logic. A clock
generation unit provides the clock signal for the USB module for full speed and low speed USB
operation. Figure 13 shows the block diagram of the functional units of the USB module with their
interfaces.

Figure 13
USB Module Block Diagram

MCB03380

XTAL1

XTAL2

D+

D-

USB

Bus

Osc.

12 MHz

(On-chip)

Transceiver

x 4

PLL

48 MHz

6 MHz

USB

Page 0

(128 x 8)

Data

Control

USB Memory

Management

MMU

Interrupt Generation

SFR

Addr.

Core

Device

USB

MCU

Interface

Module

USB

Internal

Bus

Memory

Page 1

(UDC)

Control

Address

Semiconductor Group

1997-10-01

C540U
C541U

USB Registers

Two different kinds of registers are implemented in the USB module. The global registers (GEPIR,
EPSEL, ADROFF, USBVAL) describe the basic functionality of the complete USB module and can
be accessed via unique SFR addresses. For reduction of the number of SFR addresses which are
needed to control the USB module inside the C540U/C541U, device registers and endpoint
registers are mapped into an SFR address block of seven SFR addresses (C1H to C7H). The
endpoint specific functionality of the USB module is controlled via the device registers DCR,
DPWDR, DIER, DIRR and the frame number registers. An endpoint register set is available for each
endpoint (n=0..4) and describes the functionality of the selected endpoint. Figure 14 explains the
structure of the USB module registers.

Figure 14
Register Structure of the USB Module

0 0 0 .4 .3 .2 .1 .0

0 .5 .4

.2 .1

.6 .5

ADROFF (D4 )

EPSEL (D2 )

USBVAL (D3 )

GEPIR (D6 )

Decoder

Global Registers

FNRH

DCR

DPWDR

DIER

DIRR

reserved

FNRL

Device

Registers

Endpoint 0

EPIR0

reserved

EPLEN0

Registers

EPBA0

EPBS0

EPIE0

EPBC0

Endpoint 2

Endpoint 1

Registers

Endpoint 3

Registers

Endpoint 4

Registers

reserved

EPLEN1

EPBA1

EPIR1

EPIE1

EPBS1

EPBC1

reserved

EPLEN2

EPBA2

EPIR2

EPIE2

EPBS2

EPBC2

reserved

EPLEN3

EPBA3

EPIR3

EPIE3

EPBS3

EPBC3

reserved

EPLEN4

EPBA4

EPIR4

EPIE4

EPBS4

EPBC4

MCD03312

Semiconductor Group

1997-10-01

C540U
C541U

Interrupt System

The C541U provides seven (C540U : six) interrupt sources with two priority levels. Five interrupts
can be generated by the on-chip peripherals (timer 0, timer 1, SSC interface, and USB module), and
two interrupts may be triggered externally (P3.2/INT0 and P3.3/INT1).

Figure 15 to 17 give a general overview of the interrupt sources and illustrate the request and
control flags which are described in the next sections.

Figure 15
Interrupt Request Sources (Part 1)

000B

ET0

IEN0.1

TF0

TCON.5

Timer 0 Overflow

P3.2 /
INT0

P3.3 /
INT1

001B

ET1

IEN0.3

TF1

TCON.7

Timer 1 Overflow

IP0.1

PT0

IP0.3

PT1

0013

EX1

IEN0.2

IP0.2

PX1

Low Priority

High Priority

IEN0.7

Bit addressable

Request Flag is cleared by hardware

0003

EX0

IEN0.0

IP0.0

PX0

IE0

TCON.1

IE0

TCON.3

IT0

TCON.0

ITCON.1

ITCON.0

IT1

TCON.2

ITCON.3

ITCON.2

Semiconductor Group

1997-10-01

C540U
C541U

Figure 16
Interrupt Request Sources (Part 2)

Request flag is cleared by hardware after the corresponding register has been read.

Bit addressable

IEN0.7

EPIR0.7

ACK0

EPIR0.6

NACK0

EPIR0.5

RLE0

EPIR0.3

DNR0

EPIR0.2

NOD0

EPIR0.1

EOD0

EPIR0.0

SOD0

AIE0

EPIE0.7

EPIE0.6

NAIE0

EPIE0.5

RLEIE0

EPIE0.3

DNRIE0

EPIE0.2

NODIE0

EPIE0.1

EODIE0

EPIE0.0

SODIE0

EUEI

IEN1.1

High Priority

Low Priority

PUEI

IP1.1

004B

Endpoint Interrupts

MCB03382

Endpoint 0 Interrupts

GEPIE0

GEPIR.0

EPI0

Endpoint 1 Interrupts

Endpoint 2 Interrupts

Endpoint 3 Interrupts

Endpoint 4 Interrupts

IP1.0

PSSC

0043

IEN1.0

ESSC

SCIEN.1

WCEN

TCEN

SCIEN.0

WCOL

SCF.1

SCF.0

SSC
Interrupts
(C541U only)

EPBC0.4

Semiconductor Group

1997-10-01

C540U
C541U

Figure 17
Interrupt Request Sources (Part 3)

Table 7
Interrupt Source and Vectors

Interrupt Source

Interrupt Vector Address

Interrupt Request Flags (SFRs)

External Interrupt 0

0003H

IE0

Timer 0 Overflow

000BH

TF0

External Interrupt 1

0013H

IE1

Timer 1 Overflow

001BH

TF1

SSC Interrupt (C541U only)

0043H

TC, WCOL

USB Endpoint Interrupt

004BH

in SFRs EPIR0-4 and GEIPR

USB Device Interrupt

0053H

in SFRs DIRR

Wake-up from power down

007BH

Request flag is cleared by hardware after the corresponding register has been read.

Bit addressable

IE0.7

DIRR.7

SE0I

DIRR.6

DAI

DIRR.5

DDI

DIRR.4

SBI

DIRR.3

SEI

DIRR.2

STI

DIRR.1

SUI

DIRR.0

SOFI

SE0IE

DIER.7

DIER.6

DAIE

DIER.5

DDIE

DIER.4

SBIE

DIER.3

SEIE

DIER.2

STIE

DIER.1

SUIE

DIER.0

SOFIE

EUDI

IE1.2

High Priority

Low Priority

PUDI

IP1.2

0053

Device Interrupts

MCB03383

Semiconductor Group

1997-10-01

C540U
C541U

Fail Save Mechanisms

The C540U/C541U offers enhanced fail safe mechanisms, which allow an automatic recovery from
software upset or hardware failure :

a programmable watchdog timer (WDT), with variable time-out period from 256

s up to

approx. 0.55

s at 12 MHz. The WDT is not available in the C540U.

an oscillator watchdog (OWD) which monitors the on-chip oscillator and forces the

microcontroller into reset state in case the on-chip oscillator fails; it also provides the clock for
a fast internal reset after power-on.

The watchdog timer in the C517A is a 15-bit timer, which is incremented by a count rate of

OSC

/12

OSC

/192. The system clock of the C517A is divided by two prescalers, a divide-by-two and a

divide-by-16 prescaler which are selected by bit WDTPSEL (WDTREL.7). For programming of the
watchdog timer overflow rate, the upper 7 bit of the watchdog timer can be written. Figure 8-18
shows the block diagram of the watchdog timer unit.

Figure 18
Block Diagram of the Watchdog Timer

The watchdog timer can be started by software (bit SWDT) but it cannot be stopped during active
mode of the C541U. If the software fails to refresh the running watchdog timer an internal reset will
be initiated on watchdog timer overflow. For refreshing of the watchdog timer the content of the SFR
WDTREL is transfered to the upper 7-bit of the watchdog timer. The refresh sequence consists of
two consequtive instructions which set the bits WDT and SWDT each. The reset cause (external
reset or reset caused by the watchdog) can be examined by software (flag WDTS). It must be noted,
however, that the watchdog timer is halted during the idle mode and power down mode of the
processor.

MCB03384

WDCON (CO )

OSC

OWDS WDTS

WDT

SWDT

WDTL

WDTH

/ 6

External HW Reset

Control Logic

WDT Reset-Request

WDTPSEL

WDTREL

Semiconductor Group

1997-10-01

C540U
C541U

Oscillator Watchdog

The oscillator watchdog unit serves for three functions:

Monitoring of the on-chip oscillator's function

The watchdog supervises the on-chip oscillator's frequency; if it is lower than the frequency
of the auxiliary RC oscillator in the watchdog unit, the internal clock is supplied by the RC
oscillator and the device is brought into reset; if the failure condition disappears (i.e. the on-
chip oscillator has a higher frequency than the RC oscillator), the part executes a final reset
phase of typ. 1 ms in order to allow the oscillator to stabilize; then the oscillator watchdog reset
is released and the part starts program execution again.

Fast internal reset after power-on

The oscillator watchdog unit provides a clock supply for the reset before the on-chip oscillator
has started. The oscillator watchdog unit also works identically to the monitoring function.

Control of external wake-up from software power-down mode (description see chapter 9)

When the power-down mode is left by a low level at the INT0 pin or by the USB, the oscillator
watchdog unit assures that the microcontroller resumes operation (execution of the power-
down wake-up interrupt) with the nominal clock rate. In the power-down mode the RC
oscillator and the on-chip oscillator are stopped. Both oscillators are started again when
power-down mode is released. When the on-chip oscillator has a higher frequency than the
RC oscillator, the microcontroller starts operation after a final delay of typ. 1 ms in order to
allow the on-chip oscillator to stabilize.

Semiconductor Group

1997-10-01

C540U
C541U

Figure 19
Functional Block Diagram of the Oscillator Watchdog

Int. Clock

XTAL2

XTAL1

OWDS

MCD03385

WDCON (C0 )

3 MHz

Delay

Activity on

Start /
Stop

Mode Activated

Power - Down

Power-Down Mode
Wake - Up Interrupt

Internal Reset

P3.2 / INT0

Control

WS
(PCON1.4)

(PCON1.7)

EWPD

Frequency

Comparator

On-Chip

Oscillator

Logic

Oscillator

Logic

Control

USB Bus

Semiconductor Group

1997-10-01

C540U
C541U

Power Saving Modes

The C540U/C541U provides two basic power saving modes, the idle mode and the power down
mode.

Idle mode

In the idle mode the main oscillator of the C540U/C541U continues to run, but the CPU is
gated off from the clock signal. However, the interrupt system, the SSC (C541U only), the
USB module, and the timers with the exception of the watchdog timer (C541U only) are further
provided with the clock. The CPU status is preserved in its entirety : the stack pointer, program
counter, program status word, accumulator, and all other registers maintain their data during
idle mode. The idle mode can be terminated by activating any enabled interrupt. or by a
hardware reset.

Power down mode

In the power down mode, the RC osciillator and the on-chip oscillator which operates with the
XTAL pins is stopped. Therefore, all functions of the microcontroller are stopped and only the
contents of the on-chip RAM, XRAM and the SFR's are maintained. The power down mode
can be left either by an active reset signal or by a low signal at the P3.2/INT0 pin or any activity
on the USB bus. Using reset to leave power down mode puts the microcontroller with its SFRs
into the reset state. Using the INT0 pin or USB bus for power down mode exit maintains the
state of the SFRs, which has been frozen when power down mode is entered.

In the power down mode of operation,

can be reduced to minimize power consumption. It must

be ensured, however, that

is not reduced before the power down mode is invoked, and that

is restored to its normal operating level, before the power down mode is terminated. Table 8 gives
a general overview of the entry and exit procedures of the power saving modes.

Table 8
Power Saving Modes Overview

Mode

Entering
2-Instruction
Example

Leaving by

Remarks

Idle mode

ORL PCON, #01H
ORL PCON, #20H

Ocurrence of an
interrupt from a
peripheral unit

CPU clock is stopped;
CPU maintains their data;
peripheral units are active (if
enabled) and provided with
clock

Hardware Reset

Power Down Mode

ORL PCON, #02H
ORL PCON, #40H

Hardware Reset

Oscillator is stopped;
contents of on-chip RAM and
SFR's are maintained;

Short low pulse at
pin P3.2/INT0 or
activity on the USB
bus

Semiconductor Group

1997-10-01

C540U
C541U

OTP Memory Operation

The C540U/C541U contains a 8k byte one-time programmable (OTP) program memory (C540U :
4k byte). With the C540U/C541U fast programming cycles are achieved (1 byte in 100

sec). Also

several levels of OTP memory protection can be selected.

For programming of the device, the C540U/C541U must be put into the programming mode. This
typically is done not in-system but in a special programming hardware. In the programming mode
the C540U/C541U operates as a slave device similar as an EPROM standalone memory device
and must be controlled with address/data information, control lines, and an external 11.5V
programming voltage. Figure 20 shows the pins of the C504-2E which are required for controlling
of the OTP programming mode.

Figure 20
Programming Mode Configuration

PMSEL1

PMSEL0

XTAL2

XTAL1

D0 - D7

C541U

MCS03386

A8 - A12

PALE

EA /

PROG

PRD

RESET

PSEN

PSEL

Port 2

Port 0

C540U

A0 - A7 /

Semiconductor Group

1997-10-01

C540U
C541U

Pin Configuration in Programming Mode

Figure 21
P-LCC-44 Pin Configuration of the C540U/C541U in Programming Mode (Top View)

N.C.

D4
D5

PSEN

XTAL2

A2 / A10

XTAL1

GND

MCP03387

D6
D7

EA /

4 3 2 1 44 43 42 41 40

N.C.

A3 / A11

A4 / A12

A1 / A9

37
36
35
34

30
29

C541U

N.C.

RESET

A6
A5

PMSEL1

PSEL

PRD

PALE

GND

18 19 20 21 22

PMSEL0

N.C:

N.C.
PROG

C540U

Programming

Mode

A0 / A8

Semiconductor Group

1997-10-01

C540U
C541U

Figure 22
P-SDIP-52 Pin Configuration of the C540U/C541U in Programming Mode (Top View)

C540U
C541U

Programming

Mode

N.C.
P1.5 / SLS
D0
D1
D2
D3
D4
D5
D6
D7
EA /
N.C.
N.C.

A7
A6
A5
A4 / A12
A3 / A11
A2 / A10
A1 / A9
A0 / A8
N.C.

PSEN

PROG

N.C.

14
15
16
17
18
19
20
21
22
23
24
25

50
49
48
47
46
45
44
43
42

40
39
38
37
36
35
34
33
32

30
29
28
27

XTAL1

PALE

XTAL2

GND

PRD

PSEL

PMSEL1

N.C.

PMSEL0

RESET

N.C.

V
V

MCP03388

Semiconductor Group

1997-10-01

C540U
C541U

The following table 9 contains the functional description of all C517A-2E pins which are required for
OTP memory programming.

Table 9
Pin Definitions and Functions in Programming Mode

Symbol

Pin Numbers

I/O*) Function

P-LCC-44 P-SDIP-52

RESET

Reset
This input must be at static "1" (active) level during the
whole programming mode.

PMSEL0
PMSEL1

11
13

13
16

I
I

Programming mode selection pins
These pins are used to select the different access
modes in programming mode. PMSEL1,0 must satisfy
a setup time to the rising edge of PALE. When the
logic level of PMSEL1,0 is changed, PALE must be at
low level.

PSEL

Basic programming mode select
This input is used for the basic programming mode
selection and must be switched according figure 10-
23.

PRD

Programming mode read strobe
This input is used for read access control for OTP
memory read, version byte read, and lock bit read
operations.

PALE

Programming mode address latch enable
PALE is used to latch the high address lines. The high
address lines must satisfy a setup and hold time to/
from the falling edge of PALE. PALE must be at low
level whenever the logic level of PMSEL1,0 is
changed.

XTAL2

XTAL2
Output of the inverting oscillator amplifier.

*) I = Input

O = Output

PMSEL

Access Mode

Reserved

Read version bytes

Program/read lock bits

Program/read OTP memory byte

Semiconductor Group

1997-10-01

C540U
C541U

XTAL1

XTAL1
Input to the oscillator amplifier.

A0/A8 -
A7

24 - 31

28 - 35

Address lines
P2.0-7 are used as multiplexed address input lines
A0-A7 and A8-A12. A8-A12 must be latched with
PALE. Address A12 is requred only for the C541U.

PSEN

Program store enable
This input must be at static "0" level during the whole
programming mode.

PROG

Programming mode write strobe
This input is used in programming mode as a write
strobe for OTP memory program and lock bit write
operations During basic programming mode selection
a low level must be applied to PROG.

EA/V

External Access / Programming voltage
This pin must be at 11.5 V (V

) voltage level during

programming of an OTP memory byte or lock bit.
During an OTP memory read operation this pin must
be at high level (V

). This pin is also used for basic

programming mode selection. At basic programming
mode selection a low level must be applied to EA/V

D0 - 7

43 - 38

50 - 43

I/O

Data lines 0-7
During programming mode, data bytes are read or
written from or to the C540U/C541U via the
bidirectional D0-7 lines which are located at port 0.

9, 22

11, 25

Circuit ground potential
must be applied to these pins in programming mode.

8, 23

10, 26

Power supply terminal
must be applied to these pins in programming mode.

N.C.

1, 12,,
34, 44

1 - 9, 14,
15, 27, 36,
37, 40, 41,
52

Not Connected
These pins should not be connected in programming
mode.

GND

17 - 19

20 - 22

Ground pins
In programming mode these pins must be connected
to

level.

*) I = Input

O = Output

Table 9
Pin Definitions and Functions in Programming Mode (cont'd)

Symbol

Pin Numbers

I/O*) Function

P-LCC-44 P-SDIP-52

Semiconductor Group

1997-10-01

C540U
C541U

Lock Bits Programming / Read

The C540U/C541U has two programmable lock bits which, when programmed according tabie 11,
provide four levels of protection for the on-chip OTP code memory. The state of the lock bits can
also be read.

Table 10
Access Modes Selection

Access Mode

EA/

PROG

PRD

PMSEL

Address

(Port 2)

Data

(Port 0)

Program OTP memory byte

A0-7

A8-15

D0-7

Read OTP memory byte

Program OTP lock bits

D1,D0 see

table 11

Read OTP lock bits

Read OTP version byte

Byte addr.

of sign. byte

D0-7

Table 11
Lock Bit Protection Types

Lock Bits at D1,D0

Protection
Level

Protection Type

Level 0

The OTP lock feature is disabled. During normal operation of
the C540U/C541U, the state of the EA pin is not latched on
reset.

Level 1

During normal operation of the C540U/C541U, MOVC
instructions executed from external program memory are
disabled from fetching code bytes from internal memory. EA is
sampled and latched on reset. An OTP memory read operation
is only possible using the OTP verification mode for protection
level 1. Further programming of the OTP memory is disabled
(reprogramming security).

Level 2

Same as level 1, but also OTP memory read operation using
OTP verification mode is disabled.

Level 3

Same as level 2; but additionally external code execution by
setting EA=low during normal operation of the C540U/C541U
is no more possible.
External code execution, which is initiated by an internal
program (e.g. by an internal jump instruction above the ROM
boundary), is still possible.

Semiconductor Group

1997-10-01

C540U
C541U

Absolute Maximum Ratings

Ambient temperature under bias (

) ......................................................... 0 to 70

Storage temperature (

stg

) .......................................................................... 65

C to 150

Voltage on

pins with respect to ground (

) ....................................... 0.5 V to 6.5 V

Voltage on any pin with respect to ground (

) ......................................... 0.5 V to

+0.5 V

Input current on any pin during overload condition..................................... 10 mA to 10 mA
Absolute sum of all input currents during overload condition ..................... I 100 mA I
Power dissipation........................................................................................ TBD

Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent

damage of the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for longer
periods may affect device reliability. During overload conditions (

) the

Voltage on

pins with respect to ground (

) must not exceed the values defined by the

absolute maximum ratings.

Semiconductor Group

1997-10-01

C540U
C541U

DC Characteristics

= 4.0V to 5.5V (5V +10%, -20%);

= 0 V

= 0 to 70

Notes see next page

Parameter

Symbol

Limit Values

Unit

Test Condition

min.

max.

Input low voltage (except EA,
RESET)

0.5

0.2

0.1

Input low voltage (EA)

IL1

0.5

0.2

0.3

Input low voltage (RESET)

IL2

0.5

0.2

0.1

Input high voltage (except XTAL1,
RESET)

0.2

0.9

+ 0.5

Input high voltage to XTAL1

IH1

0.7

+ 0.5

Input high voltage to RESET

IH2

0.6

+ 0.5

Output low voltage
Ports 1, 2, 3
P1.0, P1.1, P3.0

0.45
0.45

V
V

= 1.6 mA

= 10 mA

Output low voltage (port 0, ALE,
PSEN)

OL1

0.45

= 3.2 mA

Output high voltage (ports 1, 2, 3)

2.4
0.9

= 80

= 10

Output high voltage (port 0 in
external bus mode, ALE, PSEN)

OH2

2.4
0.9

= 800

= 80

Logic 0 input current (ports 1, 2, 3)

= 0.45 V

Logical 1-to-0 transition current
(ports 1, 2, 3)

650

= 2 V

Input leakage current (port 0, EA)

0.45 <

Pin capacitance

= 1 MHz,

= 25

Overload current

6) 7)

Programming voltage

10.9

12.1

11.5 V

Semiconductor Group

1997-10-01

C540U
C541U

Power Supply Current

Notes :

1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the

of ALE

and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these
pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise
pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a schmitt-trigger,
or use an address latch with a schmitt-trigger strobe input.

2) Capacitive loading on ports 0 and 2 may cause the

on ALE and PSEN to momentarily fall below the

0.9

specification when the address lines are stabilizing.

(power-down mode) is measured under following conditions:

EA = Port 0 =

; XTAL2 = N.C.; XTAL1 =

; RESET =

; all other pins are disconnected.

the USB transceiver is switched off;

(active mode) is measured with:

XTAL1 driven with

CLCH

CHCL

= 5 ns ,

+ 0.5 V,

0.5 V; XTAL2 = N.C.;

EA = RESET = Port 0 = Port 1 =

; all other pins are disconnected.

would be slightly higher if a crystal oscillator is used (appr. 1 mA).

(idle mode) is measured with all output pins disconnected and with all peripherals disabled;

XTAL1 driven with

CLCH

CHCL

= 5 ns,

+ 0.5 V,

0.5 V; XTAL2 = N.C.;

EA = RESET =

; Port 0 =

; all other pins are disconnected;

6) Overload conditions occur if the standard operating conditions are exceeded, ie. the voltage on any pin

exceeds the specified range (i.e.

+ 0.5 V or

- 0.5 V). The supply voltage

and

must

remain within the specified limits. The absolute sum of input currents on all port pins may not exceed 50 mA.

7) Not 100% tested, guaranteed by design characterization.

8) The typical

values are periodically measured at

= +25 °C but not 100% tested.

9) The maximum

values are measured under worst case conditions (

= 0 °C and

= 5.5 V)

Parameter

Symbol

Limit Values

Unit Test Condition

typ.

max.

Active mode

12 MHz

TBD

Idle mode

12 MHz

TBD

Power-down mode

TBD

= 2

...

5.5 V

Semiconductor Group

1997-10-01

C540U
C541U

AC Characteristics

= 4.0V to 5.5V (5V +10%, -20%);

= 0 V

= 0 to 70

(

for port 0, ALE and PSEN outputs = 100 pF;

for all other outputs = 80 pF)

Program Memory Characteristics

Interfacing the C540U/C541U to devices with float times up to 28 ns is permissible. This limited bus contention
will not cause any damage to port 0 drivers.

**)

For correct function of the USB module the C540U/C541U must operate with 12 MHz external clock. The
microcontroller (except the USB module) operates down to 2 MHz.

Parameter

Symbol

Limit Values

Unit

10-MHz clock

Duty Cycle

0.4 to 0.6

Variable Clock

1/CLP = 2 MHz to

12 MHz **)

min.

max.

min.

max.

ALE pulse width

LHLL

CLP - 40

Address setup to ALE

AVLL

TCL

Hmin

-20

Address hold after ALE

LLAX

TCL

Hmin

-20

ALE to valid instruction in

LLIV

2 CLP - 87

ALE to PSEN

LLPL

TCL

Lmin

-20

PSEN pulse width

PLPH

CLP+
TCL

Hmin

-30

PSEN to valid instruction in

PLIV

CLP+
TCL

Hmin

- 65

Input instruction hold after PSEN

PXIX

Input instruction float after PSEN

PXIZ

TCL

Lmin

-10

Address valid after PSEN

PXAV

TCL

Lmin

- 5

Address to valid instruction in

AVIV

140

2 CLP +
TCL

Hmin

-60

Address float to PSEN

AZPL

Semiconductor Group

1997-10-01

C540U
C541U

AC Characteristics (cont'd)

External Data Memory Characteristics

Parameter

Symbol

Limit Values

Unit

10-MHz

clock

Duty Cycle

0.4 to 0.6

Variable Clock

1/CLP= 2 MHz to 12 MHz

min.

max.

min.

max.

RD pulse width

RLRH

180

3 CLP - 70

WR pulse width

WLWH

180

3 CLP - 70

Address hold after ALE

LLAX2

CLP

- 27

RD to valid data in

RLDV

110

2 CLP+
TCL

Hmin

- 90

Data hold after RD

RHDX

Data float after RD

RHDZ

CLP - 20

ALE to valid data in

LLDV

200

4 CLP - 133

Address to valid data in

AVDV

211

4 CLP +
TCL

Hmin

-155

ALE to WR or RD

LLWL

166

CLP +
TCL

Lmin

- 50

CLP+
TCL

Lmin

+ 50

Address valid to WR

AVWL

2 CLP - 97

WR or RD high to ALE high

WHLH

TCL

Hmin

- 25

TCL

Hmin

+ 25

Data valid to WR transition

QVWX

TCL

Lmin

- 25

Data setup before WR

QVWH

163

3 CLP +
TCL

Lmin

- 120

Data hold after WR

WHQX

TCL

Hmin

- 25

Address float after RD

RLAZ

Semiconductor Group

1997-10-01

C540U
C541U

AC Characteristics (cont'd)

External Clock Drive Characteristics

Parameter

Symbol

CPU Clock = 12 MHz

Duty cycle 0.4 to 0.6

Variable CPU Clock

1/CLP = 2 to 12 MHz

Unit

min.

max.

min.

max.

Oscillator period

CLP

83.3

500

High time

TCL

CLP-TCL

Low time

TCL

CLP-TCL

Rise time

Fall time

Oscillator duty cycle

0.4

0.6

33 / CLP

1 - 33 / CLP

Clock cycle

TCL

CLP * DC

min

CLP * DC

max

SSC Interface Characteristics

Parameter

Symbol

Limit Values

Unit

min.

max.

Clock Cycle Time : Master Mode

Slave Mode

SCLK

667
667

ns
ns

Clock high time

SCH

300

Clock low time

SCL

300

Data output delay

100

Data output hold

Data input setup

100

Data input hold

TC bit set delay

DTC

8 CLP

SLS low to first SCLK clock edge

CLCL

Last SCLK clock edge to SLS high

CLCL

SLS low to STO active

100

SLS high to STO tristate

100

Data output delay (already
defined)

100

Semiconductor Group

1997-10-01

C540U
C541U

Figure 28
SSC Master Mode Timing

MCT02417

SCLK

STO

SRI

SCL

MSB

LSB

MSB

LSB

SCH

SCLK

~ ~

DTC

Notes :

Shown is the data/clock relationship for CPOL=CPHA=1. The timing diagram is valid for the other
cases accordingly.

In the case of slave mode and CPHA=0, the output delay for the MSB applies to the falling edge
of SLS (if transmitter is enabled).

In the case of master mode and CPHA=0, the MSB becomes valid after the data has been written
into the shift register, i.e. at least one half SCLK clock cycle before the first clock transition.

Semiconductor Group

1997-10-01

C540U
C541U

AC Characteristics of Programming Mode

= 5 V

10 %;

= 11.5 V

5 %;

= 25 °C

10 °C

Parameter

Symbol

Limit Values

Unit

min.

max.

ALE pulse width

PAW

PMSEL setup to ALE rising edge

PMS

Address setup to ALE, PROG, or PRD falling
edge

PAS

Address hold after ALE, PROG, or PRD
falling edge

PAH

Address, data setup to PROG or PRD

PCS

100

Address, data hold after PROG or PRD

PCH

PMSEL setup to PROG or PRD

PMS

PMSEL hold after PROG or PRD

PMH

PROG pulse width

PWW

100

PRD pulse width

PRW

100

Address to valid data out

PAD

PRD to valid data out

PRD

Data hold after PRD

PDH

Data float after PRD

PDF

PROG high between two consecutive PROG
low pulses

PWH1

PRD high between two consecutive PRD low
pulses

PWH2

100

XTAL clock period

CLKP

83.3

500

Semiconductor Group

1997-10-01

C540U
C541U

Figure 32
Lock Bit Access Timing

Figure 33
Version Byte Read Timing

H, L

D0, D1

PCS

PMS

PMH

PCH

PWW

PMS

PRD

PDH

PDF

PMH

PRW

MCT03393

PMSEL1,0

Port 0

PROG

PRD

PALE should be low during a lock bit read / write cycle.

Note:

e. g. FD

D0-7

PCS

PMS

PDH

PDF

PMH

MCT03394

Port 2

Port 0

PRD

PMSEL1,0

L, H

PRW

PRD

PCH

PROG must be high during a programming read cycle.

Note:

Semiconductor Group

1997-10-01

C540U
C541U

OTP Verification Characteristics

OTP Verification Mode for Protection Level 1

Figure 34
OTP Verification Mode for Protection Level 1

Parameter

Symbol

Limit Values

Unit

min.

typ

max.

ALE pulse width

AWD

CLCL

ALE period

ACY

CLCL

Data valid after ALE

DVA

CLCL

Data stable after ALE

DSA

CLCL

P3.5 setup to ALE low

CLCL

Oscillator frequency

CLCL

MHz

MCT02613

ACY

AWD

DSA

DVA

Data Valid

ALE

Port 0

P3.5

Semiconductor Group

1997-10-01

C540U
C541U

USB Transceiver Characteristics

= 4.0V to 5.5V (5V +10%, -20%);

= 0 V

= 0 to 70

Notes :

1) This value includes an external resistor of 30

1% (see "Load for D+/D-" diagram for testing details)

2) The crossover point is in the range of 1.3V to 2.0V for the high speed mode with a 50pF capacitance. In the

low-speed mode with a 100pF or greater capacitance, the crossover point is in the range of 1.3V to 2.0V.

Parameter

Symbol

Limit Values

Unit

Test Condition

min.

max.

Output impedance (high state)

Output impedance (low state)

Input leakage current

Tristate output off-state current

OUT

Crossover point

1.3

2.0

Parameter

Symbol

Limit Values

Unit

min.

max.

High speed mode rise time

High speed mode fall time

Low speed mode rise time

300

Low speed mode fall time

300

Semiconductor Group

1997-10-01

C540U
C541U

Figure 35
AC Testing: Input, Output Waveforms

Figure 36
AC Testing : Float Waveforms

Figure 37
Load for D+/D-

AC Inputs during testing are driven at

- 0.5 V for a logic '1' and 0.45 V for a logic '0'.

Timing measurements are made at

IHmin

for a logic '1' and

ILmax

for a logic '0'.

0.45 V

0.2

-0.1

+0.9

0.2

Test Points

MCT00039

-0.5 V

For timing purposes a port pin is no longer floating when a 100 mV change from load voltage
occurs and begins to float when a 100 mV change from the loaded

level occurs.

20 mA

MCT00038

Load

-0.1 V

+0.1 V

Load

Timing Reference

Points

-0.1 V

+0.1 V

Test Point

30 k

15 k

D.U.T

2.8 V

1.5 k

MCS03425

= 50 pF, full speed
= 50 pF, low speed (min. timing)
= 350 pF, low speed (max. timing)

*) 1.5 k

on D- (low speed) or D+ (full speed) only

Test

D- / LS

D+ / LS

D- / FS

D+ / FS

Open
Open

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