Edition 1997-08-01
Published by

Siemens AG,

Bereich Halbleiter, Marketing-
Kommunikation, Balanstraße 73,
81541 München

Siemens AG 1997.

Attention please!

As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes
and circuits implemented within components or assemblies.
The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved.
For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies
and Representatives worldwide (see address list).
Due to technical requirements components may contain dangerous substances. For information on the types in question please contact
your nearest Siemens Office, Semiconductor Group.
Siemens AG is an approved CECC manufacturer.

Packing

Please use the recycling operators known to you. We can also help you get in touch with your nearest sales office. By agreement we
will take packing material back, if it is sorted. You must bear the costs of transport.
For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs in-
curred.

Components used in life-support devices or systems must be expressly authorized for such purpose!

Critical components

of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems

with the express

written approval of the Semiconductor Group of Siemens AG.
1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the

failure of that life-support device or system, or to affect its safety or effectiveness of that device or system.

2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain hu-

man life. If they fail, it is reasonable to assume that the health of the user may be endangered.

C515 Data Sheet
Revision History:

Current Version: 1997-08-01

Previous Version:

none (Original Version)

Page
(in previous
Version)

Page
(in current
Version)

Subjects (major changes since last revision)

C515

Semiconductor Group

1997-08-01

Data Sheet

8-Bit CMOS Microcontroller

Advance Information

Full upward compatibility with SAB 80C515

Up to 24 MHz external operating frequency
500ns instruction cycle at 24 MHz operation

8K byte on-chip ROM (with optional ROM protection)
alternatively up to 64K byte external program memory

Up to 64K byte external data memory

256 byte on-chip RAM

Six 8-bit parallel I/O ports

One input port for analog/digital input

Full duplex serial interface (USART)
4 operating modes, fixed or variable baud rates

Three 16-bit timer/counters
Timer 0 / 1 (C501 compatible)
Timer 2 for 16-bit reload, compare, or capture functions

(more features on next page)

Figure 1
C515 Functional Units

MCA03198

On-Chip Emulation Support Module

Port 0

Port 1

Port 2

Port 3

RAM

256 x 8

CPU

USART

ROM

I/O

Port

Port 4

Watchdog

Timer

A/D

Converter

I/O

Analog/

Digital

Input

8-Bit

8 x 8

Power

Modes

Saving

C515

Semiconductor Group

1997-08-01

Features (cont'd):

8-bit A/D converter
8 multiplexed analog inputs
Programmable reference voltages

16-bit watchdog timer

Power saving modes
Idle mode
Slow down mode (can be combined with idle mode)
Software power-down mode

12 interrupt sources (7 external, 5 internal) selectable at four priority levels

On-chip emulation support logic (Enhanced Hooks Technology

)

ALE switch-off capability

P-MQFP-80-1 package

Temperature Ranges :

SAB-C515

= 0 to 70

SAF-C515

= -40 to 85

SAH-C515

= -40 to 110

C (max. operating frequency: 16 MHz)

The C515 is an upward compatible version of the SAB 80C515A 8-bit microcontroller which
additionally provides ALE switch-off capability, on-chip emulation support, ROM protection, and
slow down mode capability. With a maximum external clock rate of 24 MHz it achieves a 500 ns

instruction cycle time (1

s at 12 MHz). The C515 is mounted in a P-MQFP-80 package.

Note:

Versions for extended temperature ranges 40

°C to 110

°C (SAH-C515C-LM and SAH-

C515-1RM) are available on request. The ordering number of ROM types (DXXXX
extensions) is defined after program release (verification) of the customer.

Ordering Information

Type

Ordering Code

Package

Description
(8-Bit CMOS microcontroller)

SAB-C515-1RM
SAB-C515-1R24M

Q67127-DXXXX
Q67127-DXXXX

P-MQFP-80-1
P-MQFP-80-1

with mask programmable ROM (16 MHz)
with mask programmable ROM (24 MHz)

SAF-C515-1RM

Q67127-DXXXX P-MQFP-80-1 with mask programmable ROM (16 MHz)

ext. temp. 40

°C to 85

°C

SAF-C515-1R24M Q67127-DXXXX P-MQFP-80-1 with mask programmable ROM (24 MHz)

ext. temp. 40

°C to 85

°C

SAB-C515-LM
SAB-C515-L24M

Q67127-C1030
Q67127-C1032

P-MQFP-80-1
P-MQFP-80-1

for external memory (16 MHz)
for external memory (24 MHz

SAF-C515-LM

Q67127-C1031

P-MQFP-80-1 for external memory (16 MHz)

ext. temp. 40

°C to 85

°C

SAF-C515-L24M

Q67127-C1081

P-MQFP-80-1 for external memory (24 MHz)

ext. temp. 40

°C to 85

°C

Semiconductor Group

1997-08-01

C515

Figure 2
Logic Symbol

Additional Literature

For further information about the C515 the following literature is available:

Title

Ordering Number

C515 8-Bit CMOS Microcontroller User's Manual

B158-H7049-X-X-7600

C500 Microcontroller Family
Architecture and Instruction Set User's Manual

B158-H6987-X-X-7600

C500 Microcontroller Family - Pocket Guide

B158-H6986-X-X-7600

MCL03199

XTAL1
XTAL2

RESET

ALE
PSEN

C515

Port 0
8 Bit Digital I/O

Port

Port 2

Port 3

Digital Input

Port

Port 5

Port

8 Bit Digital I/O

8 Bit Analog/

AREF

V
V

AGND

C515

Semiconductor Group

1997-08-01

Figure 3

C515 Pin Configuration (P-MQFP-80 Package, Top View)

MCP03200

1 2

N.C.

3 4 5

P6.7/AIN7

P6.6/AIN6

P6.5/AIN5

P6.4/AIN4

P6.3/AIN3

P6.2/AIN2

P6.1/AIN1

P6.0/AIN0

13 14 15

P3.0/RXD

P3.1/TXD

P3.2/INT0

P3.3/INT1

P3.4/T0

P3.5/T1

AGND

P0.7/AD7

P0.6/AD6

P0.5/AD5

P0.4/AD4

P0.3/AD3

P0.2/AD2

P0.1/AD1

P0.0/AD0

ALE

PSEN

P2.7/A15

P2.6/A14

P2.5/A13

P2.4/A12

P2.3/A11

P4.7

P4.6

P4.5

P4.4

P4.3

P4.2

P4.1

P4.0

N.C.

P5.0

P5.1

P5.2

P5.3

P5.4

P5.5

P3.6/WR

P3.7/RD

P1.7/T2

P1.6/CLKOUT

P1.5/T2EX

P1.4/INT2

P1.3/INT6/CC3

P1.2/INT5/CC2

P1.1/INT4/CC1

P1.0/INT3/CC0

XTAL2

XTAL1

P2.0/A8

P2.1/A9

62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80

39
38
37
36
35
34
33
32

31
30

29
28
27
26
25
24
23
22

P5.6

P5.7

P2.2/A10

AREF

RESET

C515

N.C.

Semiconductor Group

1997-08-01

C515

Table 1
Pin Definitions and Functions

Symbol

Pin Number

(P-MQFP-80)

I/O*)

Function

RESET

RESET

A low level on this pin for the duration of two machine
cycles while the oscillator is running resets the C515. A
small internal pullup resistor permits power-on reset
using only a capacitor connected to V

VAREF

Reference voltage

for the A/D converter

VAGND

Reference ground

for the A/D converter

P6.0-P6.7

12-5

Port 6

is an 8-bit unidirectional input port to the A/D converter.
Port pins can be used for digital input, if voltage levels
simultaneously meet the specifications for high/low input
voltages and for the eight multiplexed analog inputs.

*) I = Input

O = Output

C515

Semiconductor Group

1997-08-01

P3.0-P3.7

15-22

19
20
21

I/O

Port 3

is an 8-bit quasi-bidirectional I/O port with internal pullup
resistors. Port 3 pins that have 1's written to them are
pulled high by the internal pullup resistors, and in that
state can be used as inputs. As inputs, port 3 pins being

externally pulled low will source current (

, in the DC

characteristics) because of the internal pullup resistors.
Port 3 also contains the interrupt, timer, serial port and
external memory strobe pins that are used by various
options. The output latch corresponding to a secondary
function must be programmed to a one (1) for that
function to operate. The secondary functions are
assigned to the pins of port 3 as follows:
P3.0 / RxD

Receiver data input (asynch.) or data
input/output (synch.) of serial interface

P3.1 / TxD

Transmitter data output (asynch.) or
clock output (synch.) of serial interface

P3.2 / INT0

External interrupt 0 input /
timer 0 gate control input

P3.3 / INT1

External interrupt 1 input /
timer 1 gate control input

P3.4 / T0

Timer 0 counter input

P3.5 / T1

Timer 1 counter input

P3.6 / WR

WR control output; latches the data byte
from port 0 into the external data
memory

P3.7 / RD

RD control output; enables the
external data memory

*) I = Input

O = Output

Table 1
Pin Definitions and Functions (cont'd)

Symbol

Pin Number

(P-MQFP-80)

I/O*)

Function

Semiconductor Group

1997-08-01

C515

P1.0 - P1.7

31-24

27
26

25
24

I/O

Port 1

is an 8-bit quasi-bidirectional I/O port with internal pullup
resistors. Port 1 pins that have 1's written to them are
pulled high by the internal pullup resistors, and in that
state can be used as inputs. As inputs, port 1 pins being
externally pulled low will source current (

, in the DC

characteristics) because of the internal pullup resistors.
The port is used for the low-order address byte during
program verification. Port 1 also contains the interrupt,
timer, clock, capture and compare pins that are used by
various options. The output latch corresponding to a
secondary function must be programmed to a one (1) for
that function to operate (except when used for the
compare functions). The secondary functions are
assigned to the port 1 pins as follows :
P1.0 / INT3 / CC0

Interrupt 3 input /
compare 0 output /
capture 0 input

P1.1 / INT4 / CC1

Interrupt 4 input /
compare 1 output /
capture 1 input

P1.2 / INT5 / CC2

Interrupt 5 input /
compare 2 output /
capture 2 input

P1.3 / INT6 / CC3

Interrupt 6 input /
compare 3 output /
capture 3 input

P1.4 / INT2

Interrupt 2 input

P1.5 / T2EX

Timer 2 external reload /
trigger input

P1.6 / CLKOUT

System clock output

P1.7 / T2

Counter 2 input

Ground (0 V)

33, 69

Supply voltage

during normal, idle, and power-down operation.

*) I = Input

O = Output

Table 1
Pin Definitions and Functions (cont'd)

Symbol

Pin Number

(P-MQFP-80)

I/O*)

Function

C515

Semiconductor Group

1997-08-01

XTAL2

XTAL2

Input to the inverting oscillator amplifier and input to the
internal clock generator circuits.
To drive the device from an external clock source,
XTAL2 should be driven, while XTAL1 is left
unconnected.

Minimum and maximum high and low

times as well as rise/fall times specified in the AC
characteristics must be observed.

XTAL1

XTAL1
Output of the inverting oscillator amplifier.

P2.0-P2.7

38-45

I/O

Port 2
is an 8-bit quasi-bidirectional I/O port with internal pullup
resistors. Port 2 pins that have 1's written to them are
pulled high by the internal pullup resistors, and in that
state can be used as inputs. As inputs, port 2 pins being
externally pulled low will source current (

, in the DC

characteristics) because of the internal pullup resistors.
Port 2 emits the high-order address byte during fetches
from external program memory and during accesses to
external data memory that use 16-bit addresses
(MOVX @DPTR). In this application it uses strong
internal pullup resistors when issuing 1's. During
accesses to external data memory that use 8-bit
addresses (MOVX @Ri), port 2 issues the contents of
the P2 special function register.

PSEN

The Program Store Enable
output is a control signal that enables the external
program memory to the bus during external fetch
operations. It is activated every six oscillator periods,
except during external data memory accesses. The
signal remains high during internal program execution.

ALE

The Address Latch enable
output is used for latching the address into external
memory during normal operation. It is activated every six
oscillator periods, except during an external data
memory access.

*) I = Input

O = Output

Table 1
Pin Definitions and Functions (cont'd)

Symbol

Pin Number

(P-MQFP-80)

I/O*)

Function

Semiconductor Group

1997-08-01

C515

External Access Enable
When held high, the C515 executes instructions from
the internal ROM (C515-1R) as long as the program
counter is less than 2000H. When held low, the C515
fetches all instructions from ext. program memory. For
the C515-L this pin must be tied low.

P0.0-P0.7

52-59

I/O

Port 0
is an 8-bit open-drain bidirectional I/O port. Port 0 pins
that have 1's written to them float, and in that state can
be used as high-impedance inputs. Port 0 is also the
multiplexed low-order address and data bus during
accesses to external program and data memory. In this
application it uses strong internal pullup resistors when
issuing 1's. Port 0 also outputs the code bytes during
program verification in the C515-1R. External pullup
resistors are required during program verification.

P5.ß-P5.7

67-60

I/O

Port 5
is an 8-bit quasi-bidirectional I/O port with internal pullup
resistors. Port 5 pins that have 1's written to them are
pulled high by the internal pullup resistors, and in that
state can be used as inputs. As inputs, port 5 pins being
externally pulled low will source current (

, in the DC

characteristics) because of the internal pullup resistors.

P4.0-P4.7

72-74,
76-80

I/O

Port 4
is an 8-bit quasi-bidirectional I/O port with internal pull-
up resistors. Port 4 pins that have 1's written to them are
pulled high by the internal pull-up resistors, and in that
state can be used as inputs. As inputs, port 4 pins being
externally pulled low will source current (

, in the DC

characteristics) because of the internal pull-up resistors.

Power saving mode enable
A low level on this pin allows the software to enter the
power saving modes (idle mode and power down
mode). When PE is held at high level it is impossible to
enter the power saving modes. When left unconnected
this pin is pulled high by a weak internal pull-up resistor.

*) I = Input

O = Output

Table 1
Pin Definitions and Functions (cont'd)

Symbol

Pin Number

(P-MQFP-80)

I/O*)

Function

Semiconductor Group

1997-08-01

C515

Figure 4
Block Diagram of the C515C

MCB03201

OSC & Timing

CPU

Timer 0

Timer 1

Timer 2

S & H

256 x 8

RAM

ROM

Port 0

Port 1

Port 2

Port 3

Port 0

Port 1

Port 2

XTAL2

XTAL1

RESET

ALE

Support

Emulation

Logic

Programmable

Watchdog Timer

PSEN

Port 6

Port 5

Port 4

8 Bit Digital I/O

8K x 8

Baud Rate Generator

Digital Input

Port 5

Port 4

Port 3

Port 6

Interrupt Unit

USART

C515

8-Bit

A/D Converter

Reference Voltages

Programmable

AREF

AGND

8 Bit Digital I/O

Analog

MUX

C515

Semiconductor Group

1997-08-01

CPU

The C515 is efficient both as a controller and as an arithmetic processor. It has extensive facilities
for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program
memory results from an instruction set consisting of 44 % one-byte, 41 % two-byte, and 15% three-
byte instructions. With a 6 MHz crystal, 58% of the instructions are executed in 1.0

(

10 MHz: 600).

Special Function Register PSW (Address D0H)

Reset Value : 00H

Bit

Function

Carry Flag
Used by arithmetic instruction.

Auxiliary Carry Flag
Used by instructions which execute BCD operations.

General Purpose Flag

RS1
RS0

Overflow Flag
Used by arithmetic instruction.

General Purpose Flag

Parity Flag
Set/cleared by hardware after each instruction to indicate an odd/even
number of "one" bits in the accumulator, i.e. even parity.

RS1

RS0

D0H

PSW

D7H

D6H

D5H

D4H

D3H

D2H

D1H

D0H

Bit No.

MSB

LSB

RS1

RS0

Function

Bank 0 selected, data address 00H-07H

Bank 1 selected, data address 08H-0FH

Bank 2 selected, data address 10H-17H

Bank 3 selected, data address 18H-1FH

Semiconductor Group

1997-08-01

C515

Memory Organization

The C515 CPU manipulates data and operands in the following four address spaces:

up to 64 Kbyte of internal/external program memory
up to 64 Kbyte of external data memory
256 bytes of internal data memory
a 128 byte special function register area

Figure 5 illustrates the memory address spaces of the C515.

Figure 5
C515 Memory Map

MCD03202

00 H

External

FFFF H

"Code Space"

"Data Space"

"Internal Data Space"

0000

RAM

Internal

RAM

FF H

Function

Special

Direct

Address

80 H

Address

Indirect

(EA = 0)

(EA

Internal

External

FFFF

External

0000

2000 H

1FFF H

C515

Semiconductor Group

1997-08-01

Reset and System Clock

The reset input is an active low input at pin RESET. Since the reset is synchronized internally, the
RESET pin must be held low for at least two machine cycles (24 oscillator periods) while the
oscillator is running. A pullup resistor is internally connected to

to allow a power-up reset with

an external capacitor only. An automatic reset can be obtained when

is applied by connecting

the RESET pin to

via a capacitor. Figure 6 shows the possible reset circuitries.

Figure 6
Reset Circuitries

MCS03203

RESET

C515

RESET

C515

C515

Semiconductor Group

1997-08-01

Enhanced Hooks Emulation Concept

The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative
way to control the execution of C500 MCUs and to gain extensive information on the internal
operation of the controllers. Emulation of on-chip ROM based programs is possible, too.

Each production chip has built-in logic for the support of the Enhanced Hooks Emulation Concept.
Therefore, no costly bond-out chips are necessary for emulation. This also ensure that emulation
and production chips are identical.

The Enhanced Hooks Technology

, which requires embedded logic in the C500 allows the C500

together with an EH-IC to function similar to a bond-out chip. This simplifies the design and reduces
costs of an ICE-system. ICE-systems using an EH-IC and a compatible C500 are able to emulate
all operating modes of the different versions of the C500 microcontrollers. This includes emulation
of ROM, ROM with code rollover and ROMless modes of operation. It is also able to operate in
single step mode and to read the SFRs after a break.

Figure 8
Basic C500 MCU Enhanced Hooks Concept Configuration

Port 0, port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks
Emulation Concept to control the operation of the device during emulation and to transfer
informations about the programm execution and data transfer between the external emulation
hardware (ICE-system) and the C500 MCU.

1 "Enhanced Hooks Technology" is a trademark and patent of Metalink Corporation licensed to Siemens.

MCS03280

SYSCON

PCON
TCON

RESET

PSEN

ALE

Port

I/O Ports

Optional

Port 3

Port 1

C500

MCU

Interface Circuit

Enhanced Hooks

RPort 0

RPort 2

RTCON

RPCON

RSYSCON

TEA

TALE TPSEN

EH-IC

Target System Interface

ICE-System Interface

to Emulation Hardware

Semiconductor Group

1997-08-01

C515

Special Function Registers

The registers, except the program counter and the four general purpose register banks, reside in
the special function register area.

The 59 special function registers (SFRs) include pointers and registers that provide an interface
between the CPU and the other on-chip peripherals. All SFRs with addresses where address bits 0-
2 are 0 (e.g. 80H, 88H, 90H, 98H, ..., F8H, FFH) are bitaddressable.
The SFRs of the C515 are listed in table 2 and table 3. In table 2 they are organized in groups
which refer to the functional blocks of the C515. Table 3 illustrates the contents of the SFRs in
numeric order of their addresses.

C515

Semiconductor Group

1997-08-01

Table 2
Special Function Registers - Functional Blocks

Block

Symbol

Name

Address

Contents after
Reset

CPU

ACC
B
DPH
DPL
PSW
SP
SYSCON

Accumulator
B-Register
Data Pointer, High Byte
Data Pointer, Low Byte
Program Status Word Register
Stack Pointer
System Control Register

E0H

F0H

83H
82H
D0H

81H
B1H

00H
00H
00H
00H
00H
07H
XX1X XXXXB

A/D-
Converter

ADCON

ADDAT
DAPR

A/D Converter Control Register
A/D Converter Data Register
A/D Converter Program Register

D8H

D9H
DAH

00X0 0000B

00H
00H

Interrupt
System

IEN0

IEN1

IP0

IP1
IRCON
TCON

T2CON

SCON

Interrupt Enable Register 0
Interrupt Enable Register 1
Interrupt Priority Register 0
Interrupt Priority Register 1
Interrupt Request Control Register
Timer Control Register
Timer 2 Control Register
Serial Channel Control Register

A8H

B8H

A9H
B9H
C0H

88H

C8H

98H

00H
00H
X000 0000B

XX00 0000B

00H
00H
00H
00H

Timer 0/
Timer 1

TCON

TH0
TH1
TL0
TL1
TMOD

Timer 0/1 Control Register
Timer 0, High Byte
Timer 1, High Byte
Timer 0, Low Byte
Timer 1, Low Byte
Timer Mode Register

88H

8CH
8DH
8AH
8BH
89H

00H
00H
00H
00H
00H
00H

Compare/
Capture
Unit /
Timer 2

CCEN
CCH1
CCH2
CCH3
CCL1
CCL2
CCL3
CRCH
CRCL
TH2
TL2
T2CON

Comp./Capture Enable Reg.
Comp./Capture Reg. 1, High Byte
Comp./Capture Reg. 2, High Byte
Comp./Capture Reg. 3, High Byte
Comp./Capture Reg. 1, Low Byte
Comp./Capture Reg. 2, Low Byte
Comp./Capture Reg. 3, Low Byte
Com./Rel./Capt. Reg. High Byte
Com./Rel./Capt. Reg. Low Byte
Timer 2, High Byte
Timer 2, Low Byte
Timer 2 Control Register

C1H
C3H
C5H
C7H
C2H
C4H
C6H
CBH
CAH
CDH
CCH
C8H

00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H

1) Bit-addressable special function registers
2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.
3) "X" means that the value is undefined and the location is reserved

Semiconductor Group

1997-08-01

C515

Ports

P0
P1
P2
P3
P4
P5
P6

Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6, Analog/Digital Input

80H

90H

A0H

B0H

E8H

F8H

DBH

FFH
FFH
FFH
FFH
FFH
FFH

Serial
Channel

ADCON

PCON

SBUF
SCON

A/D Converter Control Register
Power Control Register
Serial Channel Buffer Register
Serial Channel Control Register

D8H

87H
99H
98H

00X0 0000B

00H

XXH

00H

Watchdog IEN0

IEN1

IP0

2))

Interrupt Enable Register 0
Interrupt Enable Register 1
Interrupt Priority Register 0

A8H

B8H

A9H

00H
00H
X000 0000B

3))

Power
Saving
Modes

PCON

Power Control Register

87H

00H

Table 2
Special Function Registers - Functional Blocks (cont'd)

Block

Symbol

Name

Address

Contents after
Reset

C515

Semiconductor Group

1997-08-01

Table 3
Contents of the SFRs, SFRs in numeric order of their addresses

Addr Register Content

after
Reset

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

80H

FFH

81H SP

07H

82H DPL

00H

83H DPH

00H

87H PCON

00H

SMOD PDS

IDLS

GF1

GF0

PDE

IDLE

88H

TCON

00H

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

89H TMOD

00H

GATE

C/T

GATE

C/T

8AH TL0

00H

8BH TL1

00H

8CH TH0

00H

8DH TH1

00H

90H

FFH

CLK-
OUT

T2EX

INT2

INT6

INT5

INT4

INT3

98H

SCON

00H

SM0

SM1

SM2

REN

TB8

RB8

99H SBUF

XXH

A0H

FFH

A8H

IEN0

00H

EAL

WDT

ET2

ET1

EX1

ET0

EX0

A9H IP0

X000-
0000B

WDTS

B0H

FFH

INT1

INT0

TxD

RxD

B1H SYSCON XX1X-

XXXXB

EALE

B8H

IEN1

00H

EXEN2 SWDT

EX6

EX5

EX4

EX3

EX2

EADC

B9H IP1

XX00-
0000B

C0H

IRCON

00H

EXF2

TF2

IEX6

IEX5

IEX4

IEX3

IEX2

IADC

C1H CCEN

00H

COCA
H3

COCAL
3

COCA
H2

COCAL
2

COCA
H1

COCAL
1

COCA
H0

COCAL
0

C2H CCL1

00H

1) X means that the value is undefined and the location is reserved
2) Bit-addressable special function registers

Semiconductor Group

1997-08-01

C515

C3H CCH1

00H

C4H CCL2

00H

C5H CCH2

00H

C6H CCL3

00H

C7H CCH3

00H

C8H

T2CON

00H

T2PS

I3FR

I2FR

T2R1

T2R0

T2CM

T2I1

T2I0

CAH CRCL

00H

CBH CRCH

00H

CCH TL2

00H

CDH TH2

00H

D0H

PSW

00H

RS1

RS0

D8H

ADCON

00X0-
0000B

CLK

BSY

ADM

MX2

MX1

MX0

D9H ADDAT

00H

DAH DAPR

00H

DBH P6

E0H

ACC

00H

E8H

FFH

F0H

00H

F8H

FFH

1) X means that the value is undefined and the location is reserved
2) Bit-addressable special function registers

Table 3
Contents of the SFRs, SFRs in numeric order of their addresses (cont'd)

Addr Register Content

after
Reset

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

C515

Semiconductor Group

1997-08-01

Digital I/O Ports

The C515 allows for digital I/O on 48 lines grouped into 6 bidirectional 8-bit ports. Each port bit
consists of a latch, an output driver and an input buffer. Read and write accesses to the I/O ports P0
through P5 are performed via their corresponding special function registers P0 to P5.

The output drivers of port 0 and 2 and the input buffers of port 0 are also used for accessing external
memory. In this application, port 0 outputs the low byte of the external memory address, time-
multiplexed with the byte being written or read. Port 2 outputs the high byte of the external memory
address when the address is 16 bits wide. Otherwise, the port 2 pins continue emitting the P2 SFR
contents.

Analog Input Ports

Ports 6 is available as input port only and provides two functions. When used as digital inputs, the
corresponding SFR P6 contains the digital value applied to the port 6 lines. When used for analog
inputs the desired analog channel is selected by a three-bit field in SFR ADCON. Of course, it
makes no sense to output a value to these input-only ports by writing to the SFR P6. This will have
no effect.

lf a digital value is to be read, the voltage levels are to be held within the input voltage specifications
(

). Since P6 is not bit-addressable, all input lines of P6 are read at the same time by byte

instructions.

Nevertheless, it is possible to use port 6 simultaneously for analog and digital input. However, care
must be taken that all bits of P6 that have an undetermined value caused by their analog function
are masked.

Semiconductor Group

1997-08-01

C515

Timer / Counter 0 and 1

Timer/Counter 0 and 1 can be used in four operating modes as listed in table 4 :

In the "timer" function (C/T = `0') the register is incremented every machine cycle. Therefore the
count rate is

OSC

/12.

In the "counter" function the register is incremented in response to a 1-to-0 transition at its
corresponding external input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a
falling edge the max. count rate is

OSC

/24. External inputs INT0 and INT1 (P3.2, P3.3) can be

programmed to function as a gate to facilitate pulse width measurements. Figure 9 illustrates the
input clock logic.

Figure 9
Timer/Counter 0 and 1 Input Clock Logic

Table 4
Timer/Counter 0 and 1 Operating Modes

Mode

Description

TMOD

Input Clock

internal

external (max)

8-bit timer/counter with a
divide-by-32 prescaler

OSC

/12x32

OSC

/24x32

16-bit timer/counter

OSC

/12

OSC

/24

8-bit timer/counter with
8-bit autoreload

Timer/counter 0 used as one
8-bit timer/counter and one
8-bit timer
Timer 1 stops

OSC

/12

MCS01768

OSC

C/T

TMOD

Control

Timer 0/1
Input Clock

TCON

TR 0/1

Gate

TMOD

P3.4/T0
P3.5/T1
max

P3.2/INT0
P3.3/INT1

OSC

/24

C515

Semiconductor Group

1997-08-01

Timer/Counter 2 with Compare/Capture/Reload

The timer 2 of the C515 provides additional compare/capture/reload features. which allow the
selection of the following operating modes:

Compare

: up to 4 PWM signals with 16-bit/500 ns resolution

Capture

: up to 4 high speed capture inputs with 500 ns resolution

Reload

: modulation of timer 2 cycle time

The block diagram in figure 10 shows the general configuration of timer 2 with the additional
compare/capture/reload registers. The I/O pins which can used for timer 2 control are located as
multifunctional port functions at port 1.

Figure 10
Timer 2 Block Diagram

MCB03205

Comparator

CCL3/CCH3

Capture

Input/

Output

Control

P1.0/
INT3/
CC0

CC1

INT4/

P1.1/

CC2

INT5/

P1.2/

CC3

INT6/

P1.2/

CCL2/CCH2

Comparator

CCL1/CCH1

Comparator

CRCL/CRCH

Comparator

Bit

16 Bit

OSC

÷ 12

÷ 24

OSC

T2PS

Sync.

P1.7/
T2

T2EX

P1.5/

Sync.

T2I1

T2I0

Timer 2

TH2

TL2

TF2

Reload

EXEN2

Reload

EXF2

Interrupt
Request

Compare

Semiconductor Group

1997-08-01

C515

Timer 2 Operating Modes

The timer 2, which is a 16-bit-wide register, can operate as timer, event counter, or gated timer. A
roll-over of the count value in TL2/TH2 from all 1's to all 0's sets the timer overflow flag TF2 in SFR
IRCON, which can generate an interrupt. The bits in register T2CON are used to control the timer
2 operation.

Timer Mode: In timer function, the count rate is derived from the oscillator frequency. A prescaler
offers the possibility of selecting a count rate of 1/12 or 1/24 of the oscillator frequency.

Gated Timer Mode: In gated timer function, the external input pin T2 (P1.7) functions as a gate to
the input of timer 2. lf T2 is high, the internal clock input is gated to the timer. T2 = 0 stops the
counting procedure. This facilitates pulse width measurements. The external gate signal is sampled
once every machine cycle.

Event Counter Mode: In the event counter function. the timer 2 is incremented in response to a 1-
to-0 transition at its corresponding external input pin T2 (P1.7). In this function, the external input is
sampled every machine cycle. Since it takes two machine cycles (24 oscillator periods) to recognize
a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. There are no
restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled
at least once before it changes, it must be held for at least one full machine cycle.

Reload of Timer 2: Two reload modes are selectable:
In mode 0, when timer 2 rolls over from all 1's to all 0's, it not only sets TF2 but also causes the timer
2 registers to be loaded with the 16-bit value in the CRC register, which is preset by software.
In mode 1, a 16-bit reload from the CRC register is caused by a negative transition at the correspon-
ding input pin P1.5/T2EX. This transition will also set flag EXF2 if bit EXEN2 in SFR IEN1 has been
set.

C515

Semiconductor Group

1997-08-01

Timer 2 Compare Modes

The compare function of a timer/register combination operates as follows : the 16-bit value stored
in a compare or compare/capture register is compared with the contents of the timer register; if the
count value in the timer register matches the stored value, an appropriate output signal is generated
at a corresponding port pin and an interrupt can be generated.

Compare Mode 0

In compare mode 0, upon matching the timer and compare register contents, the output signal
changes from low to high. lt goes back to a low level on timer overflow. As long as compare mode
0 is enabled, the appropriate output pin is controlled by the timer circuit only and writing to the port
will have no effect. Figure 11 shows a functional diagram of a port circuit when used in compare
mode 0. The port latch is directly controlled by the timer overflow and compare match signals. The
input line from the internal bus and the write-to-latch line of the port latch are disconnected when
compare mode 0 is enabled.

Figure 11
Port Latch in Compare Mode 0

MCS02661

Latch

Port

CLK

Port

Read Pin

Read Latch

Port Circuit

Internal
Bus

Latch

Write to

Compare Reg.

Compare Register

Circuit

Comparator

Timer Register

Timer Circuit

Compare
Match

Overflow

Timer

16 Bit

Bit

Semiconductor Group

1997-08-01

C515

Compare Mode 1

If compare mode 1 is enabled and the software writes to the appropriate output latch at the port, the
new value will not appear at the output pin until the next compare match occurs. Thus, it can be
chosen whether the output signal has to make a new transition (1-to-0 or 0-to-1, depending on the
actual pin-level) or should keep its old value at the time when the timer value matches the stored
compare value.

In compare mode 1 (see figure 12) the port circuit consists of two separate latches. One latch
(which acts as a "shadow latch") can be written under software control, but its value will only be
transferred to the port latch (and thus to the port pin) when a compare match occurs.

Figure 12
Compare Function in Compare Mode 1

MCS02662

Latch

Port

CLK

Read Pin

CLK

Shadow

Latch

Read Latch

Port Circuit

Internal
Bus

Latch

Write to

Compare Reg.

Compare Register

Circuit

Comparator

Timer Register

Timer Circuit

Compare
Match

Port

16 Bit

C515

Semiconductor Group

1997-08-01

Serial Interface (USART)

The serial port is full duplex and can operate in four modes (one synchronous mode, three
asynchronous modes) as illustrated in table 5. The possible baudrates can be calculated using the
formulas given in table 5.

For clarification some terms regarding the difference between "baud rate clock" and "baud rate"
should be mentioned. In the asynchronous modes the serial interfaces require a clock rate which is
16 times the baud rate for internal synchronization. Therefore, the baud rate generators/timers have
to provide a "baud rate clock" (output signal in figure 13 to the serial interface which - there divided
by 16 - results in the actual "baud rate". Further, the abbrevation f

OSC

refers to the oscillator

frequency (crystal or external clock operation).

The variable baud rates for modes 1 and 3 of the serial interface can be derived from either timer 1
or from the system clock (see figure 13).

Table 5
USART Operating Modes

Mode

SCON

Description

SM0

SM1

Shift register mode
Serial data enters and exits through R

D/ T

D outputs the shift

clock; 8-bit are transmitted/received (LSB first); fixed baud rate

8-bit UART, variable baud rate
10 bits are transmitted (through T

D) or received (at R

9-bit UART, fixed baud rate
11 bits are transmitted (through T

D) or received (at R

9-bit UART, variable baud rate
Like mode 2

Semiconductor Group

1997-08-01

C515

Figure 13
Block Diagram of Baud Rate Generation for the Serial Interface

Table 6 below lists the values/formulas for the baud rate calculation of the serial interface with its
dependencies of the control bits BD and SMOD.

Table 6
Serial Interface - Baud Rate Dependencies

Serial Interface 0
Operating Modes

Active Control Bits Baud Rate Calculation

SMOD

Mode 0 (Shift Register)

OSC

/ 12

Mode 1 (8-bit UART)
Mode 3 (9-bit UART)

Controlled by timer 1 overflow :
(2

SMOD

timer 1 overflow rate) / 32

Controlled by system clock divider circuits :
(2

SMOD

OSC

) / 2496

Mode 2 (9-bit UART)

0
1

OSC

/ 64

OSC

/ 32

MCB03206

Rate

OSC

(SMOD)

Baud

Clock

PCON.7

÷ 2

(SM0/

SM1)

SCON.7
SCON.6

Only one mode
can be selected

ADCON.7

(BD)

0
1

Timer

Mode

Note: The switch configuration shows the reset state.

Mode

Mode 1

Overflow

÷ 6

÷ 39

C515

Semiconductor Group

1997-08-01

8-Bit A/D Converter

The C515 provides an A/D converter with the following features:

Eight multiplexed input channels
The possibility of using the analog inputs (port 6) also as digital inputs
Programmable internal reference voltages (16 steps each) via resistor array
8-bit resolution within the selected reference voltage range
Internal start-of-conversion trigger
Interrupt request generation after each conversion

For the A/D conversion, the method of successive approximation via capacitor array is used. The
externally applied reference voltage range has to be held on a fixed value within the specifications
(see section "A/D Converter Characteristics" in this data sheet). The internal reference voltages can
be varied to reduce the reference voltage range of the A/D converter and thus to achieve a higher
resolution. Figure 14 shows a block diagram of the A/D converter.

Semiconductor Group

1997-08-01

C515

Figure 14
A/D Converter Block Diagram

MCB03207

.2
.3
.4
.5
.6

MSB

(D9 )

A/D

ADDAT

Single/
Continuous
Mode

Start of
Conversion

MUX

S & H

÷ 4

Conversion Clock

ADC

OSC

Port 6

Shaded bit locations are not used in ADC-functions.

Input Clock

Write to

Converter

Internal

Bus

Internal

Bus

AGND

AREF

DAPR (DA )

DAPR

INTAREF

INTAGND

Internal Reference Voltages

Programming of

INTAREF

INTAGND

Programming of

LBS

EX5

IEX5

BSY

IEX6

EX6

IADC

MX0

MX2

IEX3

ADM

IEX4

MX1

EADC

EX3

EX4

ECAN

ADCON (D8 )

IRCON (C0 )

CLK

EXF2

TF2

IEN1 (B8 )

EXEN2 SWDT

C515

Semiconductor Group

1997-08-01

Interrupt System

The C515 provides 12 interrupt sources with four priority levels. Five interrupts can be generated by
the on-chip peripherals (timer 0, timer 1, timer 2, A/D converter, and serial interface) and seven
interrupts may be triggered externally (P3.2/INT0, P3.3/INT1, P1.4/INT2, P1.0/INT3, P1.1/INT4,
P1.2/INT5, P1.3/INT6).

This chapter shows the interrupt structure, the interrupt vectors and the interrupt related special
function registers. Figure 15 and 16 give a general overview of the interrupt sources and illustrate
the request and the control flags which are described in the next sections.

Semiconductor Group

1997-08-01

C515

Figure 15
Interrupt Request Sources (Part 1)

MCS03208

Bit addressable

Request Flag is
cleared by hardware

IP1.0

0003

TCON.1

IEN0.0

IE0

EX0

P3.2/

IT0

TCON.0

IP0.0

Highest

Priority Level

EADC

IADC

IEN1.0

IRCON.0

0043 H

A/D Converter

IP1.2

IP0.2

Timer 0

000B

TCON.5

IEN0.1

TF0

ET0

Overflow

INT0

INT2

T2CON.5

I2FR

P1.4/

EX2

IEX2

IEN1.1

IRCON.1

0053 H

Lowest

Priority Level

EAL

IEN0.7

Polling Sequence

004B H

IP0.1

IP1.1

INT1

TCON.2

IT1

P3.3/

EX1

IE1

IEN0.2

TCON.3

0013 H

IRCON.2

IEN1.2

IEX3

EX3

P1.0/

I3FR

T2CON.6

INT3
CC0

C515

Semiconductor Group

1997-08-01

Figure 16
Interrupt Request Sources (Part 2)

MCS03209

Bit addressable

Request Flag is
cleared by hardware

IP1.3

001B

IP0.3

Highest

Priority Level

EX4

IEX4

IEN1.3

IRCON.3

005B H

IP1.5

IP0.5

Timer 1

0023

TCON.7

IEN0.3

TF1

ET1

Overflow

IEN0.4

SCON.0

006B H

Lowest

Priority Level

EAL

IEN0.7

Polling Sequence

0063 H

IP0.4

IP1.4

T2EX

P1.5/

ET2

IEN0.5

002B H

P1.3/
INT6
CC3

CC1

INT4

P1.1/

SCON.1

USART

P1.2/
INT5
CC2

IRCON.4

IEN1.4

IEX5

EX5

IRCON.6

TF2

EXF2

IRCON.7

IEN1.7

EXEN2

EX6

IEX6

IEN1.5

IRCON.5

Overflow

Timer

< 1

Semiconductor Group

1997-08-01

C515

Table 7
Interrupt Source and Vectors

Interrupt Source

Interrupt Vector Address

Interrupt Request Flags

External Interrupt 0

0003H

IE0

Timer 0 Overflow

000BH

TF0

External Interrupt 1

0013H

IE1

Timer 1 Overflow

001BH

TF1

Serial Channel

0023H

RI / TI

Timer 2 Overflow / Ext. Reload

002BH

TF2 / EXF2

A/D Converter

0043H

IADC

External Interrupt 2

004BH

IEX2

External Interrupt 3

0053H

IEX3

External Interrupt 4

005BH

IEX4

External Interrupt 5

0063H

IEX5

External Interrupt 6

006BH

IEX6

C515

Semiconductor Group

1997-08-01

Fail Save Mechanisms

As a means of graceful recovery from software or hardware upset a watchdog timer is provided in
the C515. lf the software fails to clear the watchdog timer at least every 65532

s (at 12 MHz clock

rate), an internal hardware reset will be initiated. The software can be designed such that the
watchdog times out if the program does not progress properly. The watchdog will also time out if the
software error was due to hardware-related problems. This prevents the controller from
malfunctioning for longer than 65 ms if a 12-MHz oscillator is used. Figure 17 shows the block
diagram of the watchdog timer unit.

Figure 17
Block Diagram of the Watchdog Timer

The watchdog timer can be started by software (bit SWDT) but it cannot be stopped during active
mode of the C515. lf the software fails to clear the watchdog in time, an internally generated
watchdog reset is entered at the counter state FFFCH and lasts four instruction cycles. This internal
reset differs from an external reset only to the extent that the watchdog timer is not disabled. Bit
WDTS (was set by starting WDT) allows the software to examine from which source the reset was
initiated. lf it is set, the reset was caused by a watchdog timer overflow.

MCB03210

Control Logic

WDT Reset if WDT count is between

IEN1

IEN0

)

( B8 H

(

)

16-Bit Watchdog Timer

IP0 ( A9 H)

WDT

SWDT

External HW Reset

WDTS

OSC

÷ 12

Reset

FFFC H

FFFF

Semiconductor Group

1997-08-01

C515

Power Saving Modes

The C515 provides two basic power saving modes, the idle mode and the power down mode.
Additionally, a slow down mode is available. This power saving mode reduces the internal clock
rate in normal operating mode and it can be also used for further power reduction in idle mode.

Idle mode

The CPU is gated off from the oscillator. All peripherals are still provided with the clock and
are able to work. Idle mode is entered by software and can be left by an interrupt or reset.

Power down mode

The operation of the C515 is completely stopped and the oscillator is turned off. This mode is
used to save the contents of the internal RAM with a very low standby current. Power down
mode is entered by software and can be left by reset or by a short low pulse at pin P3.2/INT0.

Slow-down mode

The controller keeps up the full operating functionality, but its normal clock frequency is
internally divided by 8. This slows down all parts of the controller, the CPU and all peripherals,
to 1/8 th of their normal operating frequency. Slowing down the frequency significantly
reduces power consumption.

Table 8 gives a general overview of the entry and exit procedures of the power saving modes.

In the power down mode of operation,

can be reduced to minimize power consumption. It must

be ensured, however, that

is not reduced before the power down mode is invoked, and that

is restored to its normal operating level, before the power down mode is terminated.

Table 8
Power Saving Modes Overview

Mode

Entering
2-Instruction
Example

Leaving by

Remarks

Idle mode

ORL PCON, #01H
ORL PCON, #20H

Occurrence of an
interrupt from a
peripheral unit

CPU clock is stopped;
CPU maintains their data;
peripheral units are active (if
enabled) and provided with
clock

Hardware Reset

Power Down Mode

ORL PCON, #02H
ORL PCON, #40H

Hardware Reset

Oscillator is stopped;
contents of on-chip RAM and
SFR's are maintained;

Slow Down Mode

In normal mode :
ORL PCON,#10H

ANL PCON,#0EFH
or
Hardware Reset

Internal clock rate is reduced
to 1/8 of its nominal frequency

With idle mode :
ORL PCON,#01H
ORL PCON, #30H

Occurrence of an
interrupt from a
peripheral unit

CPU clock is stopped;
CPU maintains their data;
peripheral units are active (if
enabled) and provided with 1/8
of its nominal frequency

Hardware reset

C515

Semiconductor Group

1997-08-01

Absolute Maximum Ratings

Ambient temperature under bias (

) ......................................................... 40 to 110

Storage temperature (

stg

) .......................................................................... 65

C to 150

Voltage on

pins with respect to ground (

) ....................................... 0.5 V to 6.5 V

Voltage on any pin with respect to ground (

) ......................................... 0.5 V to

+0.5 V

Input current on any pin during overload condition..................................... 10 mA to 10 mA
Absolute sum of all input currents during overload condition ..................... I 100 mA I
Power dissipation........................................................................................ TBD

Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent

damage of the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for longer
periods may affect device reliability. During overload conditions (

) the

Voltage on

pins with respect to ground (

) must not exceed the values defined by the

absolute maximum ratings.

Semiconductor Group

1997-08-01

C515

DC Characteristics

= 5 V + 10%, 15%;

= 0 V

= 0 to 70

for the SAB-C515-1RM

= 40 to 85

for the SAF-C515-1RM

= 40 to 110

for the SAH-C515-1RM

Notes on next page

Parameter

Symbol

Limit Values

Unit

Test Condition

min.

max.

Input low voltages
all except EA
EA pin

IL1

0.5
0.5

0.2

- 0.1

0.2

- 0.3

V
V

Input high voltages
all except XTAL2 and RESET
XTAL2 pin
RESET pin

IH1

IH2

0.2

+ 0.9

0.7

0.6

+ 0.5

V
V
V

Output low voltages
Ports 1, 2, 3, 4, 5
Port 0, ALE, PSEN

OL1

0.45
0.45

V
V

= 1.6 mA

= 3.2 mA

Output high voltages
Ports 1, 2, 3, 4, 5

Port 0 in external bus mode,
ALE, PSEN

OH2

2.4
0.9

V
V
V
V

= 80

= 10

= 800

= 80

Logic 0 input current
Ports 1, 2, 3, 4, 5

= 0.45 V

Logical 0-to-1 transition current
Ports 1, 2, 3, 4, 5

650

= 2 V

Input leakage current
Port 0, AIN0-7 (Port 6), EA

0.45 <

Input low current
to RESET for reset
XTAL2
PE

LI2

LI3

LI4

100
15
20

= 0.45 V

Pin capacitance

= 1 MHz,

= 25

Overload current

7) 8)

C515

Semiconductor Group

1997-08-01

Power Supply Current

1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the

of ALE

and ports1, 3, 4, and 5. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins
when these pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF),
the noise pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a schmitt-
trigger, or use an address latch with a schmitt-trigger strobe input.

2) Capacitive loading on ports 0 and 2 may cause the

on ALE and PSEN to momentarily fall below the

0.9

specification when the address lines are stabilizing.

(power-down mode) is measured under following conditions:

EA = Port 0 = Port 6 =

; RESET =

; XTAL1 = N.C.; PE = XTAL2 =

;

AGND

;

AREF

; all

other pins are disconnected. The typical

current is measured at

= 5 V.

(active mode) is measured with:

XTAL2 driven with

CLCH

CHCL

= 5 ns ,

+ 0.5 V,

0.5 V; XTAL1 = N.C.;

EA = Port 0 = Port 6 =

; RESET =

; all other pins are disconnected.

(idle mode) is measured with all output pins disconnected and with all peripherals disabled;

XTAL2 driven with

CLCH

CHCL

= 5 ns,

+ 0.5 V,

0.5 V; XTAL1 = N.C.;

EA = Port 0 = Port 6 =

; RESET =

; all other pins are disconnected;

(active mode with slow-down mode) is measured : TBD

8) Overload conditions occur if the standard operating conditions are exceeded, ie. the voltage on any pin

exceeds the specified range (i.e.

+ 0.5 V or

- 0.5 V). The supply voltage

and

must

remain within the specified limits. The absolute sum of input currents on all port pins may not exceed 50 mA.

9) Not 100% tested, guaranteed by design characterization

10)The typical

values are periodically measured at

= +25

C but not 100% tested.

Parameter

Symbol

Limit Values

Unit Test Condition

typ.

max.

10)

Active mode

16 MHz
24 MHz

13.7
19.6

18.2
25

mA
mA

Idle mode

16 MHz
24 MHz

6.9
9.1

9.6
12.8

mA
mA

Active mode with
slow-down enabled

16 MHz
24 MHz

4.9
6.5

7.0
8.8

mA
mA

Power-down mode

= 2...5.5 V

Semiconductor Group

1997-08-01

C515

Figure 18
ICC Diagram

MCD03282

OSC

MHz

Active Mode

Idle Mode

Active Mode with Slow Down

= 0.68 x + 2.8

OSC

CC typ

= 0.85 x + 4.6

CC max

OSC

= 0.39 x + 3.4

= 0.28 x + 2.4

CC max

CC typ

OSC

= 0.18 x + 2.0
= 0.23 x + 3.3

CC max

CC typ

OSC

Active mode

Idle mode

Active mode with slow-down

is the oscillator frequency in MHz. values are given in mA.

OSC

CC typ

CC max

Active Mode

Idle Mode

C515

Semiconductor Group

1997-08-01

A/D Converter Characteristics

= 5 V

10%, 15%;

= 0

= 0 to 70

for the SAB-C515-1RM

= 40 to 85

for the SAF-C515-1RM

= 40 to 110

for the SAH-C515-1RM

0.25 V

AREF

0.25

;

0.2 V

AGND

+ 0.2 V;

IntAREF

IntAGND

1 V;

Notes:

1) V

AIN

may exceed V

AGND

or V

AREF

up to the absolute maximum ratings. However, the conversion result in

these cases will be 00

or FF

, respectively.

2) During the sample time the input capacitance

AIN

can be charged/discharged by the external source. The

internal resistance of the analog source must allow the capacitance to reach their final voltage level within t

After the end of the sample time t

, changes of the analog input voltage have no effect on the conversion

result.

3) This parameter includes the sample time t

and the conversion time t

. The values for the conversion clock

ADC

is always 8 x t

4) T

is tested at V

AREF

= 5.0 V, V

AGND

= 0 V, V

= 4.9 V. It is guaranteed by design characterization for all

other voltages within the defined voltage range.
If an overload condition occurs on maximum 2 not selected analog input pins and the absolute sum of input
overload currents on all analog input pins does not exceed 10 mA, an additional conversion error of 1/2 LSB
is permissible.

5) During the conversion the ADC's capacitance must be repeatedly charged or discharged. The internal

resistance of the reference source must allow the capacitance to reach their final voltage level within the
indicated time. The maximum internal resistance results from the programmed conversion timing.

6) Not 100% tested, but guaranteed by design characterization.

Parameter

Symbol

Limit Values

Unit

Test Condition

min.

max.

Analog input voltage

AIN

AGND

0.2

AREF

0.2

A/D converter input clock

2 x

CLCL

Sample time

16 x

Conversion cycle time

ADCC

80 x

Total unadjusted error

LSB

IntAREF

AREF

= V

IntAGND

AGND

= V

Internal resistance of
reference voltage source

AREF

8 x

/500

- 1

in [ns]

5) 6)

Internal resistance of
analog source

ASRC

/ 500 - 1

in [ns]

2) 6)

ADC input capacitance

AIN

Semiconductor Group

1997-08-01

C515

AC Characteristics (16 MHz)

= 5 V + 10%, 15%;

= 0 V

= 0 to 70

for the SAB-C515-1RM

= 40 to 85

for the SAF-C515-1RM

= 40 to 110

for the SAH-C515-1RM

(

for port 0, ALE and PSEN outputs = 100 pF;

for all other outputs = 80 pF)

Program Memory Characteristics

Interfacing the C515 to devices with float times up to 75 ns is permissible. This limited bus contention will not
cause any damage to port 0 drivers.

CLKOUT Characteristics

Parameter

Symbol

Limit Values

Unit

16 MHz

Clock

Variable Clock

CLCL

= 1 MHz to 16 MHz

min.

max.

min.

max.

ALE pulse width

LHLL

CLCL

Address setup to ALE

AVLL

CLCL

Address hold after ALE

LLAX

CLCL

ALE low to valid instr in

LLIV

150

CLCL

100

ALE to PSEN

LLPL

CLCL

PSEN pulse width

PLPH

153

CLCL

PSEN to valid instr in

PLIV

CLCL

100

Input instruction hold after PSEN

PXIX

Input instruction float after PSEN

PXIZ

CLCL

Address valid after PSEN

PXAV

CLCL

Address to valid instr in

AVIV

198

CLCL

115

Address float to PSEN

AZPL

Parameter

Symbol

Limit Values

Unit

16 MHz

Clock

Variable Clock

CLCL

= 1 MHz to 16 MHz

min.

max.

min.

max.

ALE to CLKOUT

LLSH

398

CLCL

CLKOUT high time

SHSL

CLCL

CLKOUT low time

SLSH

585

CLCL

CLKOUT low to ALE high

SLLH

103

CLCL

+ 40

C515

Semiconductor Group

1997-08-01

AC Characteristics (16 MHz) (cont'd)

External Data Memory Characteristics

External Clock Drive Characteristics

Parameter

Symbol

Limit Values

Unit

16 MHz

Clock

Variable Clock

CLCL

= 1 MHz to 16 MHz

min.

max.

min.

max.

RD pulse width

RLRH

275

CLCL

100

WR pulse width

WLWH

275

CLCL

100

Address hold after ALE

LLAX2

CLCL

RD to valid data in

RLDV

148

CLCL

165

Data hold after RD

RHDX

Data float after RD

RHDZ

CLCL

ALE to valid data in

LLDV

350

CLCL

150

Address to valid data in

AVDV

398

CLCL

165

ALE to WR or RD

LLWL

138

238

CLCL

+ 50

Address valid to WR or RD

AVWL

120

CLCL

130

WR or RD high to ALE high

WHLH

103

CLCL

+ 40

Data valid to WR transition

QVWX

CLCL

Data setup before WR

QVWH

288

CLCL

150

Data hold after WR

WHQX

CLCL

Address float after RD

RLAZ

Parameter

Symbol

Limit Values

Unit

Variable Clock

Freq. = 1 MHz to 16 MHz

min.

max.

Oscillator period

CLCL

62.5

1000

High time

CHCX

CLCL

CLCX

Low time

CLCX

CLCL

CHCX

Rise time

CLCH

Fall time

CHCL

Semiconductor Group

1997-08-01

C515

AC Characteristics (24 MHz)

= 5 V + 10%, 15%;

= 0 V

= 0 to 70

for the SAB-C515-1RM

= 40 to 85

for the SAF-C515-1RM

= 40 to 110

for the SAH-C515-1RM

(

for port 0, ALE and PSEN outputs = 100 pF;

for all other outputs = 80 pF)

Program Memory Characteristics

Interfacing the C515 to devices with float times up to 37 ns is permissible. This limited bus contention will not
cause any damage to port 0 drivers.

CLKOUT Characteristics

Parameter

Symbol

Limit Values

Unit

24 MHz

Clock

Variable Clock

CLCL

= 1 MHz to 24 MHz

min.

max.

min.

max.

ALE pulse width

LHLL

CLCL

Address setup to ALE

AVLL

CLCL

Address hold after ALE

LLAX

CLCL

ALE low to valid instr in

LLIV

CLCL

ALE to PSEN

LLPL

CLCL

PSEN pulse width

PLPH

CLCL

PSEN to valid instr in

PLIV

CLCL

Input instruction hold after PSEN

PXIX

Input instruction float after PSEN

PXIZ

CLCL

Address valid after PSEN

PXAV

CLCL

Address to valid instr in

AVIV

148

CLCL

Address float to PSEN

AZPL

Parameter

Symbol

Limit Values

Unit

24 MHz

Clock

Variable Clock

CLCL

= 1 MHz to 24 MHz

min.

max.

min.

max.

ALE to CLKOUT

LLSH

252

CLCL

CLKOUT high time

SHSL

CLCL

CLKOUT low time

SLSH

377

CLCL

CLKOUT low to ALE high

SLLH

CLCL

+ 40

C515

Semiconductor Group

1997-08-01

AC Characteristics (24 MHz) (cont'd)

External Data Memory Characteristics

External Clock Drive Characteristics

Parameter

Symbol

Limit Values

Unit

24 MHz

Clock

Variable Clock

CLCL

= 1 MHz to 24 MHz

min.

max.

min.

max.

RD pulse width

RLRH

180

CLCL

WR pulse width

WLWH

180

CLCL

Address hold after ALE

LLAX2

CLCL

RD to valid data in

RLDV

118

CLCL

Data hold after RD

RHDX

Data float after RD

RHDZ

CLCL

ALE to valid data in

LLDV

200

CLCL

133

Address to valid data in

AVDV

220

CLCL

155

ALE to WR or RD

LLWL

175

CLCL

+ 50

Address valid to WR or RD

AVWL

CLCL

WR or RD high to ALE high

WHLH

CLCL

+ 25

Data valid to WR transition

QVWX

CLCL

Data setup before WR

QVWH

170

CLCL

122

Data hold after WR

WHQX

CLCL

Address float after RD

RLAZ

Parameter

Symbol

Limit Values

Unit

Variable Clock

Freq. = 1 MHz to 24 MHz

min.

max.

Oscillator period

CLCL

41.7

1000

High time

CHCX

CLCL

CLCX

Low time

CLCX

CLCL

CHCX

Rise time

CLCH

Fall time

CHCL

C515

Semiconductor Group

1997-08-01

ROM Verification Characteristics for the C515-1RM

ROM Verification Mode 1

Figure 24
ROM Verification Mode 1

Parameter

Symbol

Limit Values

Unit

min.

max.

Address to valid data

AVQV

CLCL

MCT03212

AVQV

New Address

New Data Out

Port 0

Inputs : PSEN =

ALE, EA =

RESET =

Data :

Address : P1.0 - P1.7 = A0 - A7

IL2

P2.0 - P2.4 = A8 - A12

P0.0 - P0.7 = D0 - D7

P2.0 - P2.4

P1.0 - P1.7

Address

Data OUT

Semiconductor Group

1997-08-01

C515

ROM Verification Mode 2

Figure 25
ROM Verification Mode 2

Parameter

Symbol

Limit Values

Unit

min.

typ

max.

ALE pulse width

AWD

CLCL

ALE period

ACY

CLCL

Data valid after ALE

DVA

CLCL

Data stable after ALE

DSA

CLCL

P3.5 setup to ALE low

CLCL

Oscillator frequency

CLCL

MHz

MCT02613

ACY

AWD

DSA

DVA

Data Valid

ALE

Port 0

P3.5

C515

Semiconductor Group

1997-08-01

Figure 26
AC Testing: Input, Output Waveforms

Figure 27
AC Testing : Float Waveforms

Figure 28
Recommended Oscillator Circuits for Crystal Oscillator

0.45 V

0.2

-0.1

+0.9

0.2

Test Points

MCT00039

-0.5 V

AC Inputs during testing are driven at

- 0.5 V for a logic '1' and 0.45 V for a logic '0'.

Timing measurements are made at

IHmin

for a logic '1' and

ILmax

for a logic '0'.

MCT00038

Load

-0.1 V

+0.1 V

Load

Timing Reference

Points

-0.1 V

+0.1 V

For timing purposes a port pin is no longer floating when a 100 mV
change from load voltage occurs and begins to float when a 100 mV change from the loaded

level occurs.

MCS03204

XTAL1

XTAL2

XTAL1

Crystal Oscillator Mode

Driving from External Source

External Oscillator
Signal

N.C.

1-24 MHz

C = 20 pF±10 pF (incl. stray capacitance)

Crystal Mode :

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: Q67127-C1030

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: Q67127-C1030