Semiconductor Group

08.95

High-Performance

SAB 80C515A / 83C515A-5

8-Bit CMOS Single-Chip Microcontroller

Preliminary

SAB 83C515A-5

Microcontroller with factory mask-programmable ROM

SAB 80C515A

Microcontroller for external ROM

SAB 80C515A / 83C515A-5, up to 18 MHz operation frequency

32 K

8 ROM (SAB 83C515A-5 only, ROM-Protection available)

256

8 on-chip RAM

Additional 1 K

8 on-chip RAM (XRAM)

Superset of SAB 80C51 architecture:
1

s instruction cycle time at 12 MHz

666 ns instruction cycle time at 18 MHz
256 directly addressable bits
Boolean processor
64 Kbyte external data and program memory addressing

Three 16-bit timer/counters

Versatile "fail-safe" provisions

Twelve interrupt vectors, four priority levels selectable

Genuine 10-bit A/D converter with 8 multiplexed inputs

Full duplex serial interface with programmable Baudrate-Generator

Functionally compatible with SAB 80C515

Extended power saving mode

Fast Power-On Reset

Seven ports: 48 I/O lines, 8 input lines

Two temperature ranges available:
0 to 70

C (T1)

40 to 85

C (T3)

Plastic packages: P-LCC-68 and P-MQFP-80

The SAB 80C515A/83C515A-5 is a high-end member of the Siemens SAB 8051
microcontroller family. It is designed in Siemens ACMOS technology and based on the
SAB 8051 architecture. ACMOS is a technology which combines high-speed and density
characteristics with low-power consumption or dissipation.

While maintaining all the SAB 80C515 features and operating characteristics the
SAB 80C515A/83C515A-5 contains more on-chip RAM/ROM. Furthermore a new 10-bit A/D-
Converter is implemented as well as extended security mechanisms. The SAB 80C515A is
identical with the SAB 83C515A-5 except that it lacks the on-chip program memory. The
SAB 80C515A / 83C515A-5 is supplied in a 68-pin plastic leaded chip carrier package
(P-LCC- 68) and in a 80-pin plastic metric quad flat package (P-MQFP-80).

Versions for extended temperature range 40 to + 110

C are available on request.

SAB 80C515A/83C515A-5

Semiconductor Group

Ordering Information

Notes

Versions for extended temperature range

40 to + 110

C on request.

The ordering number of ROM types (DXXXX extension) is defined after program release
(verification) of the customer.

Type

Ordering
Code

Package

Description
8-Bit CMOS microcontroller

SAB 80C515A-N18

Q67120-C0581

P-LCC-68

for external memory, 18 MHz

SAB 83C515A-5N18

Q67120-DXXXX P-LCC-68

with mask-programmable ROM,
18 MHz

SAB 80C515A-N18-T3

Q67120-C0784

P-LCC-68

for external memory, 18 MHz
ext. temperature

40 to + 85

SAB 83C515A-5N18-T3 Q67120-DXXXX P-LCC-68

with mask-programmable ROM,
18 MHz
ext. temperature

40 to + 85

SAB 80C515A-M18-T3

Q67120-C0851

P-MQFP-80 for external memory, 18 MHz

ext. temperature

40 to + 85

SAB 83C515A-5M18-T3 Q67120-DXXXX P-MQFP-80 with mask-programmable ROM,

18 MHz
ext. temperature

40 to + 85

SAB 80C515A/83C515A-5

Semiconductor Group

Pin Configuration

(P-MQFP-80

)

N.C. pins must not be connected.

P0.6 / AD6

SAB 80C515A / 80C515A-5

P0.7 / AD7

P0.5 / AD5
P0.4 / AD4

P0.2 / AD2

P0.3 / AD3

P0.1 / AD1
P0.0 / AD0

P5.7

N.C.

EA
ALE
PSEN

P2.7 / A15

N.C.

P2.6 / A14
P2.5 / A13
P2.4 / A12
P2.3 / A11

VAREF

N.C.

VAGND

P6.7 / AIN7

P6.5 / AIN5

P6.6 / AIN6

P6.4 / AIN4
P6.3 / AIN3

RESET

P6.2 / AIN2

P6.0 / AIN0

N.C.
N.C.

P3.1 / TXD0

P6.1 / AIN1

P3.0 / RXD0

P3.2 / INT0
P3.3 / INT1

P3.4 / T0
P3.5 / T1

N.C.

P3.7 /

P1.7 / T2

P1.6 / CLKOUT

P1.4 /

INT2

P1.5 / T2EX

P1.3 / INT6 / CC3

P1.2 / INT5 / CC2

P3.6 /

P1.1 / INT4 / CC1

VCC

VSS

XTAL2

P1.0 /

INT3

/ CC0

VSS

XTAL1

P2.0 / A8

P2.1 / A9

P2.2 / A10

P4.5

P4.6

P4.4

P4.3

P4.2

/ SWD

P4.1

P4.0 /

ADST

P4.7

N.C.

HWPD

N.C.

P5.0

P5.2

N.C.

P5.1

P5.3

P5.4

P5.5

P5.6

SAB 80C515A/83C515A-5

Semiconductor Group

Pin Definitions and Functions

Symbol

Pin
P-LCC-68

Pin
P-MQFP-80

Input (I)
Output (O)

Function

P4.0-P4.7 1-3, 5-9

72-74,
76-80

I/O

Port 4

is an 8-bit bidirectional I/O port with internal
pull-up resistors. Port 4 pins that have 1's writ-
ten to them are pulled high by the internal pull-
up resistors, and in that state can be used as
inputs. As inputs, port 4 pins being externally

pulled low will source current (

, in the DC

characteristics) because of the internal pull-up
resistors.
P4 also contains the external A/D converter
control pin. The output latch corresponding to
a secondary function must be programmed to
a one (1) for that function to operate. The sec-
ondary function assigned to port 6:
ADST(P4.0): external A/D converter start

PE/SWD

Power saving mode enable/Start Watch-
dog Timer

A low level on this pin allows the software to
enter the power down, idle and slow down
mode. In case the low level is also seen during
reset, the watchdog timer function is off on de-
fault.
Use of the software controlled power saving
modes is blocked, when this pin is held on
high level. A high level during reset performs
an automatic start of the watchdog timer im-
mediately after reset.
When left unconnected this pin is pulled high
by a weak internal pull-up resistor.

RESET

Reset pin

A low level on this pin for the duration of two
machine cycles while the oscillator is running
resets the SAB 80C515A. A small internal
pullup resistor permits power-on reset using
only a capacitor connected to

AREF1

Reference voltage

for the A/D converter

AGND

Reference ground

for the A/D converter

SAB 80C515A/83C515A-5

Semiconductor Group

P6.7-P6.0 13-20

5-12

Port 6

is an 8-bit unidirectional input port to the A/
D converter. Port pins can be used for digital
input, if voltage levels simultaneously meet
the specifications high/low input voltages, and
for the eight multiplexed analog inputs.

P3.0-P3.7 21-28

15-22

I/O

Port 3

is an 8-bit bidirectional I/O port with internal
pullup resistors. Port 3 pins that have1's
written to them are pulled high by the internal
pullup resistors, and in that state can be used
as inputs. As inputs, port 3 pins being
externally pulled low will source current (

, in

the DC characteristics) because of the internal
pullup resistors. Port 3 also contains the
interrupt, timer, serial port and external
memory strobe pins that are used by various
options. The output latch corresponding to a
secondary function must be programmed to a
one (1) for that function to operate. The
secondary functions are assigned to the pins
of port 3, as follows:

D (P3.0): serial port's receiver data

input (asynchronous) or data
input/output (synchronous)

D (P3.1): serial port's transmitter data

output (asynchronous) or
clock output (synchronous)

INT0(P3.2):

interrupt 0

input/timer 0 gate

control input

INT1(P3.3):

interrupt 1 input/timer 1 gate
control input

T0 (P3.4):

counter 0 input

T1 (P3.5):

counter 1 input

WR(P3.6):

the write control signal
latches the data byte from
port 0 into the external data
memory

RD(P3.7):

the read control signal
enables the external data
memory to port 0

Pin Definitions and Functions

(cont'd)

Symbol

Pin
P-LCC-68

Pin
P-MQFP-80

Input (I)
Output (O)

Function

SAB 80C515A/83C515A-5

Semiconductor Group

P1.7 -
P1.0

29-36

24-31

I/O

Port 1

is an 8-bit bidirectional I/O port with internal
pullup resistors. Port 1 pins that have 1's
written to them are pulled high by the internal
pullup resistors, and in that state can be used
as inputs. As inputs, port 1 pins being
externally pulled low will source current (

the DC characteristics) because of the internal
pullup resistors. The port is used for the low-
order address byte during program
verification. Port 1 also contains the interrupt,
timer, clock, capture and compare pins that
are used by various options. The output latch
corresponding to a secondary function must
be programmed to a one (1) for that function to
operate (except when used for the compare
functions). The secondary functions are
assigned to the port 1 pins as follows:

INT3/CC0 (P1.0): interrupt 3 input /

compare 0 output /
capture 0 input

INT4/CC1 (P1.1): interrupt 4 input /

compare 1 output /
capture 1 input

INT5/CC2 (P1.2): interrupt 5 input /

compare 2 output /
capture 2 input

INT6/CC3 (P1.3): interrupt 6 input /

compare 3 output /
capture 3 input

INT2(P1.4):

interrupt 2 input

T2EX (P1.5):

timer 2 external
reloadtrigger input

CLKOUT (P1.6):

system clock output

T2 (P1.7):

counter 2 input

XTAL2

XTAL2

Input to the inverting oscillator amplifier and
input to the internal clock generator circuits.

Pin Definitions and Functions

(cont'd)

Symbol

Pin
P-LCC-68

Pin
P-MQFP-80

Input (I)
Output (O)

Function

SAB 80C515A/83C515A-5

Semiconductor Group

XTAL1

XTAL1

Output of the inverting oscillator amplifier.
To drive the device from an external clock
source, XTAL2 should be driven, while XTAL1
is left unconnected. There are no require-
ments on the duty cycle of the external clock
signal, since the input to the internal clok-
king circuitry is divided down by a divide-by-
two flip-flop. Minimum and maximum high and
low times and rise/fall times specified in the
AC characteristics must be taken into account.

P2.0-P2.7 41-48

38-45

I/O

Port 2

is an 8-bit bidirectional I/O port with internal
pullup resistors. Port 2 pins that have 1's
written to them are pulled high by the internal
pullup resistors, and in that state can be used
as inputs. As inputs, port 2 pins being
externally pulled low will source current (

IL,

the DC characteristics) because of the internal
pullup resistors.
Port 2 emits the high-order address byte
during fetches from external program memory
and during accesses to external data memory
that use 16-bit addresses (MOVX@DPTR). In
this application it uses strong internal pullup
resistors when issuing 1's. During accesses to
external data memory that use 8-bit
addresses (MOVX@Ri), port 2 issues the
contents of the P2 special function register.

PSEN

The

Program Store Enable

output is a control signal that enables the
external program memory to the bus during
external fetch operations. It is activated every
six oscillator periods, except during external
data memory accesses. The signal remains
high during internal program execution.

ALE

The

Address Latch enable

output is used for latching the address into
external memory during normal operation. It is
activated every six oscillator periods, except
during an external data memory access.

Pin Definitions and Functions (cont'd)

Symbol

Pin
P-LCC-68

Pin
P-MQFP-80

Input (I)
Output (O)

Function

SAB 80C515A/83C515A-5

Semiconductor Group

External Access Enable
When held high, the SAB 80C515A executes
instructions from the internal ROM as long as
the PC is less than 32768. When held low, the
SAB 80C515A fetches all instructions from
external program memory. For the SAB
80C515A this pin must be tied low.

P0.0-P0.7 52-59

52-59

I/O

Port 0
is an 8-bit open-drain bidirectional I/O port.
Port 0 pins that have 1's written to them float,
and in that state can be used as high-
impedance inputs.
Port 0 is also the multiplexed low-order
address and data bus during accesses to
external program and data memory. In this
application it uses strong internal pullup
resistors when issuing 1's.
Port 0 also outputs the code bytes during
program verification in the SAB 80C515A.
External pullup resistors are required during
program verification.

P5.7-P5.0 60-67

60-67

I/O

Port 5 is an 8-bit bidirectional I/O port with
internal pullup resistors. Port 5 pins that have
1's written to them are pulled high by the
internal pullup resistors, and in that state can
be used as inputs. As inputs, port 5 pins being
externally pulled low will source current
(

in the DC characteristics) because of the

internal pullup resistors.

HWPD

Hardware Power Down
A low level on this pin for the duration of one
machine cycle while the oscillator is running
resets the SAB 80C515A.
A low level for a longer period will force the
part to Power Down Mode with the pins float-
ing. (see table 5)

32, 33

Supply voltage
during normal, idle, and power-down operation.

34, 35

Ground (0 V)

N.C.

2, 13, 14, 23,
46, 50, 51,
68, 70, 71

Not connected
These pins of the P-MQFP-80 package must
not be connected.

Pin Definitions and Functions (cont'd)

Symbol

Pin
P-LCC-68

Pin
P-MQFP-80

Input (I)
Output (O)

Function

SAB 80C515A/83C515A-5

Semiconductor Group

Functional Description

The SAB 80C515A is based on 8051 architecture. It is a fully compatible member of the
Siemens SAB 8051/80C51 microcontroller family being an significantly enhanced
SAB 80C515. The SAB 80C515A is therefore code compatible with the SAB 80C515.

Having an 8-bit CPU with extensive facilities for bit-handling and binary BCD arithmetics the
SAB 80C515A is optimized for control applications. With a 18 MHz crystal, 58 % of the
instructions are executed in 666.67 ns.

While maintaining all architectural and operational characteristics of the SAB 80C515 the SAB
80C515A incorporates more on-chip RAM. A new 10-bit A/D-Converter is implemented as well
as an oscillator watchdog unit. Also the maximum operating frequency of 18 MHz is higher than
at the SAB 80C515.

With exception of the ROM sizes both parts are identical. Therefore the therm SAB 80C515A
refers to both versions within this specification unless otherwise noted.

Memory Organisation

According to the SAB 8051 architecture, the SAB 80C515A has separate address spaces for
program and data memory. Figure 2 illustrates the mapping of address spaces.

Figure 2
Memory Map

SAB 80C515A/83C515A-5

Semiconductor Group

Program Memory ('Code Space')

The SAB 83C515A-5 has 32 Kbyte of on-chip ROM, while the SAB 80C515A has no internal
ROM. The program memory can externally be expanded up to 64 Kbyte. Pin EA determines
whether program fetches below address 8000

are done from internal or external memory.

As a new feature the SAB 83C515A-5 offers the possibility of protecting the internal ROM
against unauthorized access. This protection is implemented in the ROM-Mask. Therefore, the
decision ROM-Protection 'yes' or 'no' has to be made when delivering the ROM-Code. Once
enabled, there is no way of disabling the ROM-Protection.

Effect:

The access to internal ROM done by an externally fetched MOVC instruction is
disabled. Nevertheless, an access from internal ROM to external ROM is possible.

To verify the read protected ROM-Code a special ROM-Verify-Mode is implemented. This
mode also can be used to verify unprotected internal ROM.

ROM -Protection

ROM-Verification Mode
(see 'AC Characteristics')

Restrictions

ROM-Verification Mode 1
(standard 8051 Verification Mode)
ROM-Verification Mode 2

yes

ROM-Verification Mode 2

standard 8051

Verification Mode is
disabled

externally applied MOVC

accessing internal ROM
is disabled

SAB 80C515A/83C515A-5

Semiconductor Group

Data Memory ('Data Space')

The data memory space consists of an internal and an external memory space.The
SAB 80C515A contains another 1 Kbyte on On-Chip RAM additional to the 256-bytes internal
RAM of the base type SAB 80C515. This RAM is called XRAM ('extended RAM') in this
document.

External Data Memory

Up to 64 Kbyte external data memory can be addressed by instructions that use 8-bit or 16-bit
indirect addressing. For 8-bit addressing MOVX instructions in combination with registers R0
and R1 can be used. A 16-bit external memory addressing is supported by a 16-bit datapointer.
Registers XPAGE and SYSCON are controlling whether data fetches at addresses F800

FBFF

are done from internal XRAM or from external data memory.

Internal Data Memory

The internal data memory is divided into four physically distinct blocks:

the lower 128 bytes of RAM including four register banks containing eight

registers each

the upper 128 byte of RAM

the 128 byte special function register area.

a 1 K

8 area which is accessed like external RAM (MOVX-instructions), implemented on

chip at the address range from F800

to FBFF

. Special Function Register SYSCON

controls whether data is read from or written to XRAM or external RAM.

A map of the internal data memory is shown in figure 2. The overlapping address spaces of the
standard internal data memory (256 byte) are accessed by different addressing modes (see
User's Manual SAB 80C515). The stack can be located anywhere in the internal data memory.

Architecture of the XRAM

The contents of the XRAM is not affected by a reset or HW Power Down. After power-up the
contents is undefined, while it remains unchanged during and after a reset or HW Power Down
if the power supply is not turned off.

The additional On-Chip RAM is logically located in the "external data memory" range at the
upper end of the 64 Kbyte address range (F800

-FBFF

). Nevertheless when XRAM is

enabled the address range F800

to FFFF

is occupied. This is done to assure software

compatibility to SAB 80C517A. It is possible to enable and disable (only by reset) the XRAM. If
it is disabled the device shows the same behaviour as the parts without XRAM, i.e. all MOVX
accesses use the external bus to physically external data memory.

SAB 80C515A/83C515A-5

Semiconductor Group

Accesses to XRAM

Because the XRAM is used in the same way as external data memory the same instruction
types must be used for accessing the XRAM.

Note:

If a reset occurs during a write operation to XRAM, the effect on XRAM depends on the
cycle which the reset is detected at (MOVX is a 2-cycle instruction):

Reset detection at cycle 1:

The new value will not be written to XRAM. The old value
is not affected.

Reset detection at cycle 2:

The old value in XRAM is overwritten by the new value.

Accesses to XRAM using the DPTR

There are a Read and a Write instruction from and to XRAM which use one of the 16-bit DPTR
for indirect addressing. The instructions are:

MOVX A,

@DPTR (Read)

MOVX

@DPTR, A (Write)

Normally the use of these instructions would use a physically external memory. However, in the
SAB 80C515A the XRAM is accessed if it is enabled and if the DPTR points to the XRAM
address space (DPTR

F800

Accesses to XRAM using the Registers R0/R1

The 8051 architecture provides also instructions for accesses to external data memory range
which use only an 8-bit address (indirect addressing with registers R0 or R1). The instructions
are:

MOVX A,

@Ri (Read)

MOVX

@Ri, A (Write)

In application systems, either a real 8-bit bus (with 8-bit address) is used or Port 2 serves as
page register which selects pages of 256-byte. However, the distinction, whether Port 2 is
used as general purpose I/O or as "page address" is made by the external system design. From
the device's point of view it cannot be decided whether the Port 2 data is used externally as
address or as I/O data!

Hence, a special page register is implemented into the SAB 80C515A to provide the possibility
of accessing the XRAM also with the MOVX @Ri instructions, i.e. XPAGE serves the same
function for the XRAM as Port 2 for external data memory.

SAB 80C515A/83C515A-5

Semiconductor Group

Special Function Register XPAGE

The reset value of XPAGE is 00

XPAGE can be set and read by software.

The register XPAGE provides the upper address byte for accesses to XRAM with MOVX @Ri
instructions. If the address formed from XPAGE and Ri is less than the XRAM address range,
then an external access is performed. For the SAB 80C515A the contents of XPAGE must be
greater or equal than F8

in order to use the XRAM. Of course, the XRAM must be enabled if

it shall be used with MOVX @Ri instructions.

Thus, the register XPAGE is used for addressing of the XRAM; additionally its contents are
used for generating the internal XRAM select. If the contents of XPAGE is less than the XRAM
address range then an external bus access is performed where the upper address byte is
provided by P2 and not by XPAGE!

Therefore, the software has to distinguish two cases, if the MOVX @Ri instructions with paging
shall be used:

a) Access to XRAM:

The upper address byte must be written to XPAGE or P2;
both writes selects the XRAM address range.

b) Access to external memory: The upper address byte must be written to P2; XPAGE will

be loaded with the same address in order to deselect the
XRAM.

Addr. 91

XPAGE

SAB 80C515A/83C515A-5

Semiconductor Group

Control of XRAM in the SAB 80C515A

There are two control bits in register SYSCON which control the use and the bus operation
during accesses to the additional On-Chip RAM (XRAM).

Special Function Register SYSCON

Reset value of SYSCON is XXXX XX01B.

The control bit XMAP0 is a global enable/disable bit for the additional On-Chip RAM (XRAM).
If this bit is set, the XRAM is disabled, all MOVX accesses use external memory via the external
bus. In this case the SAB 80C515A does not use the additional On-Chip RAM and is compatible
with the types without XRAM.

Addr. 0B1

XMAP1 XMAP0 SYSCON

Bit

Function

XMAP0

Global enable/disable bit for XRAM memory.
XMAP0 =0: The access to XRAM (= On-Chip XDATA memory) is en-

abled.

XMAP0 = 1: The access to XRAM is disabled. All MOVX accesses are

performed by the external bus (reset state).

XMAP1

Control bit for / RD/WRsignals during accesses to XRAM; this bit has no
effect if XRAM is disabled (XMAP0 = 1) or if addresses exceeding the
XRAM address range are used for MOVX accesses.
XMAP1 = 0: The signals RD and WR are not activated during accesses

to XRAM.

XMAP1 = 1: The signals RD and WR are activated during accesses to

XRAM.

SAB 80C515A/83C515A-5

Semiconductor Group

XMAP0 is hardware protected by an unsymmetric latch. An unintentional disabling of XRAM
could be dangerous since indeterminate values would be read from external bus. To avoid this
the XMAP-bit is forced to '1' only by reset. Additionally, during reset an internal capacitor is
loaded. So after reset state XRAM is disabled. Because of the load time of the capacitor
XMAP0-bit once written to '0' (that is, discharging capacitor) cannot be set to '1' again by
software. On the other hand any distortion (software hang up, noise, ...) is not able to load this
capacitor, too. That is, the stable status is XRAM enabled. The only way to disable XRAM after
it was enabled is a reset.

The clear instruction for XMAP0 should be integrated in the program initialization routine before
XRAM is used. In extremely noisy systems the user may have redundant clear instructions.

The control bit XMAP1 is relevant only if the XRAM is accessed. In this case the external RD
and WR signals at P3.6 and P3.7 are not activated during the access, if XMAP1 is cleared. For
debug purposes it might be useful to have these signals and the addresses at Ports 0.2
available. This is performed if XMAP1 is set.

The behaviour of Port 0 and P2 during a MOVX access depends on the control bits in register
SYSCON and on the state of pin EA. The table 1 lists the various operating conditions. It shows
the following characteristics:

a) Use of P0 and P2 pins during the MOVX access.

Bus: The pins work as external address/data bus. If (internal) XRAM

is accessed, the data written to the XRAM can be seen on the bus in
debug mode.

I/0:

The pins work as Input/Output lines under control of their latch.

b) Activation of the RD and WR pin during the access.

c) Use of internal or external XDATA memory.

The shaded areas describe the standard operation as each 80C51 device without on-chip
XRAM behaves.

SAB 80C515A/83C515A-5

Semiconductor Group

Table 1:
Behaviour of P0/P2 and

during MOVX accesses

DPTR < XRAM

address
range

MOVX

@Ri

MOVX

@DPTR

a) P0/P2

Bus

WR active

c) ext. memory is
used

a) P0/P2

Bus

WR active

c) ext. memory is
used

a) P0/P2

Bus

b) RD

active

c) ext. memory is

used

a) P0/P2

Bus

b) RD

WR active

c) ext. memory is
used

a) P0/P2

Bus

WR active

c) ext. memory is
used

a) P0/P2

Bus

WR active

c) ext. memory is
used

a) P0/P2

Bus

WR active

c) ext. memory is
used

a) P0/P2

Bus

WR active

c) ext. memory is
used

modes compatible to 8051 - family

XMAP1, XMAP0

= 0

a) P0/P2

BUS

(

-Data only)

WR inactive

c) XRAM is used

a) P0/P2

BUS

(

-Data only)

WR active

c) XRAM is used

a) P0/P2

I/0

WR inactive

c) XRAM is used

a) P0/P2

BUS

(

-Data only)

WR active

c) XRAM is used

a) P0/P2

BUS

(

-Data only)

I/0

WR inactive

c) XRAM is used

a) P0/P2

BUS

(

-Data only)

I/0

WR active

c) XRAM is used

a) P0

Bus

I/0

WR active

c) ext. memory is
used

a) P0/P2

I/0

WR inactive

c) XRAM is used

a) P0

BUS

(

-Data only)

I/0

WR active

c) XRAM is used

a) P0

Bus

I/0

WR active

c) ext. memory is
used

a) P0

Bus

I/0

WR active

c) ext. memory is
used

a) P0

Bus

I/0

WR active

c) ext. memory is
used

a) P0

Bus

I/0

WR active

c) ext. memory is
used

a) P0

Bus

I/0

WR active

c) ext. memory is
used

a) P0

Bus

I/0

WR active

c) ext. memory is
used

DPTR

XRAM

address
range

XPAGE < XRAM

addr.

page

range

XPAGE

XRAM

addr.

page

range

XMAP1, XMAP0

= 1

a) P0

Bus

I/0

WR active

c) ext. memory is
used

SAB 80C515A/83C515A-5

Semiconductor Group

Special Function Registers

All registers, except the program counter and the four general purpose register banks, reside
in the special function register area. The special function registers include arithmetic registers,
pointers, and registers that provide an interface between the CPU and the on-chip peripherals.
There are also 128 directly addressable bits within the SFR area. All special function registers
are listed in table 2 and table 3.

In table 2 they are organized in numeric order of their addresses. In table 3 they are organized
in groups which refer to the functional blocks of the SAB 80C515A.

Table 2
Special Function Register

Address

Register

Contents
after Reset

Address

Register

Contents
after Reset

SP
DPL
DPH
(WDTL)
(WDTH)
WDTREL
PCON

0FF

S0CON

SBUF
reserved
reserved
reserved
reserved
reserved
reserved

TCON

TMOD
TL0
TL1
TH0
TH1
reserved
reserved

reserved
reserved
reserved
reserved
reserved
reserved
reserved

0FF

XPAGE
reserved
reserved
reserved
reserved
reserved
reserved

0FF

IEN0

IP0
SRELL
reserved
reserved
reserved
reserved
reserved

0D9

Bit-addressable special function registers

X means that the value is indeterminate and the location is reserved

SAB 80C515A/83C515A-5

Semiconductor Group

Table 2: Special Function Register (cont'd)

Address

Register

Contents
after Reset

Address

Register

Contents
after Reset

SYSCON
reserved
reserved
reserved
reserved
reserved
reserved

0FF

XXXX XX01

PSW

reserved
reserved
reserved
reserved
reserved
reserved
reserved

EN1

IP1
SRELH
reserved
reserved
reserved
reserved
reserved

XX00 0000

XXXX XX11

ADCON0

ADDATH
ADDATL
P6
ADCVON1
reserved
reserved
reserved

XXXX 0000

IRCON

CCEN
CCL1
CCH1
CCL2
CCH2
CCL3
CCH3

ACC

reserved
reserved
reserved
reserved
reserved
reserved
reserved

T2CON

reserved
CRCL
CRCH
TL2
TH2
reserved
reserved

reserved
reserved
reserved
reserved
reserved
reserved
reserved

0FF

Bit-addressable special function registers

X means that the value is indeterminate and the location is reserved

SAB 80C515A/83C515A-5

Semiconductor Group

reserved
reserved
reserved
reserved
reserved
reserved
reserved

reserved
reserved

00F

Bit-addressable special function registers

X means that the value is indeterminate and the location is reserved

Table 2: Special Function Register (cont'd)

Address

Register

Contents
after Reset

Address

Register

Contents
after Reset

SAB 80C515A/83C515A-5

Semiconductor Group

Table 3
Special Function Registers - Functional Blocks

Block

Symbol

Name

Address

Contents
after Reset

CPU

ACC
B
DPH
DPL
PSW
SP

Accumulator
B-Register
Data Pointer, High Byte
Data Pointer, Low Byte
Program Status Word Register
Stack Pointer

0E0

0F0

0D0

A/D-
Converter

ADCON0
ADCON1
ADDATH
ADDATL

A/D Converter Control Register 0
A/D Converter Control Register 1
A/D Converter Data Reg. High Byte
A/D Converter Data Reg. Low Byte

0D8

0DC

0D9

0DA

0XXX 0000

Interrupt
System

EN0
IEN1
IP0
IP1
IRCON0
TCON

T2CON

Interrupt Enable Register 0
Interrupt Enable Register 1
Interrupt Priority Register 0
Interrupt Priority Register 1
Interrupt Request Control Register
Timer Control Register
Timer 2 Control Register

0A8

0B8

0A9

0B9

0C0

0C8

XX00 0000

Compare/
Capture-
Unit
(CCU)

CCEN
CCH1
CCH2
CCH3
CCL1
CCL2
CCL3
CRCH
CRCL
TH2
TL2
T2CON

Comp./Capture Enable Reg.
Comp./Capture Reg. 1, High Byte
Comp./Capture Reg. 2, High Byte
Comp./Capture Reg. 3, High Byte
Comp./Capture Reg. 1, Low Byte
Comp./Capture Reg. 2, Low Byte
Comp./Capture Reg. 3, Low Byte
Com./Rel./Capt. Reg. High Byte
Com./Rel./Capt. Reg. Low Byte
Timer 2, High Byte
Timer 2, Low Byte
Timer 2 Control Register

0C1

0C3

0C5

0C7

0C2

0C4

0C6

0CB

0CA

0CD

0CC

0C8

XRAM

XPAGE

SYSCON

Page Address Register for Exten-
ded On Chip RAM
XRAM Control Register

0B1

XXXX XX01

Bit-addressable special function registers

This special function register is listed repeatedly since some bits of it also belong to other

functional blocks.

X means that the value is indeterminate and the location is reserved

SAB 80C515A/83C515A-5

Semiconductor Group

Table 3
Special Function Registers - Functional Blocks (cont'd)

Block

Symbol

Name

Address

Contents
after Reset

Ports

P0
P1
P2
P3
P4
P5
P6

Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6, Analog/Digital Input

0A0

0B0

0E8

0F8

0DB

0FF

Pow.Sav.M
ode

PCON

Power Control Register

Serial
Channels

ADCON0

PCON

SBUF
SCON
SRELL

SRELH

A/D Converter Control Reg.
Power Control Register
Serial Channel Buffer Reg.
Serial Channel Control Reg.
Serial Channel Reload Reg.,
low byte
Serial Channel Reload Reg.,
high byte

0D8

0XX

XXXX XX11

Timer 0/
Timer 1

TCON
TH0
TH1
TL0
TL1
TMOD

Timer Control Register
Timer 0, High Byte
Timer 1, High Byte
Timer 0, Low Byte
Timer 1, Low Byte
Timer Mode Register

Watchdog

IEN0

IEN1

IP0

IP1

WDTREL

Interrupt Enable Register 0
Interrupt Enable Register 1
Interrupt Priority Register 0
Interrupt Priority Register 1
Watchdog Timer Reload Reg.

0A8

0B8

0A9

0B9

XX00 0000

Bit-addressable special function registers

This special function register is listed repeatedly since some bits of it also belong to other
functional blocks.

X means that the value is indeterminate and the location is reserved

SAB 80C515A/83C515A-5

Semiconductor Group

A/D Converter

In the SAB 80C515A a new high performance / high-speed 8-channel 10-bit A/D-Converter
(ADC) is implemented. Its successive approximation technique provides 7

s conversion time

(

OSC

= 16 MHz). The conversion principle is upward compatible to the one used in the

SAB 80C515. The main functional blocks are shown in figure 3.

The comparator is a fully differential comparator for a high power supply rejection ratio and very
low offset voltages. The capacitor network is binary weighted providing genuine10-bit
resolution.

The table below shows the sample time

and the conversion time

, which are dependend

OSC

and a new prescaler.

The ADC is clocked (

ADC

) with

OSC

/8. Because of the ADC's maximum clock frequency of

2 MHz the prescaler (divide-by-2) has to be enabled (set Bit ADCL in SFR ADCON 1) when the
oscillator frequency (

OSC

) is higher than 16 MHz.

OSC

[MHz]

Prescaler

ADC

[MHz]

Sample Time

[

Conversion Time
(incl. sample time)

[

1.5

2.67

9.3

0.75

5.33

18.66

2.0

7.0

1.0

14.0

1.125

3.55

12.4

SAB 80C515A/83C515A-5

Semiconductor Group

Timers /Counters

The SAB 80C515A contains three 16-bit timers/counters wich are useful in many applications
for timing and counting. the input clock for wach timer/counter is 1/12 of the oscillator frequency
in the timer operation or can be taken from an external clock source for the counter operation
(maximum count rate is 1/24 of the oscillator frequency).

 Timer/Counter 0 and 1

These timers/counters can operate in four modes:

Mode 0:

8-bit timer/counter with 32:1 prescaler

Mode 1:

16-bit timer/counter

Mode 2:

8-bit timer/counter with 8-bit auto-reload

Mode 3:

Timer/counter 0 is configured as one 8-bit timer/counter and one
8-bit timer; Timer/counter 1 in this mode holds its count.

External inputs INTO and INT1 can be programmed to function as a gate for timer/counters 0
and 1 to facilitate pulse width measurements.

 Timer/Counter 2

Timer/counter 2 of the SAB 80C515A is a 16-bit timer/counter with several additional features.
It offers a 2:1 prescaler, a selectable gate function, and compare, capture and reload functions.
Corresponding to the 16-bit timer register there are four 16-bit capture/compare registers, one
of them can be used to perform a 16-bit reload on a timer overflow or external event. Each of
these registers corresponds to a pin of port 1 for capture input/compare output.

Figure 4 shows a block diagram of timer/counter 2.

Reload

A 16-bit reload can be performed with the 16-bit CRC register consisting of CRCL and CRCH.
There are two modes from which to select:

Mode 0:

Reload is caused by a timer 2 overflow (auto-reload).

Mode 1:

Reload is caused in response to a negative transition at pin T2EX
(P1.5), which can also request an interrupt.

SAB 80C515A/83C515A-5

Semiconductor Group

Capture

This feature permits saving of the actual timer/counter contents into a selected register upon
an external event or a software write operation. Two modes are provided to latch the current
16-bit value of timer 2 registers TL2 and TH2 into a dedicated capture register.

Mode 0:

Capture is performed in response to a transition at the corresponding
port 1 pins CC0 to CC3.

Mode 1:

Write operation into the low-order byte of the dedicated capture
register causes the timer 2 contents to be latched into this register.

Compare

In compare mode, the 16-bit values stored in the dedicated compare registers are compared
to the contents of the timer 2 registers. If the count value in the timer 2 registers matches one
of the stored values, an appropriate output signal is generated and an interrupt is requested.
Two compare modes are provided:

Mode 0: Upon a match the output signal changes from low to high. It goes

back to low level when timer 2 overflows.

Mode 1: The transition of the output signal can be determined by software.

A timer 2 overflow causes no output change.

SAB 80C515A/83C515A-5

Semiconductor Group

Interrupt Structure

The SAB 80C515A has 12 interrupt vectors with the following vector addresses and request
flags.

Each interrupt vector can be individually enabled/disabled. The minimum response time to an
interrupt request is more than 3 machine cycles and less than 9 machine cycles, if no other
interrrupt of the same or a higher priority level is in process.

Figure 5 shows the interrupt request sources.

External interrupts 0 and 1 can be activated by a low-level or a negative transition (selectable)
at their corresponding input pin, external interrupts 2 and 3 can be programmed for triggering
on a negative or a positive transition. The external interrupts 3 or 6 are combined with the
corresponding alternate functions compare (output) and capture (input) on port 1.

For programming of the priority levels the interrupt vectors are combined to pairs. Each pair can
be programmed individually to one of four priority levels by setting or clearing one bit in special
function register IP0 and one in IP1.

Figure 6 shows the priority level structure.

Table 4
Interrupt Sources and Vectors

Source (Request Flags)

Vector Address

Vector

IE0
TF0
IE1
TF1
RI + TI
TF2 + EXF2
IADC
IEX2
IEX3
IEX4
IEX5
IEX6

0003

000B

0013

001B

0023

002B

0043

004B

0053

005B

0063

006B

External interrupt 0
Timer 0 interrupt
External interrupt 1
Timer 1 interrupt
Serial port interrupt
Timer 2 interrupt
A/D converter interrupt
External interrupt 2
External interrupt 3
External interrupt 4
External interrupt 5
External interrupt 6

SAB 80C515A/83C515A-5

Semiconductor Group

I/O Ports

The SAB 80C515A has six 8-bit I/O ports and one input port. Port 0 is an open-drain
bidirectional I/O port, while ports 1 to 5 are quasi-bidirectional I/O ports with internal pull-up
resistors. That means, when configured as inputs, ports 1 to 5 will be pulled high and will source
current when externally pulled low. Port 0 will float when configured as input.

Port 0 and port 2 can be used to expand the program and data memory externally. During an
access to external memory, port 0 emits the low-order address byte and reads/writes the data
byte, while port 2 emits the high-order address byte. In this function, port 0 is not an open-drain
port, but uses a strong internal pull-up FET. Ports 1, 3 and 4 are provided for several alternate
functions, as listed below:

The SAB 80C515A has one dual-purpose input port. The ANx lines of port 6 in the SAB 80C515
can individually be used as analog or digital inputs. Reading the special function register P6
allows the user to input the digital values currently applied to the port pins. It is not necessary
to select these modes by software; the voltages applied at port 6 pins can be converted to
digital values using the A/D converter and at the same time the pins can be read via SFR P6.
It must be noted, however, that the results in port P6 bits will be indeterminate if the levels at
the corresponding pins are not within their

specifications. Furthermore, it is not possible

to use port P6 as an output port. Special function register P6 is located at address 0DB

In Hardware Power Down Mode the port pins and several control lines enter a floating state.
For more details see the section about Hardware Power Down Mode.

Port

Symbol

Function

P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P3.0

P3.1

P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P4.0

INT3/CC0
INT4/CC1
INT5/CC2
INT6/CC3
INT2
T2EX
CLKOUT
T2
RxD

TxD

INT0
INT1
T0
T1
WR
RD
ADST

External interrupt 3 input, compare 0 output, capture 0 input
External interrupt 4 input, compare 1 output, capture 1 input
External interrupt 5 input, compare 2 output, capture 2 input
External interrupt 6 input, compare 3 output, capture 3 input
External interrupt 2 input
Timer 2 external reload trigger input
System clock output
Timer 2 external count or gate input
Serial port's receiver data input (asynchronous) or
data input /output (synchronous)
Serial port's transmitter data output (asynchronous) or
clock output (synchronous)
External interrupt 0 input, timer 0 gate control
External interrupt 1 input, timer 1 gate control
Timer 0 external counter input
Timer 1 external counter input
External data memory write strobe
External data memory read strobe
A/D Converter, external start of conversion

SAB 80C515A/83C515A-5

Semiconductor Group

Power Saving Modes

The SAB 80C515A provides due to Siemens ACMOS technology four modes in which
power consumption can be significantly reduced.

The Slow Down Mode

The controller keeps up the full operating functionality, but is driven with one eight of its
normal operating frequency. Slowing down the frequency remarkable reduces power
consumption.

The Idle Mode

The CPU is gated off from the oscillator, but all peripherals are still supplied with the clock
and continue working.

The Software Power Down Mode

Operation of the SAB 80C515A is stopped, the on-chip oscillator and the RC-oscillator are
turned off. This mode is used to save the contents of the internal RAM with a very low
standby current and is fully compatible to the Power Down Mode of the SAB 80C515.

The Hardware Power Down Mode

Operation of the SAB 80C515A is stopped, the on-chip oscillator and the RC-oscillator are
turned off. The pin HWPD controls this mode. Port pins and several control lines enter a
floating state. The Hardware Power Down Mode is new in the SAB 80C515A and is
independent of the state of pin PE/SWD (which enables only the software initiated power
reduction modes).

Hardware Enable for Software controlled Power Saving Modes

A dedicated pin PE/SWD of the SAB 80C515A allows to block the Software controlled power
saving modes. Since this pin is mostly used in noise-critical application it is combined with an
automatic start of the Watchdog Timer.

PE/SWD =

(logic high level):

Using of the power saving modes is not possible. The
watchdog timer starts immediately after reset. The
instruction sequences used for entering of power saving
modes will not affect the normal operation of the device.

PE/SWD =

(logic low level):

All power saving moes can be activated by software. The
watchdog timer can be started by software at any time.

When left unconnected, pin PE/SWD is pulled high by a weak internall pull-up. This is done to
provide system protection on default.

The logic-level applied to pin PE/SWD can be changed during program execution to allow or to
block the use of the power saving modes without any effect on the on-chip watchdog circuitry.

SAB 80C515A/83C515A-5

Semiconductor Group

Requirements for Hardware Power Down Mode

There is no dedicated pin to enable the Hardware Power Down Mode. The control pin PE/SWD
has no control function in this mode. It enables and disables only the use of software controlled
power saving modes.

Software Controlled Power Saving Modes

All of these modes are entered by software. Special function register PCON (power control
register, address is 87

) is used to select one of these modes.

Slow Down Mode

During slow down operation all signal frequencies that are derived from the oscillator clock, are
divided by eight, also the clockout signal and and the watchdog timer count.

The slow down mode is enabled by setting bit SD. The controller actually enters the slow down
mode after a short synchronisation period (max. 2 machine cycles).

The slow down mode is disabled by clearing bit SD.

Idle Mode

During idle mode all peripherals of the SAB 80C515A (except for the watchdog timer) are still
supplied by the oscillator clock. Thus the user has to take care which peripheral should
continue to run and which has to be stopped during Idle.

The procedure to enter the Idle mode is similar to the one entering the power down mode. The
two bits IDLE and IDLS must be set by two consecutive instructions to minimize the chance of
unintentional activating of the idle mode.

There are two ways to terminate the idle mode:

The idle mode can be terminated by activating any enabled interrupt. This interrupt will be

serviced and the instruction to be executed following the RETI instruction will be the one
following the instruction that set the bit IDLS.

The other way to terminate the idle mode, is a hardware reset. Since the oscillator is still

running, the hardware reset must be held active only for two machine cycles for a complete
reset.

Normally the port pins hold the logical state they had at the time idle mode was activated. If
some pins are programmed to serve their alternate functions they still continue to output during
idle mode if the assigned function is on. The control signals ALE and PSEN hold at logic high
levels (see table 5).

SAB 80C515A/83C515A-5

Semiconductor Group

Software Power Down Mode

The power down mode is entered by two consecutive instructions directly following each other.
The first instruction has to set the flag PDE (power down enable) and must not set PDS (power
down set). The following instruction has to set the start bit PDS. Bits PDE and PDS will
automatically be cleared after having been set.

The instruction that sets bit PDS is the last instruction executed before going into power down
mode. The only exit from power down mode is a hardware reset.

The status of all output lines of the controller can be looked up in table 5.

Hardware Controlled Power Down Mode

The pin HWPD controls this mode. If it is on logic high level (inactive) the part is running in the
normal operating modes. If pin HWPD gets active (low level) the part enters the Hardware
Power Down Mode; this is independent of the state of pin PE/SWD.

HWPD is sampled once per machine cycle. If it is found active, the device starts a complete
internal reset sequence. The watchdog timer is stopped and its status flag WDTS is cleared
exactly the same effects as a hardware reset. In this phase the power consumption is not yet
reduced. After completion of the internal reset both oscillators of the chip are disabled. At the
same time the port pins and several control lines enter a floating state as shown in table 5. In
this state the power consumption is reduced to the power down current IPD. Also the supply
voltage can be reduced. Table 5 also lists the voltages which may be applied at the pins during
Hardware Power Down Mode without affecting the low power consumption.

Termination of HWPD Mode:

This power down state is maintained while pin HWPD is held active. If HWPD goes to high level
(inactive state) an automatic start up procedure is performed:

First the pins leave their floating condition and enter their default reset state (as they had

immediately before going to float state).

Both oscillators are enabled. The oscillator watchdog's RC oscillator starts up very fast (typ.

less than 2 ms).

Because the oscillator watchdog is active it detects a failure condition if the on-chip oscillator

hasn't yet started. Hence, the watchdog keeps the part in reset and supplies the internal
clock from the RC oscillator.

Finally, when the on-chip oscillator has started, the oscillator watchdog releases the part

from reset with oscillator watchdog status flag set.
When automatic start of the watchdog was enabled (PE/SWD connected to

the

Watchdog Timer will start, too (with its default reload value for time-out period).

The Reset pin overrides the Hardware Power Down function, i.e. if reset gets active during

Hardware Power Down it is terminated and the device performs the normal
resetfunction.(Thus, pin Reset has to be inactive during Hardware Power Down Mode).
function.(Thus, pin Reset has to be inactive during Hardware Power Down Mode).

SAB 80C515A/83C515A-5

Semiconductor Group

Table 5
Status of all pins during Idle Mode, Power Down Mode and Hardware Power
Down Mode

Pins

Idle Mode

Last instruction

executed from

Power Down Mode

Last instruction

executed from

Hardware Power
Down

internal

ROM

external

ROM

internal

ROM

external

ROM

Status

Data

float

Data

float

Data
alt outputs

Dat
alt outputsa

Data
last outputs

floating

Data

Address

Data

Data
alt outputs

Data
last output

outputs

Data
alt outputs

Data
last outputs

Data
last output

disabled

Data
alt output

Data
last output

input

function

active input

PE/SWD

active input pull-up
disabled

XTAL1

active output

XTAL2

disabled input
function

PSEN

high

low

floating output

ALE

high

low

AREF

AGND

active supply pins

RESET

active input must
be high

Applied voltage range at pin

;

AREF

AGND

SAB 80C515A/83C515A-5

Semiconductor Group

Serial Interface

The SAB 80C515A has a full duplex and receive buffered serial interface. It is functionally
identical with the serial interface of the SAB 8051.

Table 6 shows possible configurations and the according baud rates.

Table 6
Baud Rate Generation

Mode

Mode 0

8-Bit
syn-
chron-
ous
channel

Baud-
rate

O SC

=12 MHz

O SC

=16 MHz

O SC

=18 MHz

1 MHz

1.33 MHz

1.5 MHz

derived from

OSC

Mode

Mode 1

8-Bit
UART

Baud-
rate

OSC

=12 MHz

OSC

=16 MHz

OSC

=18 MHz

1 Baud 62.5 kBaud

1 Baud 83 kBaud

1 Baud 93.7 kBaud

183 Baud 375 kBaud

244 Baud 500 kBaud

2375

Baud

562.5

kBaud

derived from

Timer 1

10-Bit Baudrate
Generator

Mode

Mode 2

Mode 3

9-Bit
UART

Baud-
rate

OSC =

12 MHz

OSC

=16 MHz

OSC

=18 MHz

187.5 kBaud/
375 kBaud

250 Baud/
500 kBaud

281.2 kBaud/
562.5 kBaud

1 Baud
62.5 kBaud

1 Baud
83.3 kBaud

1 Baud
93.7 kBaud

183 Baud 75 kBaud

244 Baud 500 kBaud

275 Baud 562.5 kBaud

derived from

OSC/

Timer 1

10-Bit
Baudrate
Generator

SAB 80C515A/83C515A-5

Semiconductor Group

The Serial Interface can operate in 4 modes:

Mode 0: Shift register mode:

Serial data enters and exits through R

D. T

D outputs the shift clock 8 data bits

are transmitted/received (LSB first). The baud rate is fixed at 1/12 of the oscillator fre-
quency.

Mode 1: 8-bit UART, variable baud rate:

10-bit are transmitted (through T

D) or received (through R

D): a start bit (0), 8

data bits (LSB first), and a stop bit (1). On reception, the stop bit goes into RB80 in
special function register SCON. The baud rate is variable.

Mode 2: 9-bit UART, fixed baud rate:

11-bit are transmitted (through T

D) or received (through R

D): a start bit (0), 8

data bits (LSB first), a programmable 9th, and a stop bit (1). On transmission, the 9th
data bit (TB80 in SCON) can be assigned to the value of 0 or 1. For example, the par-
ity bit (P in the PSW) could be moved into TB80 or a second stop bit by setting TB80
to 1. On reception the 9th data bit goes into RB80 in special function register SCON,
while the stop bit is ignored. The baud rate is programmable to either 1/32 or 1/64 of
the oscillator frequency.

Mode 3: 9-bit UART, variable baud rate:

11-bit are transmitted (through T

D) or received (through R

D): a start bit (0), 8

data bits (LSB first), a programmable 9th, and a stop bit (1). In fact, mode 3 is the
same as mode 2 in all respects except the baud rate. The baud rate in mode 3 is vari-
able.

Variable Baud Rates for Serial Interface

Variable baud rates for modes 1 and 3 of serial interface can be derived from either timer 1 or
a new dedicated Baudrate Generator.

The baud rate is generated by a free running 10-bit timer with programmable reload register.

The default value after reset in the reload registers SRELL and SRELH provides a baud rate of
4.8 kBaud (SMOD = 0) or 9.6 kBaud (SMOD = 1) at 12 MHz oscillator frequency. This guaran-
tees full compatibility to the SAB 80C515.

Mode 1.3 baud rate =

SMOD

OSC

64 * (2

- SREL)

SAB 80C515A/83C515A-5

Semiconductor Group

Fail Safe Units

The SAB 80C515A offers enhanced fail safe mechanisms, which allow an automatic recovery
from software upset or hardware failure:

a programmable watchdog timer (WDT), with variable time-out period from 512

s up to

appr. 1.1 s @12 MHz. Upward compatible to SAB 80C515 watchdog timer.

an oscillator watchdog (OWD) which monitors the on-chip oscillator and forces the

microcontroller into reset state, in case the on-chip oscillator fails; it also controls the restart
from the Hardware Power Down Mode and provides the clock for a fast internal reset after
power-on.

Programmable Watchdog Timer

The WDT can be activated by hardware or software.

Hardware initialization is done when pin PE/SWD (Pin 4) is held high during RESET. The
SAB 80C515A then starts program execution with the WDT running. Since pin PE/SWD is only
sampled during Reset, the WDT cannot be started externally during normal operation.

Software initialization is done by setting bit SWDT in SFR IEN1.

A refresh of the watchdog timer is done by setting bits WDT (SFR IEN0) and SWDT
consecutively. This double instruction sequence has been implemented to increase system
security.

When a watchdog timer reset occurs, the watchdog timer keeps on running, but a status flag
WDTS (SFR IP0) is set. This flag can also be cleared by software.

Figure 7 shows the block diagram of the programmable Watchdog Timer.

Oscillator Watchdog

The unit serves three functions:

Monitoring of the on-chip oscillator's function.

The watchdog monitors the on-chip oscillator's frequency; if it is lower than the frequency of
the auxiliary RC oscillator in the watchdog unit, the internal clock is supplied by the RC
oscillator and the device is forced into reset; if the failure condition disappears (i.e. the on-
chip oscillator has again a higher frequency than the RC oscillator), the part executes a final
reset phase of appr. 0.25 ms in order to allow the oscillator to stabilize; then the oscillator
watchdog reset is released and the part starts program execution again.

Restart from the Hardware Power Down Mode.

If the Hardware Power Down Mode is terminated the oscillator watchdog has to control the
correct start-up of the on-chip oscillator and to restart the program. The oscillator watchdog
function is only part of the complete Hardware Power Down sequence; however, the
watchdog works identically to the monitoring function.

Fast internal reset after power-on.

In this function the oscillator watchdog unit provides a clock supply for the reset before the
on-chip oscillator has started. In this case the oscillator watchdog unit also works identically
to the monitoring function.

SAB 80C515A/83C515A-5

Semiconductor Group

Fast internal reset after power-on

The SAB 80C515A can use the oscillator watchdog unit for a fast internal reset procedure after
power-on.

Normally members of the 8051 family (like the SAB 80C515) enter their default reset state not
before the on-chip oscillator starts. The reason is that the external reset signal must be
internally synchronized and processed in order to bring the device into the correct reset state.
Especially if a crystal is used the start up time of the oscillator is relatively long (typ. 1 ms).
During this time period the pins have an undefined state which could have severe effects e.g.
to actuators connected to port pins.

In the SAB 80C515A the oscillator watchdog unit avoids this situation. After power-on the
oscillator watchdog's RC oscillator starts working within a very short start-up time (typ. less than
2 ms). In the following the watchdog circuitry detects a failure condition for the on-chip oscillator
because this has not yet started (a failure is always recognized if the watchdog's RC oscillator
runs faster than the on-chip oscillator). As long as this condition is valid the watchdog uses the
RC oscillator output as clock source for the chip rather than the on-chip oscillator's output. This
allows correct resetting of the part and brings also all ports to the defined state.

Delay time between power-on and correct reset state:

Typ.: 18

Max.: 34

Instruction Set

The SAB 80C515A / 83C515A-5 has the same instruction set as the industry standard 8051
microcontroller.

A pocket guide is available which contains the complete instruction set in functional and
hexadecimal order. Furtheron it provides helpful information about Special Function Registers,
Interrupt Vectors and Assembler Directives.

Literature Information

Title

Ordering No.

Microcontroller Family SAB 8051 Pocket Guide

B158-H6497-X-X-7600

SAB 80C515A/83C515A-5

Semiconductor Group

Absolute Maximum Ratings

Ambient temperature under bias

40 to 85 °C

Storage temperature

65 to 150 °C

Voltage on

pins with respect to ground (

)

0.5 V to 6.5 V

Voltage on any pin with respect to ground (

)

0.5 to

+ 0.5 V

Input current on any pin during overload condition

10mA to + 10 mA

Absolute sum of all input currents during overload condition

|100 mA|

Power dissipation

1 W

Note Stresses above those listed under "Absolute Maximum Ratings" may cause permanent

damage of the device. This is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for longer
periods may affect device reliability. During overload conditions (V

)

theVoltage on V

pins with respect to ground (V

) must not exeed the values defind-

ed by the absolute maximum ratings.

DC Characteristics

= 5 V + 10 %, 15 %;

= 0 V

= 0 to 70 °C for the SAB 80C515A

40 to 85 °C for the SAB 80C515A-T3

Parameter

Symbol

Limit Values

Unit

Test condition

min.

max.

Input low voltage
(exept EA,RESET, HWPD)

0.5

0.2

0.1

Input low voltage EA

I L1

0.5

0.2

0.3

Input low voltage
(HWPD, RESET)

I L2

0.5

0.2

+ 0.1

Input high voltage (exept
RESET, XTAL2 and HWPD)

0.2

+ 0.9

+ 0.5

Input high voltage to XTAL2

IH1

0.7

+ 0.5

Input high voltage to RESET
and HWPD

IH2

0.6

+ 0.5

SAB 80C515A/83C515A-5

Semiconductor Group

DC Characteristics (cont'd)

Parameter

Symbol

Limit Values

Unit

Test condition

min.

max.

Output low voltage
(ports 1, 2, 3, 4, 5)

0.45

1.6 mA

Output low voltage
(ports 0, ALE, RESET)

OL1

0.45

3.2 mA

Output high voltage,
(ports1, 2, 3, 4, 5)

2.4
0.9

C C

V
V

Output high voltage
(port 0 in external bus mode,-
ALE, PSEN)

OH1

2.4
0.9

C C

V
V

800

Logic 0 input current
(ports 1, 2, 3, 4, 5)

I N

2 V

Logical 1-to-0 transition
current, ports 1, 2, 3, 4, 5

650

I N

2 V

Input leakage current
(port 0, EA, P6, HWPD)

L I

100

150

nA
nA

0.45

I N

0.45

I N

> 100 °C

Input low current to RESET
for reset

IL2

100

I N

0.45

Input low current (XTAL2)

I L3

I N

0.45 V

Input low current (PE/SWD)

I L

I N

0.45 V

Pin capacitance

I O

1 MHz,

= 25 °C

Power-supply current:
Active mode, 12 MHz

Active mode, 18 MHz

Idle mode, 12 MHz

Idle mode, 18 MHz

Slow down mode, 12 MHz
Slow down mode, 18 MHz
Power Down Mode

26
35
11.8
14.2
9
10
50

mA
mA
mA
mA
mA
mA

5 V

2 ... 5.5 V

Notes see page 43.

SAB 80C515A/83C515A-5

Semiconductor Group

Notes for page 44:

1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed

on the

of ALE and ports 1, 3, 4 and 5. The noise is due to external bus capacitance

discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during
bus operation. In the worst case (capacitive loading > 100 pF), the noise pulse on ALE line
may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a schmitt-trigger,
or use an address latch with a schmitt-trigger strobe input.

2) Capacitive loading on ports 0 and 2 may cause the

on ALE and PSEN to momentarily

fall

below the

0.9

C C

specification when the address lines are stabilizing.

(Software Power Down Mode) is measured under following conditions:

EA = RESET =

; Port0 = Port6 =

; XTAL1 = N.C.; XTAL2 =

;

PE/SWD =

; HWPD =

; V

AGND

;

ARef

; all other pins are

disconnected.

(Hardware Power Down Mode): independent of any particular pin connection.

(active mode) is measured with:

XTAL2 driven with

CLCH

CHCL

= 5 ns,

+ 0.5 V,

0.5 V; XTAL1 = N.C.;

EA = PE/SWD =

; Port0 = Port6 =

; HWPD =

; RESET =

;

all other pins are disconnected.

would be slightly higher if a crystal oscillator is used (ap-

pr. 1 mA).

(Idle mode) is measured with all output pins disconnected and with all peripherals dis-

abled; XTAL2 driven with

CLCH

CHCL

= 5 ns,

+ 0.5 V,

0.5 V; XTAL1

= N.C.; RESET =

; HWPD =

; Port0 = Port6 =

; EA = PE/SWD =

SS;

all other

pins are disconnected;

(slow down mode) is measured with all output pins disconnected and with all peripherals

disabled;
XTAL2 driven with

CLCH

CHCL

= 5 ns,

+ 0.5 V,

0.5 V; XTAL1 =

N.C.; RESET =

; HWPD =

; Port6 =

; EA = PE/SWD =

; all other pins are

disconnected;

Max

at other frequencies is given by:

active mode:

(max) = 1.5

OSC

+ 8

idle mode:

(max)= 0.4

OSC

+ 7

where

OSC

is the oscillator frequency in MHz.

values are given in mA and

measured at

= 5 V.

SAB 80C515A/83C515A-5

Semiconductor Group

A/D Converter Characteristics

= 5 V + 10 %, 15 %;

= 0 V

AREF

5 %;

AGND

0.2 V;

0 to 70 °C for the SAB 80C515A/83C515A-5

40 to 85 °C for the SAB 80C515A-T3/83C515A-5-T3

Parameter

Symbol

Limit values

Unit

Test condition

min.

typ.

max.

Analog input capacitance

Sample time
(inc. load time)

Conversion time
(inc. sample time)

Total unadjusted error

TUE

LSB

AREF

AGND

AREF

supply current

REF

= (8*2

ADCL

)

OSC

; (

= 1/

ADC

;

ADC

OSC

/(8*2

ADCL

))

This parameter specifies the time during the input capacitance

can be charged/discharged by the

external source. It must be guaranteed, that the input capacitance

, is fully loaded within this time.

4TCY is 2

s at the

OSC

= 16 MHz. After the end of the sample time

, changes of the analog input

voltage have no effect on the conversion result.

This parameter includes the sample time

14TCY is 7

s at

OSC

= 16 MHz.

SAB 80C515A/83C515A-5

Semiconductor Group

AC Characteristics

= 5 V + 10 %, 15 %;

= 0 V

0 to 70 °C for the SAB 80C515A/83C515A-5

40 to 85 °C for the SAB 80C515A-T3/83C515A-5-T3

(

for port 0, ALE and

PSEN outputs = 100 pF;

for all other outputs = 80 pF)

Parameter

Symbol

Limit values

Unit

18 MHz clock

Variable clock

CLCL

= 3.5 MHz to 18 MHz

min.

max.

min.

max.

Program Memory Characteristics

ALE pulse width

LHLL

C LCL

Address setup to ALE

AVLL

C LCL

Address hold after ALE

LLAX

C LCL

ALE to valid
instruction in

LLIV

122

C LCL

100 ns

ALE to PSEN

LLPL

C LCL

PSEN pulse width

PLPH

132

C LCL

PSEN to valid
instruction in

PLIV

C LCL

Input instruction hold
after PSEN

PXIX

Input instruction float
after PSEN

PXIZ

C LCL

Address valid after
PSEN

PXAV

C LCL

Address to valid
instruction in

AVIV

218

C LCL

Address float to PSEN

A ZPL

Interfacing the SAB 80C515A to devices with float times up to 45 ns is permissible.

This limited bus contention will not cause any damage to port 0 drivers.

SAB 80C515A/83C515A-5

Semiconductor Group

AC Characteristics (cont'd)

Parameter

Symbol

Limit values

Unit

18 MHz clock

Variable clock

CLCL

= 3.5 MHz to 18 MHz

min

max.

min.

max.

External Data Memory Characteristics

RD pulse width

RLRH

233

CLCL

100

WR pulse width

WLWH

233

CLCL

100

Address hold after
ALE

LLAX2

CLCL

RD to valid data in

RLDV

128

CLCL

150

DATA hold after RD

RHDX

Data float after RD

RHDZ

CLCL

ALE to valid data in

LLDV

294

CLCL

150

Address to valid
data in

AVDV

335

CLCL

165

ALE to WR or RD

LLWL

117

217

CLCL

+ 50

WR or RD high to
ALE high

WHLH

CLCL

+ 40

Address valid to WR

AVWL

CLCL

130

Data valid to WR
transition

QVWX

CLCL

Data setup before WR

QVWH

239

CLCL

150

Data hold after WR

WHQX

CLCL

Address float after RD

RLAZ

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