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Data Sheet 12.96 (Advance Information)

Microcomputer Components

C167CR-16RM

16-Bit CMOS Single-Chip Microcontrollers

Controller Area Network (CAN): License of Robert Bosch GmbH

C167CR-16RM
Revision History:

Original Version 12.96 (Advance Information)

Previous Releases:

Page

Subjects (compared to Data Sheet C167CR, 06.95)

Incremental Interface Mode added.

T3 capture trigger for CAPREL added.

Edition 12.96

Published by Siemens AG, Bereich Halbleiter, Marketing-Kommunikation
Balanstraße 73, D-81541 München.

As far as patents or other rights of third parties are concerned, liability is only assumed for
components per se, not for applications, processes and circuits implemented within components or
assemblies.

The information describes the type of component and shall not be considered as assured
characteristics.

Terms of delivery and rights to change design reserved.

For questions on technology, delivery and prices please contact the Offices of Siemens
Aktiengesellschaft in Germany or the Siemens Companies and Representatives worldwide.

Due to technical requirements components may contain dangerous substances. For information on
the type in question please contact your nearest Siemens Office, Components Group.

Siemens AG is an approved CECC manufacturer.

High Performance 16-bit CPU with 4-Stage Pipeline

100 ns Instruction Cycle Time at 20 MHz CPU Clock

500 ns Multiplication (16

16 bit), 1

s Division (32 / 16 bit)

Enhanced Boolean Bit Manipulation Facilities

Additional Instructions to Support HLL and Operating Systems

Single-Cycle Context Switching Support

Clock Generation via on-chip PLL or via direct clock input

Up to 16 MBytes Linear Address Space for Code and Data

2 KBytes On-Chip Internal RAM (IRAM)

2 KBytes On-Chip Extension RAM (XRAM)

128 KBytes On-Chip ROM

Programmable External Bus Characteristics for Different Address Ranges

8-Bit or 16-Bit External Data Bus

Multiplexed or Demultiplexed External Address/Data Buses

Five Programmable Chip-Select Signals

Hold- and Hold-Acknowledge Bus Arbitration Support

1024 Bytes On-Chip Special Function Register Area

Idle and Power Down Modes

8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event
Controller (PEC)

16-Priority-Level Interrupt System with 56 Sources, Sample-Rate down to 50 ns

16-Channel 10-bit A/D Converter with 9.7

s Conversion Time

Two 16-Channel Capture/Compare Units

4-Channel PWM Unit

Two Multi-Functional General Purpose Timer Units with 5 Timers

Two Serial Channels (Synchronous/Asynchronous and High-Speed-Synchronous)

On-Chip CAN Interface with 15 Message Objects (Full-CAN/Basic-CAN)

Programmable Watchdog Timer

Up to 111 General Purpose I/O Lines, partly with Selectable Input Thresholds and Hysteresis

Supported by a Wealth of Development Tools like C-Compilers, Macro-Assembler Packages,
Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers,
Programming Boards

On-Chip Bootstrap Loader

144-Pin MQFP Package (EIAJ)

This document describes the SAB-C167CR-16RM and the SAK-C167CR-16RM. For simplicity all
versions are referred to by the term C167CR-16RM throughout this document.

C16x-Family of
High-Performance CMOS 16-Bit Microcontrollers

Advance Information

C167CR-16RM 16-Bit Microcontroller

C167CR-16RM

12.96

20Dec96@09:25h Intermediate Version

Semiconductor Group

C167CR-16RM

Introduction

The C167CR-16RM is a new derivative of the Siemens C16x Family of full featured single-chip
CMOS microcontrollers. It combines high CPU performance (up to 10 million instructions per
second) with high peripheral functionality and enhanced IO-capabilities. It also provides on-chip
ROM, on-chip high-speed RAM and clock generation via PLL.

Figure 1
Logic Symbol

Ordering Information

Type

Ordering Code

Package

Function

SAB-C167CR-16RM

Q67121-D...

P-MQFP-144-1

16-bit microcontroller with
2 * 2 KByte RAM
Temperature range 0 to +70 °C

SAF-C167CR-16RM

Q67121-D...

P-MQFP-144-1

16-bit microcontroller with
2 * 2 KByte RAM
Temperature range -40 to +85 °C

SAK-C167CR-16RM

Q67121-D...

P-MQFP-144-1

16-bit microcontroller with
2 * 2 KByte RAM
Temperature range -40 to +125 °C

C167CR-

16RM

20Dec96@09:25h Intermediate Version

Semiconductor Group

C167CR-16RM

Note: The ordering codes (Q67121-D...) for the Mask-ROM versions are defined for each product

after verifiction of the respective ROM code.

Pin Configuration
(top view)

Figure 2

C167CR-16RM

A22/CAN_TxD

/CAN_RxD

20Dec96@09:25h Intermediate Version

Semiconductor Group

C167CR-16RM

Pin Definitions and Functions

Symbol

Pin
Number

Input (I)
Output (O)

Function

P6.0
P6.7

1 -
8

1
...
5
6
7
8

I/O

O
...
O
I
O
O

Port 6 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-
impedance state. Port 6 outputs can be configured as push/
pull or open drain drivers.
The following Port 6 pins also serve for alternate functions:
P6.0

CS0

Chip Select 0 Output

...

P6.4

CS4

Chip Select 4 Output

P6.5

HOLD

External Master Hold Request Input

P6.6

HLDA

Hold Acknowledge Output

P6.7

BREQ

Bus Request Output

P8.0
P8.7

9 -
16

9
...
16

I/O

I/O
...
I/O

Port 8 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-
impedance state. Port 8 outputs can be configured as push/
pull or open drain drivers. The input threshold of Port 8 is
selectable (TTL or special).
The following Port 8 pins also serve for alternate functions:
P8.0

CC16IO

CAPCOM2: CC16 Cap.-In/Comp.Out

...

P8.7

CC23IO

CAPCOM2: CC23 Cap.-In/Comp.Out

P7.0
P7.7

19 -
26

19
...
22
23
...
26

I/O

O
...
O
I/O
...
I/O

Port 7 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-
impedance state. Port 7 outputs can be configured as push/
pull or open drain drivers. The input threshold of Port 7 is
selectable (TTL or special).
The following Port 7 pins also serve for alternate functions:
P7.0

POUT0

PWM Channel 0 Output

...

P7.3

POUT3

PWM Channel 3 Output

P7.4

CC28IO

CAPCOM2: CC28 Cap.-In/Comp.Out

...

P7.7

CC31IO

CAPCOM2: CC31 Cap.-In/Comp.Out

20Dec96@09:25h Intermediate Version

Semiconductor Group

C167CR-16RM

P5.0
P5.15

27 36
39 44

39
40
41
42
43
44

I
I

I
I
I
I
I
I

Port 5 is a 16-bit input-only port with Schmitt-Trigger
characteristics. The pins of Port 5 also serve as the (up to 16)
analog input channels for the A/D converter, where P5.x
equals ANx (Analog input channel x), or they serve as timer
inputs:
P5.10

T6EUD

GPT2 Timer T6 Ext.Up/Down Ctrl.Input

P5.11

T5EUD

GPT2 Timer T5 Ext.Up/Down Ctrl.Input

P5.12

T6IN

GPT2 Timer T6 Count Input

P5.13

T5IN

GPT2 Timer T5 Count Input

P5.14

T4EUD

GPT1 Timer T4 Ext.Up/Down Ctrl.Input

P5.15

T2EUD

GPT1 Timer T2 Ext.Up/Down Ctrl.Input

P2.0
P2.15

47 54
57 - 64

47
...
54
57

...
64

I/O

I/O
...
I/O
I/O
I
...
I/O
I
I

Port 2 is a 16-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-
impedance state. Port 2 outputs can be configured as push/
pull or open drain drivers. The input threshold of Port 2 is
selectable (TTL or special).
The following Port 2 pins also serve for alternate functions:
P2.0

CC0IO

CAPCOM: CC0 Cap.-In/Comp.Out

...

P2.7

CC7IO

CAPCOM: CC7 Cap.-In/Comp.Out

P2.8

CC8IO

CAPCOM: CC8 Cap.-In/Comp.Out,

EX0IN

Fast External Interrupt 0 Input

...

P2.15

CC15IO

CAPCOM: CC15 Cap.-In/Comp.Out,

EX7IN

Fast External Interrupt 7 Input

T7IN

CAPCOM2 Timer T7 Count Input

Pin Definitions and Functions (cont'd)

Symbol

Pin
Number

Input (I)
Output (O)

Function

20Dec96@09:25h Intermediate Version

Semiconductor Group

C167CR-16RM

P3.0
P3.13,
P3.15

65 70,
73 80,
81

65
66
67
68
69
70

73
74

75
76
77
78
79

80
81

I/O
I/O
I/O

I
O
I
O
I
I

I
I

I/O
I/O
O
I/O
O
O
I/O
O

Port 3 is a 15-bit (P3.14 is missing) bidirectional I/O port. It is
bit-wise programmable for input or output via direction bits.
For a pin configured as input, the output driver is put into high-
impedance state. Port 3 outputs can be configured as push/
pull or open drain drivers. The input threshold of Port 3 is
selectable (TTL or special).
The following Port 3 pins also serve for alternate functions:
P3.0

T0IN

CAPCOM Timer T0 Count Input

P3.1

T6OUT

GPT2 Timer T6 Toggle Latch Output

P3.2

CAPIN

GPT2 Register CAPREL Capture Input

P3.3

T3OUT

GPT1 Timer T3 Toggle Latch Output

P3.4

T3EUD

GPT1 Timer T3 Ext.Up/Down Ctrl.Input

P3.5

T4IN

GPT1 Timer T4 Input for
Count/Gate/Reload/Capture

P3.6

T3IN

GPT1 Timer T3 Count/Gate Input

P3.7

T2IN

GPT1 Timer T2 Input for
Count/Gate/Reload/Capture

P3.8

MRST

SSC Master-Rec./Slave-Transmit I/O

P3.9

MTSR

SSC Master-Transmit/Slave-Rec. O/I

P3.10

ASC0 Clock/Data Output (Asyn./Syn.)

P3.11

ASC0 Data Input (Asyn.) or I/O (Syn.)

P3.12

BHE

Ext. Memory High Byte Enable Signal,

WRH

Ext. Memory High Byte Write Strobe

P3.13

SCLK

SSC Master Clock Outp./Slave Cl. Inp.

P3.15

CLKOUT

System Clock Output (=CPU Clock)

P4.0
P4.7

85 - 92

85
...
89
90

I/O

O
...
O
O
I
O
O
O

Port 4 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-
impedance state.
In case of an external bus configuration, Port 4 can be used to
output the segment address lines:
P4.0

A16

Least Significant Segment Addr. Line

...

P4.4

A20

Segment Address Line

P4.5

A21

Segment Address Line,

CAN_RxD CAN Receive Data Input

P4.6

A22

Segment Address Line,

CAN_TxD CAN Transmit Data Output

P4.7

A23

Most Significant Segment Addr. Line

External Memory Read Strobe. RD is activated for every
external instruction or data read access.

Pin Definitions and Functions (cont'd)

Symbol

Pin
Number

Input (I)
Output (O)

Function

20Dec96@09:25h Intermediate Version

Semiconductor Group

C167CR-16RM

WR/
WRL

External Memory Write Strobe. In WR-mode this pin is
activated for every external data write access. In WRL-mode
this pin is activated for low byte data write accesses on a 16-
bit bus, and for every data write access on an 8-bit bus. See
WRCFG in register SYSCON for mode selection.

READY

Ready Input. When the Ready function is enabled, a high
level at this pin during an external memory access will force
the insertion of memory cycle time waitstates until the pin
returns to a low level.

ALE

Address Latch Enable Output. Can be used for latching the
address into external memory or an address latch in the
multiplexed bus modes.

External Access Enable pin. A low level at this pin during and
after Reset forces the C167CR-16RM to begin instruction
execution out of external memory. A high level forces
execution out of the internal ROM. ROMless versions must
have this pin tied to `0'.

PORT0:
P0L.0
P0L.7,
P0H.0 -
P0H.7

100
107
108,
111-117

I/O

PORT0 consists of the two 8-bit bidirectional I/O ports P0L
and P0H. It is bit-wise programmable for input or output via
direction bits. For a pin configured as input, the output driver
is put into high-impedance state.
In case of an external bus configuration, PORT0 serves as
the address (A) and address/data (AD) bus in multiplexed bus
modes and as the data (D) bus in demultiplexed bus modes.
Demultiplexed bus modes:
Data Path Width:

8-bit

16-bit

P0L.0 P0L.7:

D0 D7

D0 - D7

P0H.0 P0H.7:

I/O

D8 - D15

Multiplexed bus modes:
Data Path Width:

8-bit

16-bit

P0L.0 P0L.7:

AD0 AD7

AD0 - AD7

P0H.0 P0H.7:

A8 - A15

AD8 - AD15

Pin Definitions and Functions (cont'd)

Symbol

Pin
Number

Input (I)
Output (O)

Function

20Dec96@09:25h Intermediate Version

Semiconductor Group

C167CR-16RM

PORT1:
P1L.0
P1L.7,
P1H.0 -
P1H.7

118
125
128
135

132
133
134
135

I/O

I
I
I
I

PORT1 consists of the two 8-bit bidirectional I/O ports P1L
and P1H. It is bit-wise programmable for input or output via
direction bits. For a pin configured as input, the output driver
is put into high-impedance state. PORT1 is used as the 16-bit
address bus (A) in demultiplexed bus modes and also after
switching from a demultiplexed bus mode to a multiplexed bus
mode.
The following PORT1 pins also serve for alternate functions:
P1H.4

CC24IO

CAPCOM2: CC24 Capture Input

P1H.5

CC25IO

CAPCOM2: CC25 Capture Input

P1H.6

CC26IO

CAPCOM2: CC26 Capture Input

P1H.7

CC27IO

CAPCOM2: CC27 Capture Input

XTAL1

XTAL2

138

137

XTAL1:

Input to the oscillator amplifier and input to the
internal clock generator

XTAL2:

Output of the oscillator amplifier circuit.

To clock the device from an external source, drive XTAL1,
while leaving XTAL2 unconnected. Minimum and maximum
high/low and rise/fall times specified in the AC Characteristics
must be observed.

RSTIN

140

Reset Input with Schmitt-Trigger characteristics. A low level at
this pin for a specified duration while the oscillator is running
resets the C167CR-16RM. An internal pullup resistor permits
power-on reset using only a capacitor connected to

RSTOUT 141

Internal Reset Indication Output. This pin is set to a low level
when the part is executing either a hardware-, a software- or a
watchdog timer reset. RSTOUT remains low until the EINIT
(end of initialization) instruction is executed.

NMI

142

Non-Maskable Interrupt Input. A high to low transition at this
pin causes the CPU to vector to the NMI trap routine. When
the PWRDN (power down) instruction is executed, the NMI
pin must be low in order to force the C167CR-16RM to go into
power down mode. If NMI is high, when PWRDN is executed,
the part will continue to run in normal mode.
If not used, pin NMI should be pulled high externally.

AREF

Reference voltage for the A/D converter.

AGND

Reference ground for the A/D converter.

Flash programming voltage. This pin accepts the
programming voltage for flash versions of the C167CR-16RM.
Note: This pin is not connected (NC) on non-flash versions.

Pin Definitions and Functions (cont'd)

Symbol

Pin
Number

Input (I)
Output (O)

Function

20Dec96@09:25h Intermediate Version

Semiconductor Group

C167CR-16RM

17, 46,
56, 72,
82, 93,
109,
126,
136, 144

Digital Supply Voltage:
+ 5 V during normal operation and idle mode.

2.5 V during power down mode.

18, 45,
55, 71,
83, 94,
110,
127,
139, 143

Digital Ground.

Pin Definitions and Functions (cont'd)

Symbol

Pin
Number

Input (I)
Output (O)

Function

20Dec96@09:25h Intermediate Version

Semiconductor Group

C167CR-16RM

Functional Description

The architecture of the C167CR-16RM combines advantages of both RISC and CISC processors
and of advanced peripheral subsystems in a very well-balanced way. The following block diagram
gives an overview of the different on-chip components and of the advanced, high bandwidth internal
bus structure of the C167CR-16RM.

Note: All time specifications refer to a CPU clock of 20 MHz

(see definition in the AC Characteristics section).

Figure 3
Block Diagram

20Dec96@09:25h Intermediate Version

Semiconductor Group

C167CR-16RM

Memory Organization

The memory space of the C167CR-16RM is configured in a Von Neumann architecture which
means that code memory, data memory, registers and I/O ports are organized within the same
linear address space which includes 16 MBytes. The entire memory space can be accessed
bytewise or wordwise. Particular portions of the on-chip memory have additionally been made
directly bitaddressable.

The C167CR-16RM contains 128 KBytes of on-chip mask-programmable ROM for code or
constant data. The lower 32 KBytes of the on-chip ROM can be mapped either to segment 0 or
segment 1.

2 KBytes of on-chip Internal RAM are provided as a storage for user defined variables, for the
system stack, general purpose register banks and even for code. A register bank can consist of up
to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0, ..., RL7, RH7) so-called General Purpose
Registers (GPRs).

1024 bytes (2 * 512 bytes) of the address space are reserved for the Special Function Register
areas (SFR space and ESFR space). SFRs are wordwide registers which are used for controlling
and monitoring functions of the different on-chip units. Unused SFR addresses are reserved for
future members of the C16x family.

2 KBytes of on-chip Extension RAM (XRAM) are provided to store user data, user stacks or code.
The XRAM is accessed like external memory and therefore cannot be used for the system stack or
for register banks and is not bitadressable. The XRAM allows 16-bit accesses with maximum speed.

In order to meet the needs of designs where more memory is required than is provided on chip, up
to 16 MBytes of external RAM and/or ROM can be connected to the microcontroller.

20Dec96@09:25h Intermediate Version

Semiconductor Group

C167CR-16RM

External Bus Controller

All of the external memory accesses are performed by a particular on-chip External Bus Controller
(EBC). It can be programmed either to Single Chip Mode when no external memory is required, or
to one of four different external memory access modes, which are as follows:

16-/18-/20-/24-bit Addresses, 16-bit Data, Demultiplexed

16-/18-/20-/24-bit Addresses, 16-bit Data, Multiplexed

16-/18-/20-/24-bit Addresses, 8-bit Data, Multiplexed

16-/18-/20-/24-bit Addresses, 8-bit Data, Demultiplexed

In the demultiplexed bus modes, addresses are output on PORT1 and data is input/output on
PORT0 or P0L, respectively. In the multiplexed bus modes both addresses and data use PORT0 for
input/output.

Important timing characteristics of the external bus interface (Memory Cycle Time, Memory Tri-
State Time, Length of ALE and Read Write Delay) have been made programmable to allow the user
the adaption of a wide range of different types of memories and external peripherals.
In addition, up to 4 independent address windows may be defined (via register pairs ADDRSELx /
BUSCONx) which allow to access different resources with different bus characteristics. These
address windows are arranged hierarchically where BUSCON4 overrides BUSCON3 and
BUSCON2 overrides BUSCON1. All accesses to locations not covered by these 4 address windows
are controlled by BUSCON0.
Up to 5 external CS signals (4 windows plus default) can be generated in order to save external glue
logic. Access to very slow memories is supported via a particular `Ready' function.

A HOLD/HLDA protocol is available for bus arbitration and allows to share external resources with
other bus masters. The bus arbitration is enabled by setting bit HLDEN in register SYSCON. After
setting HLDEN once, pins P6.7...P6.5 (BREQ, HLDA, HOLD) are automatically controlled by the
EBC. In Master Mode (default after reset) the HLDA pin is an output. By setting bit DP6.7 to '1' the
Slave Mode is selected where pin HLDA is switched to input. This allows to directly connect the
slave controller to another master controller without glue logic.

For applications which require less than 16 MBytes of external memory space, this address space
can be restricted to 1 MByte, 256 KByte or to 64 KByte. In this case Port 4 outputs four, two or no
address lines at all. It outputs all 8 address lines, if an address space of 16 MBytes is used.

Note: When the on-chip CAN Module is to be used the segment address output on Port 4 must be

limited to 4 bits (ie. A19...A16) in order to enable the alternate function of the CAN interface
pins.

20Dec96@09:25h Intermediate Version

Semiconductor Group

C167CR-16RM

Central Processing Unit (CPU)

The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit
(ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divide
unit, a bit-mask generator and a barrel shifter.

Based on these hardware provisions, most of the C167CR-16RM's instructions can be executed in
just one machine cycle which requires 100 ns at 20-MHz CPU clock. For example, shift and rotate
instructions are always processed during one machine cycle independent of the number of bits to
be shifted. All multiple-cycle instructions have been optimized so that they can be executed very fast
as well: branches in 2 cycles, a 16

16 bit multiplication in 5 cycles and a 32-/16 bit division in

10 cycles. Another pipeline optimization, the so-called `Jump Cache', allows reducing the execution
time of repeatedly performed jumps in a loop from 2 cycles to 1 cycle.

Figure 4
CPU Block Diagram

20Dec96@09:25h Intermediate Version

Semiconductor Group

C167CR-16RM

The CPU disposes of an actual register context consisting of up to 16 wordwide GPRs which are
physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the
base address of the active register bank to be accessed by the CPU at a time. The number of
register banks is only restricted by the available internal RAM space. For easy parameter passing,
a register bank may overlap others.

A system stack of up to 2048 bytes is provided as a storage for temporary data. The system stack
is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP)
register. Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack
pointer value upon each stack access for the detection of a stack overflow or underflow.

The high performance offered by the hardware implementation of the CPU can efficiently be utilized
by a programmer via the highly efficient C167CR-16RM instruction set which includes the following
instruction classes:

Arithmetic Instructions
Logical Instructions
Boolean Bit Manipulation Instructions
Compare and Loop Control Instructions
Shift and Rotate Instructions
Prioritize Instruction
Data Movement Instructions
System Stack Instructions
Jump and Call Instructions
Return Instructions
System Control Instructions
Miscellaneous Instructions

The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes and words.
A variety of direct, indirect or immediate addressing modes are provided to specify the required
operands.

20Dec96@09:25h Intermediate Version

Semiconductor Group

C167CR-16RM

Interrupt System

With an interrupt response time within a range from just 250 ns to 600 ns (in case of internal
program execution), the C167CR-16RM is capable of reacting very fast to the occurence of non-
deterministic events.

The architecture of the C167CR-16RM supports several mechanisms for fast and flexible response
to service requests that can be generated from various sources internal or external to the
microcontroller. Any of these interrupt requests can be programmed to being serviced by the
Interrupt Controller or by the Peripheral Event Controller (PEC).

In contrast to a standard interrupt service where the current program execution is suspended and
a branch to the interrupt vector table is performed, just one cycle is `stolen' from the current CPU
activity to perform a PEC service. A PEC service implies a single byte or word data transfer between
any two memory locations with an additional increment of either the PEC source or the destination
pointer. An individual PEC transfer counter is implicity decremented for each PEC service except
when performing in the continuous transfer mode. When this counter reaches zero, a standard
interrupt is performed to the corresponding source related vector location. PEC services are very
well suited, for example, for supporting the transmission or reception of blocks of data. The
C167CR-16RM has 8 PEC channels each of which offers such fast interrupt-driven data transfer
capabilities.

A separate control register which contains an interrupt request flag, an interrupt enable flag and an
interrupt priority bitfield exists for each of the possible interrupt sources. Via its related register, each
source can be programmed to one of sixteen interrupt priority levels. Once having been accepted
by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For
the standard interrupt processing, each of the possible interrupt sources has a dedicated vector
location.

Fast external interrupt inputs are provided to service external interrupts with high precision
requirements. These fast interrupt inputs feature programmable edge detection (rising edge, falling
edge or both edges).

Software interrupts are supported by means of the `TRAP' instruction in combination with an
individual trap (interrupt) number.

The following table shows all of the possible C167CR-16RM interrupt sources and the
corresponding hardware-related interrupt flags, vectors, vector locations and trap (interrupt)
numbers:

Note: Three nodes in the table (X-Peripheral nodes) are prepared to accept interrupt requests from

integrated X-Bus peripherals. Nodes, where no X-Peripherals are connected, may be used
to generate software controlled interrupt requests by setting the respective XPnIR bit.

20Dec96@09:25h Intermediate Version

Semiconductor Group

C167CR-16RM

Source of Interrupt or
PEC Service Request

Request
Flag

Enable
Flag

Interrupt
Vector

Vector
Location

Trap
Number

CAPCOM Register 0

CC0IR

CC0IE

CC0INT

00'0040

CAPCOM Register 1

CC1IR

CC1IE

CC1INT

00'0044

CAPCOM Register 2

CC2IR

CC2IE

CC2INT

00'0048

CAPCOM Register 3

CC3IR

CC3IE

CC3INT

00'004C

CAPCOM Register 4

CC4IR

CC4IE

CC4INT

00'0050

CAPCOM Register 5

CC5IR

CC5IE

CC5INT

00'0054

CAPCOM Register 6

CC6IR

CC6IE

CC6INT

00'0058

CAPCOM Register 7

CC7IR

CC7IE

CC7INT

00'005C

CAPCOM Register 8

CC8IR

CC8IE

CC8INT

00'0060

CAPCOM Register 9

CC9IR

CC9IE

CC9INT

00'0064

CAPCOM Register 10

CC10IR

CC10IE

CC10INT

00'0068

CAPCOM Register 11

CC11IR

CC11IE

CC11INT

00'006C

CAPCOM Register 12

CC12IR

CC12IE

CC12INT

00'0070

CAPCOM Register 13

CC13IR

CC13IE

CC13INT

00'0074

CAPCOM Register 14

CC14IR

CC14IE

CC14INT

00'0078

CAPCOM Register 15

CC15IR

CC15IE

CC15INT

00'007C

CAPCOM Register 16

CC16IR

CC16IE

CC16INT

00'00C0

CAPCOM Register 17

CC17IR

CC17IE

CC17INT

00'00C4

CAPCOM Register 18

CC18IR

CC18IE

CC18INT

00'00C8

CAPCOM Register 19

CC19IR

CC19IE

CC19INT

00'00CC

CAPCOM Register 20

CC20IR

CC20IE

CC20INT

00'00D0

CAPCOM Register 21

CC21IR

CC21IE

CC21INT

00'00D4

CAPCOM Register 22

CC22IR

CC22IE

CC22INT

00'00D8

CAPCOM Register 23

CC23IR

CC23IE

CC23INT

00'00DC

CAPCOM Register 24

CC24IR

CC24IE

CC24INT

00'00E0

CAPCOM Register 25

CC25IR

CC25IE

CC25INT

00'00E4

CAPCOM Register 26

CC26IR

CC26IE

CC26INT

00'00E8

CAPCOM Register 27

CC27IR

CC27IE

CC27INT

00'00EC

CAPCOM Register 28

CC28IR

CC28IE

CC28INT

00'00E0

CAPCOM Register 29

CC29IR

CC29IE

CC29INT

00'0110

CAPCOM Register 30

CC30IR

CC30IE

CC30INT

00'0114

CAPCOM Register 31

CC31IR

CC31IE

CC31INT

00'0118

CAPCOM Timer 0

T0IR

T0IE

T0INT

00'0080

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C167CR-16RM

CAPCOM Timer 1

T1IR

T1IE

T1INT

00'0084

CAPCOM Timer 7

T7IR

T7IE

T7INT

00'00F4

CAPCOM Timer 8

T8IR

T8IE

T8INT

00'00F8

GPT1 Timer 2

T2IR

T2IE

T2INT

00'0088

GPT1 Timer 3

T3IR

T3IE

T3INT

00'008C

GPT1 Timer 4

T4IR

T4IE

T4INT

00'0090

GPT2 Timer 5

T5IR

T5IE

T5INT

00'0094

GPT2 Timer 6

T6IR

T6IE

T6INT

00'0098

GPT2 CAPREL Register

CRIR

CRIE

CRINT

00'009C

A/D Conversion Complete ADCIR

ADCIE

ADCINT

00'00A0

A/D Overrun Error

ADEIR

ADEIE

ADEINT

00'00A4

ASC0 Transmit

S0TIR

S0TIE

S0TINT

00'00A8

ASC0 Transmit Buffer

S0TBIR

S0TBIE

S0TBINT

00'011C

ASC0 Receive

S0RIR

S0RIE

S0RINT

00'00AC

ASC0 Error

S0EIR

S0EIE

S0EINT

00'00B0

SSC Transmit

SCTIR

SCTIE

SCTINT

00'00B4

SSC Receive

SCRIR

SCRIE

SCRINT

00'00B8

SSC Error

SCEIR

SCEIE

SCEINT

00'00BC

PWM Channel 0...3

PWMIR

PWMIE

PWMINT

00'00FC

CAN Interface

XP0IR

XP0IE

XP0INT

00'0100

X-Peripheral Node

XP1IR

XP1IE

XP1INT

00'0104

X-Peripheral Node

XP2IR

XP2IE

XP2INT

00'0108

PLL Unlock

XP3IR

XP3IE

XP3INT

00'010C

Source of Interrupt or
PEC Service Request

Request
Flag

Enable
Flag

Interrupt
Vector

Vector
Location

Trap
Number

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C167CR-16RM

The C167CR-16RM also provides an excellent mechanism to identify and to process exceptions or
error conditions that arise during run-time, so-called `Hardware Traps'. Hardware traps cause
immediate non-maskable system reaction which is similar to a standard interrupt service (branching
to a dedicated vector table location). The occurence of a hardware trap is additionally signified by
an individual bit in the trap flag register (TFR). Except when another higher prioritized trap service
is in progress, a hardware trap will interrupt any actual program execution. In turn, hardware trap
services can normally not be interrupted by standard or PEC interrupts.

The following table shows all of the possible exceptions or error conditions that can arise during run-
time:

Exception Condition

Trap
Flag

Trap
Vector

Vector
Location

Trap
Number

Trap
Priority

Reset Functions:

Hardware Reset
Software Reset
Watchdog Timer Overflow

RESET
RESET
RESET

00'0000

III
III
III

Class A Hardware Traps:

Non-Maskable Interrupt
Stack Overflow
Stack Underflow

NMI
STKOF
STKUF

NMITRAP
STOTRAP
STUTRAP

00'0008

00'0010

00'0018

II
II
II

Class B Hardware Traps:

Undefined Opcode
Protected Instruction
Fault
Illegal Word Operand
Access
Illegal Instruction Access
Illegal External Bus
Access

UNDOPC
PRTFLT

ILLOPA

ILLINA
ILLBUS

BTRAP
BTRAP

BTRAP

BTRAP
BTRAP

00'0028

I
I

Reserved

[2C

] [0B

]

Software Traps

TRAP Instruction

Any
[00'0000

00'01FC

]

in steps
of 4

Any
[00

]

Current
CPU
Priority

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C167CR-16RM

Capture/Compare (CAPCOM) Units

The CAPCOM units support generation and control of timing sequences on up to 32 channels with
a maximum resolution of 400 ns (at 20-MHz system clock). The CAPCOM units are typically used
to handle high speed I/O tasks such as pulse and waveform generation, pulse width modulation
(PMW), Digital to Analog (D/A) conversion, software timing, or time recording relative to external
events.

Four 16-bit timers (T0/T1, T7/T8) with reload registers provide two independent time bases for the
capture/compare register array.

The input clock for the timers is programmable to several prescaled values of the internal system
clock, or may be derived from an overflow/underflow of timer T6 in module GPT2. This provides a
wide range of variation for the timer period and resolution and allows precise adjustments to the
application specific requirements. In addition, external count inputs for CAPCOM timers T0 and T7
allow event scheduling for the capture/compare registers relative to external events.

Both of the two capture/compare register arrays contain 16 dual purpose capture/compare
registers, each of which may be individually allocated to either CAPCOM timer T0 or T1 (T7 or T8,
respectively), and programmed for capture or compare function. Each register has one port pin
associated with it which serves as an input pin for triggering the capture function, or as an output pin
(except for CC24...CC27) to indicate the occurence of a compare event.

When a capture/compare register has been selected for capture mode, the current contents of the
allocated timer will be latched (`capture'd) into the capture/compare register in response to an
external event at the port pin which is associated with this register. In addition, a specific interrupt
request for this capture/compare register is generated. Either a positive, a negative, or both a
positive and a negative external signal transition at the pin can be selected as the triggering event.
The contents of all registers which have been selected for one of the five compare modes are
continuously compared with the contents of the allocated timers. When a match occurs between the
timer value and the value in a capture/compare register, specific actions will be taken based on the
selected compare mode.

Compare Modes

Function

Mode 0

Interrupt-only compare mode;
several compare interrupts per timer period are possible

Mode 1

Pin toggles on each compare match;
several compare events per timer period are possible

Mode 2

Interrupt-only compare mode;
only one compare interrupt per timer period is generated

Mode 3

Pin set `1' on match; pin reset `0' on compare time overflow;
only one compare event per timer period is generated

Double
Register Mode

Two registers operate on one pin; pin toggles on each compare match;
several compare events per timer period are possible.

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C167CR-16RM

Figure 5
CAPCOM Unit Block Diagram

*) 12 outputs on CAPCOM2

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C167CR-16RM

PWM Module

The Pulse Width Modulation Module can generate up to four PWM output signals using edge-
aligned or center-aligned PWM. In addition the PWM module can generate PWM burst signals and
single shot outputs. The frequency range of the PWM signals covers 4.8 Hz to 1 MHz (referred to
a CPU clock of 20 MHz), depending on the resolution of the PWM output signal. The level of the
output signals is selectable and the PWM module can generate interrupt requests.

General Purpose Timer (GPT) Unit

The GPT unit represents a very flexible multifunctional timer/counter structure which may be used
for many different time related tasks such as event timing and counting, pulse width and duty cycle
measurements, pulse generation, or pulse multiplication.

The GPT unit incorporates five 16-bit timers which are organized in two separate modules, GPT1
and GPT2. Each timer in each module may operate independently in a number of different modes,
or may be concatenated with another timer of the same module.

Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for one of four
basic modes of operation, which are Timer, Gated Timer, Counter, and Incremental Interface Mode.
In Timer Mode, the input clock for a timer is derived from the CPU clock, divided by a programmable
prescaler, while Counter Mode allows a timer to be clocked in reference to external events.
Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the operation of
a timer is controlled by the `gate' level on an external input pin. For these purposes, each timer has
one associated port pin (TxIN) which serves as gate or clock input. The maximum resolution of the
timers in module GPT1 is 400 ns (@ 20-MHz CPU clock).

The count direction (up/down) for each timer is programmable by software or may additionally be
altered dynamically by an external signal on a port pin (TxEUD) to facilitate eg. position tracking.

In Incremental Interface Mode the GPT1 timers (T2, T3, T4) can be directly connected to the
incremental position sensor signals A and B via their respective inputs TxIN and TxEUD. Direction
and count signals are internally derived from these two input signals, so the contents of the
respective timer Tx corresponds to the sensor position. The third position sensor signal TOP0 can
be connected to an interrupt input.

Timers T3 and T4 have output toggle latches (TxOTL) which change their state on each timer over-
flow/underflow. The state of these latches may be output on port pins (TxOUT) eg. for time out
monitoring of external hardware components, or may be used internally to clock timers T2 and T4
for measuring long time periods with high resolution.

In addition to their basic operating modes, timers T2 and T4 may be configured as reload or capture
registers for timer T3. When used as capture or reload registers, timers T2 and T4 are stopped. The
contents of timer T3 is captured into T2 or T4 in response to a signal at their associated input pins
(TxIN). Timer T3 is reloaded with the contents of T2 or T4 triggered either by an external signal or
by a selectable state transition of its toggle latch T3OTL. When both T2 and T4 are configured to
alternately reload T3 on opposite state transitions of T3OTL with the low and high times of a PWM
signal, this signal can be constantly generated without software intervention.

With its maximum resolution of 200 ns (@ 20 MHz), the GPT2 module provides precise event
control and time measurement. It includes two timers (T5, T6) and a capture/reload register

20Dec96@09:25h Intermediate Version

Semiconductor Group

C167CR-16RM

(CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock via
a programmable prescaler or with external signals. The count direction (up/down) for each timer is
programmable by software or may additionally be altered dynamically by an external signal on a
port pin (TxEUD). Concatenation of the timers is supported via the output toggle latch (T6OTL) of
timer T6, which changes its state on each timer overflow/underflow.

The state of this latch may be used to clock timer T5, and/or it may be output on a port pin (T6OUT).
The overflows/underflows of timer T6 can additionally be used to clock the CAPCOM timers T0 or
T1, and to cause a reload from the CAPREL register. The CAPREL register may capture the
contents of timer T5 based on an external signal transition on the corresponding port pin (CAPIN),
and timer T5 may optionally be cleared after the capture procedure. This allows absolute time
differences to be measured or pulse multiplication to be performed without software overhead.

The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of GPT1 timer
T3's inputs T3IN and/or T3EUD. This is especially advantageous when T3 operates in Incremental
Interface Mode.

Figure 6
Block Diagram of GPT1

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C167CR-16RM

Figure 7
Block Diagram of GPT2

Watchdog Timer

The Watchdog Timer represents one of the fail-safe mechanisms which have been implemented to
prevent the controller from malfunctioning for longer periods of time.

The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time
interval until the EINIT (end of initialization) instruction has been executed. Thus, the chip's start-up
procedure is always monitored. The software has to be designed to service the Watchdog Timer
before it overflows. If, due to hardware or software related failures, the software fails to do so, the
Watchdog Timer overflows and generates an internal hardware reset and pulls the RSTOUT pin low
in order to allow external hardware components to be reset.

The Watchdog Timer is a 16-bit timer, clocked with the system clock divided either by 2 or by 128.
The high byte of the Watchdog Timer register can be set to a prespecified reload value (stored in
WDTREL) in order to allow further variation of the monitored time interval. Each time it is serviced
by the application software, the high byte of the Watchdog Timer is reloaded. Thus, time intervals
between 25

s and 420 ms can be monitored (@ 20 MHz). The default Watchdog Timer interval

after reset is 6.55 ms (@ 20 MHz).

20Dec96@09:25h Intermediate Version

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C167CR-16RM

A/D Converter

For analog signal measurement, a 10-bit A/D converter with 16 multiplexed input channels and a
sample and hold circuit has been integrated on-chip. It uses the method of successive
approximation. The sample time (for loading the capacitors) and the conversion time is
programmable and can so be adjusted to the external circuitry.

Overrun error detection/protection is provided for the conversion result register (ADDAT): either an
interrupt request will be generated when the result of a previous conversion has not been read from
the result register at the time the next conversion is complete, or the next conversion is suspended
in such a case until the previous result has been read.

For applications which require less than 16 analog input channels, the remaining channel inputs can
be used as digital input port pins.

The A/D converter of the C167CR-16RM supports four different conversion modes. In the standard
Single Channel conversion mode, the analog level on a specified channel is sampled once and
converted to a digital result. In the Single Channel Continuous mode, the analog level on a specified
channel is repeatedly sampled and converted without software intervention. In the Auto Scan mode,
the analog levels on a prespecified number of channels are sequentially sampled and converted. In
the Auto Scan Continuous mode, the number of prespecified channels is repeatedly sampled and
converted. In addition, the conversion of a specific channel can be inserted (injected) into a running
sequence without disturbing this sequence. This is called Channel Injection Mode.

The Peripheral Event Controller (PEC) may be used to automatically store the conversion results
into a table in memory for later evaluation, without requiring the overhead of entering and exiting
interrupt routines for each data transfer.

After each reset and also during normal operation the ADC automatically performs calibration
cycles. This automatic self-calibration constantly adjusts the converter to changing operating
conditions (eg. temperature) and compensates process variations.

These calibration cycles are part of the conversion cycle, so they do not affect the normal operation
of the A/D converter.

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C167CR-16RM

Serial Channels

Serial communication with other microcontrollers, processors, terminals or external peripheral
components is provided by two serial interfaces with different functionality, an Asynchronous/
Synchronous Serial Channel (ASC0) and a High-Speed Synchronous Serial Channel (SSC).

The ASC0 is upward compatible with the serial ports of the Siemens 8-bit microcontroller families
and supports full-duplex asynchronous communication at up to 625 KBaud and half-duplex
synchronous communication at up to 2.5 MBaud @ 20 MHz CPU clock.
A dedicated baud rate generator allows to set up all standard baud rates without oscillator tuning.
For transmission, reception and error handling 4 separate interrupt vectors are provided. In
asynchronous mode, 8- or 9-bit data frames are transmitted or received, preceded by a start bit and
terminated by one or two stop bits. For multiprocessor communication, a mechanism to distinguish
address from data bytes has been included (8-bit data plus wake up bit mode).
In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a shift clock
which is generated by the ASC0. The ASC0 always shifts the LSB first. A loop back option is
available for testing purposes.
A number of optional hardware error detection capabilities has been included to increase the
reliability of data transfers. A parity bit can automatically be generated on transmission or be
checked on reception. Framing error detection allows to recognize data frames with missing stop
bits. An overrun error will be generated, if the last character received has not been read out of the
receive buffer register at the time the reception of a new character is complete.

The SSC supports full-duplex synchronous communication at up to 5 Mbaud @ 20 MHz CPU clock.
It may be configured so it interfaces with serially linked peripheral components. A dedicated baud
rate generator allows to set up all standard baud rates without oscillator tuning. For transmission,
reception and error handling 3 separate interrupt vectors are provided.
The SSC transmits or receives characters of 2...16 bits length synchronously to a shift clock which
can be generated by the SSC (master mode) or by an external master (slave mode). The SSC can
start shifting with the LSB or with the MSB and allows the selection of shifting and latching clock
edges as well as the clock polarity.
A number of optional hardware error detection capabilities has been included to increase the
reliability of data transfers. Transmit and receive error supervise the correct handling of the data
buffer. Phase and baudrate error detect incorrect serial data.

20Dec96@09:25h Intermediate Version

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C167CR-16RM

CAN-Module

The integrated CAN-Module handles the completely autonomous transmission and reception of
CAN frames in accordance with the CAN specification V2.0 part B (active), ie. the on-chip CAN-
Module can receive and transmit standard frames with 11-bit identifiers as well as extended frames
with 29-bit identifiers.

The module provides Full CAN functionality on up to 15 message objects. Message object 15 may
be configured for Basic CAN functionality. Both modes provide separate masks for acceptance
filtering which allows to accept a number of identifiers in Full CAN mode and also allows to disregard
a number of identifiers in Basic CAN mode. All message objects can be updated independent from
the other objects and are equipped for the maximum message length of 8 bytes.

The bit timing is derived from the XCLK and is programmable up to a data rate of 1 MBaud. The
CAN-Module uses two pins of Port 4 to interface to a bus transceiver.

Note: When the CAN interface is to be used the segment address output on Port 4 must be limited

to 4 bits, ie. A19...A16. This is necessary to enable the alternate function of the CAN
interface pins.

Parallel Ports

The C167CR-16RM provides up to 111 I/O lines which are organized into eight input/output ports
and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-
wise) programmable as inputs or outputs via direction registers. The I/O ports are true bidirectional
ports which are switched to high impedance state when configured as inputs. The output drivers of
five I/O ports can be configured (pin by pin) for push/pull operation or open-drain operation via
control registers. During the internal reset, all port pins are configured as inputs.

The input threshold of Port 2, Port 3, Port 7 and Port 8 is selectable (TTL or CMOS like), where the
special CMOS like input threshold reduces noise sensitivity due to the input hysteresis. The input
threshold may be selected individually for each byte of the respective ports.

All port lines have programmable alternate input or output functions associated with them.
PORT0 and PORT1 may be used as address and data lines when accessing external memory,
while Port 4 outputs the additional segment address bits A23/19/17...A16 in systems where
segmentation is enabled to access more than 64 KBytes of memory.

Port 2, Port 8 and Port 7 are associated with the capture inputs or compare outputs of the CAPCOM
units and/or with the outputs of the PWM module.
Port 6 provides optional bus arbitration signals (BREQ, HLDA, HOLD) and chip select signals.
Port 3 includes alternate functions of timers, serial interfaces, the optional bus control signal BHE
and the system clock output (CLKOUT).
Port 5 is used for the analog input channels to the A/D converter or timer control signals.

All port lines that are not used for these alternate functions may be used as general purpose IO
lines.

20Dec96@09:25h Intermediate Version

Semiconductor Group

C167CR-16RM

Instruction Set Summary

The table below lists the instructions of the C167CR-16RM in a condensed way.
The various addressing modes that can be used with a specific instruction, the operation of the
instructions, parameters for conditional execution of instructions, and the opcodes for each
instruction can be found in the "C16x Family Instruction Set Manual".

This document also provides a detailled description of each instruction.

Instruction Set Summary

Mnemonic

Description

Bytes

ADD(B)

Add word (byte) operands

2 / 4

ADDC(B)

Add word (byte) operands with Carry

2 / 4

SUB(B)

Subtract word (byte) operands

2 / 4

SUBC(B)

Subtract word (byte) operands with Carry

2 / 4

MUL(U)

(Un)Signed multiply direct GPR by direct GPR (16-16-bit)

DIV(U)

(Un)Signed divide register MDL by direct GPR (16-/16-bit)

DIVL(U)

(Un)Signed long divide reg. MD by direct GPR (32-/16-bit)

CPL(B)

Complement direct word (byte) GPR

NEG(B)

Negate direct word (byte) GPR

AND(B)

Bitwise AND, (word/byte operands)

2 / 4

OR(B)

Bitwise OR, (word/byte operands)

2 / 4

XOR(B)

Bitwise XOR, (word/byte operands)

2 / 4

BCLR

Clear direct bit

BSET

Set direct bit

BMOV(N)

Move (negated) direct bit to direct bit

BAND, BOR, BXOR

AND/OR/XOR direct bit with direct bit

BCMP

Compare direct bit to direct bit

BFLDH/L

Bitwise modify masked high/low byte of bit-addressable
direct word memory with immediate data

CMP(B)

Compare word (byte) operands

2 / 4

CMPD1/2

Compare word data to GPR and decrement GPR by 1/2

2 / 4

CMPI1/2

Compare word data to GPR and increment GPR by 1/2

2 / 4

PRIOR

Determine number of shift cycles to normalize direct
word GPR and store result in direct word GPR

SHL / SHR

Shift left/right direct word GPR

ROL / ROR

Rotate left/right direct word GPR

ASHR

Arithmetic (sign bit) shift right direct word GPR

20Dec96@09:25h Intermediate Version

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C167CR-16RM

MOV(B)

Move word (byte) data

2 / 4

MOVBS

Move byte operand to word operand with sign extension

2 / 4

MOVBZ

Move byte operand to word operand. with zero extension

2 / 4

JMPA, JMPI, JMPR

Jump absolute/indirect/relative if condition is met

JMPS

Jump absolute to a code segment

J(N)B

Jump relative if direct bit is (not) set

JBC

Jump relative and clear bit if direct bit is set

JNBS

Jump relative and set bit if direct bit is not set

CALLA, CALLI, CALLR

Call absolute/indirect/relative subroutine if condition is met

CALLS

Call absolute subroutine in any code segment

PCALL

Push direct word register onto system stack and call
absolute subroutine

TRAP

Call interrupt service routine via immediate trap number

PUSH, POP

Push/pop direct word register onto/from system stack

SCXT

Push direct word register onto system stack und update
register with word operand

RET

Return from intra-segment subroutine

RETS

Return from inter-segment subroutine

RETP

Return from intra-segment subroutine and pop direct
word register from system stack

RETI

Return from interrupt service subroutine

SRST

Software Reset

IDLE

Enter Idle Mode

PWRDN

Enter Power Down Mode
(supposes NMI-pin being low)

SRVWDT

Service Watchdog Timer

DISWDT

Disable Watchdog Timer

EINIT

Signify End-of-Initialization on RSTOUT-pin

ATOMIC

Begin ATOMIC sequence

EXTR

Begin EXTended Register sequence

EXTP(R)

Begin EXTended Page (and Register) sequence

2 / 4

EXTS(R)

Begin EXTended Segment (and Register) sequence

2 / 4

NOP

Null operation

Instruction Set Summary (cont'd)

Mnemonic

Description

Bytes

20Dec96@09:25h Intermediate Version

Semiconductor Group

C167CR-16RM

Special Function Registers Overview

The following table lists all SFRs which are implemented in the C167CR-16RM in alphabetical
order.
Bit-addressable SFRs are marked with the letter "b" in column "Name". SFRs within the Extended
SFR-Space (ESFRs) are marked with the letter "E" in column "Physical Address".

An SFR can be specified via its individual mnemonic name. Depending on the selected addressing
mode, an SFR can be accessed via its physical address (using the Data Page Pointers), or via its
short 8-bit address (without using the Data Page Pointers).

Special Function Registers Overview

Name

Physical
Address

8-Bit
Address

Description

Reset
Value

ADCIC

b FF98

A/D Converter End of Conversion Interrupt
Control Register

0000

ADCON

b FFA0

A/D Converter Control Register

0000

ADDAT

FEA0

A/D Converter Result Register

0000

ADDAT2

F0A0

E 50

A/D Converter 2 Result Register

0000

ADDRSEL1

FE18

Address Select Register 1

0000

ADDRSEL2

FE1A

Address Select Register 2

0000

ADDRSEL3

FE1C

Address Select Register 3

0000

ADDRSEL4

FE1E

Address Select Register 4

0000

ADEIC

b FF9A

A/D Converter Overrun Error Interrupt Control
Register

0000

BUSCON0 b FF0C

Bus Configuration Register 0

0XX0

BUSCON1 b FF14

Bus Configuration Register 1

0000

BUSCON2 b FF16

Bus Configuration Register 2

0000

BUSCON3 b FF18

Bus Configuration Register 3

0000

BUSCON4 b FF1A

Bus Configuration Register 4

0000

CAPREL

FE4A

GPT2 Capture/Reload Register

0000

CC0

FE80

CAPCOM Register 0

0000

CC0IC

b FF78

CAPCOM Register 0 Interrupt Control Register

0000

CC1

FE82

CAPCOM Register 1

0000

CC1IC

b FF7A

CAPCOM Register 1 Interrupt Control Register

0000

CC2

FE84

CAPCOM Register 2

0000

CC2IC

b FF7C

CAPCOM Register 2 Interrupt Control Register

0000

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C167CR-16RM

CC3

FE86

CAPCOM Register 3

0000

CC3IC

b FF7E

CAPCOM Register 3 Interrupt Control Register

0000

CC4

FE88

CAPCOM Register 4

0000

CC4IC

b FF80

CAPCOM Register 4 Interrupt Control Register

0000

CC5

FE8A

CAPCOM Register 5

0000

CC5IC

b FF82

CAPCOM Register 5 Interrupt Control Register

0000

CC6

FE8C

CAPCOM Register 6

0000

CC6IC

b FF84

CAPCOM Register 6 Interrupt Control Register

0000

CC7

FE8E

CAPCOM Register 7

0000

CC7IC

b FF86

CAPCOM Register 7 Interrupt Control Register

0000

CC8

FE90

CAPCOM Register 8

0000

CC8IC

b FF88

CAPCOM Register 8 Interrupt Control Register

0000

CC9

FE92

CAPCOM Register 9

0000

CC9IC

b FF8A

CAPCOM Register 9 Interrupt Control Register

0000

CC10

FE94

CAPCOM Register 10

0000

CC10IC

b FF8C

CAPCOM Register 10 Interrupt Control Register

0000

CC11

FE96

CAPCOM Register 11

0000

CC11IC

b FF8E

CAPCOM Register 11 Interrupt Control Register

0000

CC12

FE98

CAPCOM Register 12

0000

CC12IC

b FF90

CAPCOM Register 12 Interrupt Control Register

0000

CC13

FE9A

CAPCOM Register 13

0000

CC13IC

b FF92

CAPCOM Register 13 Interrupt Control Register

0000

CC14

FE9C

CAPCOM Register 14

0000

CC14IC

b FF94

CAPCOM Register 14 Interrupt Control Register

0000

CC15

FE9E

CAPCOM Register 15

0000

CC15IC

b FF96

CAPCOM Register 15 Interrupt Control Register

0000

CC16

FE60

CAPCOM Register 16

0000

CC16IC

b F160

E B0

CAPCOM Register 16 Interrupt Control Register

0000

CC17

FE62

CAPCOM Register 17

0000

Special Function Registers Overview (cont'd)

Name

Physical
Address

8-Bit
Address

Description

Reset
Value

20Dec96@09:25h Intermediate Version

Semiconductor Group

C167CR-16RM

CC17IC

b F162

E B1

CAPCOM Register 17 Interrupt Control Register

0000

CC18

FE64

CAPCOM Register 18

0000

CC18IC

b F164

E B2

CAPCOM Register 18 Interrupt Control Register

0000

CC19

FE66

CAPCOM Register 19

0000

CC19IC

b F166

E B3

CAPCOM Register 19 Interrupt Control Register

0000

CC20

FE68

CAPCOM Register 20

0000

CC20IC

b F168

E B4

CAPCOM Register 20 Interrupt Control Register

0000

CC21

FE6A

CAPCOM Register 21

0000

CC21IC

b F16A

E B5

CAPCOM Register 21 Interrupt Control Register

0000

CC22

FE6C

CAPCOM Register 22

0000

CC22IC

b F16C

E B6

CAPCOM Register 22 Interrupt Control Register

0000

CC23

FE6E

CAPCOM Register 23

0000

CC23IC

b F16E

E B7

CAPCOM Register 23 Interrupt Control Register

0000

CC24

FE70

CAPCOM Register 24

0000

CC24IC

b F170

E B8

CAPCOM Register 24 Interrupt Control Register

0000

CC25

FE72

CAPCOM Register 25

0000

CC25IC

b F172

E B9

CAPCOM Register 25 Interrupt Control Register

0000

CC26

FE74

CAPCOM Register 26

0000

CC26IC

b F174

E BA

CAPCOM Register 26 Interrupt Control Register

0000

CC27

FE76

CAPCOM Register 27

0000

CC27IC

b F176

E BB

CAPCOM Register 27 Interrupt Control Register

0000

CC28

FE78

CAPCOM Register 28

0000

CC28IC

b F178

E BC

CAPCOM Register 28 Interrupt Control Register

0000

CC29

FE7A

CAPCOM Register 29

0000

CC29IC

b F184

E C2

CAPCOM Register 29 Interrupt Control Register

0000

CC30

FE7C

CAPCOM Register 30

0000

CC30IC

b F18C

E C6

CAPCOM Register 30 Interrupt Control Register

0000

CC31

FE7E

CAPCOM Register 31

0000

CC31IC

b F194

E CA

CAPCOM Register 31 Interrupt Control Register

0000

Special Function Registers Overview (cont'd)

Name

Physical
Address

8-Bit
Address

Description

Reset
Value

20Dec96@09:25h Intermediate Version

Semiconductor Group

C167CR-16RM

CCM0

b FF52

CAPCOM Mode Control Register 0

0000

CCM1

b FF54

CAPCOM Mode Control Register 1

0000

CCM2

b FF56

CAPCOM Mode Control Register 2

0000

CCM3

b FF58

CAPCOM Mode Control Register 3

0000

CCM4

b FF22

CAPCOM Mode Control Register 4

0000

CCM5

b FF24

CAPCOM Mode Control Register 5

0000

CCM6

b FF26

CAPCOM Mode Control Register 6

0000

CCM7

b FF28

CAPCOM Mode Control Register 7

0000

FE10

CPU Context Pointer Register

FC00

CRIC

b FF6A

GPT2 CAPREL Interrupt Control Register

0000

CSP

FE08

CPU Code Segment Pointer Register (read only)

0000

DP0L

b F100

E 80

P0L Direction Control Register

DP0H

b F102

E 81

P0H Direction Control Register

DP1L

b F104

E 82

P1L Direction Control Register

DP1H

b F106

E 83

P1H Direction Control Register

DP2

b FFC2

Port 2 Direction Control Register

0000

DP3

b FFC6

Port 3 Direction Control Register

0000

DP4

b FFCA

Port 4 Direction Control Register

DP6

b FFCE

Port 6 Direction Control Register

DP7

b FFD2

Port 7 Direction Control Register

DP8

b FFD6

Port 8 Direction Control Register

DPP0

FE00

CPU Data Page Pointer 0 Register (10 bits)

0000

DPP1

FE02

CPU Data Page Pointer 1 Register (10 bits)

0001

DPP2

FE04

CPU Data Page Pointer 2 Register (10 bits)

0002

DPP3

FE06

CPU Data Page Pointer 3 Register (10 bits)

0003

EXICON

b F1C0

E E0

External Interrupt Control Register

0000

MDC

b FF0E

CPU Multiply Divide Control Register

0000

MDH

FE0C

CPU Multiply Divide Register High Word

0000

MDL

FE0E

CPU Multiply Divide Register Low Word

0000

Special Function Registers Overview (cont'd)

Name

Physical
Address

8-Bit
Address

Description

Reset
Value

20Dec96@09:25h Intermediate Version

Semiconductor Group

C167CR-16RM

ODP2

b F1C2

E E1

Port 2 Open Drain Control Register

0000

ODP3

b F1C6

E E3

Port 3 Open Drain Control Register

0000

ODP6

b F1CE

E E7

Port 6 Open Drain Control Register

ODP7

b F1D2

E E9

Port 7 Open Drain Control Register

ODP8

b F1D6

E EB

Port 8 Open Drain Control Register

ONES

FF1E

Constant Value 1's Register (read only)

FFFF

P0L

b FF00

Port 0 Low Register (Lower half of PORT0)

P0H

b FF02

Port 0 High Register (Upper half of PORT0)

P1L

b FF04

Port 1 Low Register (Lower half of PORT1)

P1H

b FF06

Port 1 High Register (Upper half of PORT1)

b FFC0

Port 2 Register

0000

b FFC4

Port 3 Register

0000

b FFC8

Port 4 Register (8 bits)

b FFA2

Port 5 Register (read only)

XXXX

b FFCC

Port 6 Register (8 bits)

b FFD0

Port 7 Register (8 bits)

b FFD4

Port 8 Register (8 bits)

PECC0

FEC0

PEC Channel 0 Control Register

0000

PECC1

FEC2

PEC Channel 1 Control Register

0000

PECC2

FEC4

PEC Channel 2 Control Register

0000

PECC3

FEC6

PEC Channel 3 Control Register

0000

PECC4

FEC8

PEC Channel 4 Control Register

0000

PECC5

FECA

PEC Channel 5 Control Register

0000

PECC6

FECC

PEC Channel 6 Control Register

0000

PECC7

FECE

PEC Channel 7 Control Register

0000

PICON

F1C4

E E2

Port Input Threshold Control Register

0000

PP0

F038

E 1C

PWM Module Period Register 0

0000

PP1

F03A

E 1D

PWM Module Period Register 1

0000

PP2

F03C

E 1E

PWM Module Period Register 2

0000

Special Function Registers Overview (cont'd)

Name

Physical
Address

8-Bit
Address

Description

Reset
Value

20Dec96@09:25h Intermediate Version

Semiconductor Group

C167CR-16RM

PP3

F03E

E 1F

PWM Module Period Register 3

0000

PSW

b FF10

CPU Program Status Word

0000

PT0

F030

E 18

PWM Module Up/Down Counter 0

0000

PT1

F032

E 19

PWM Module Up/Down Counter 1

0000

PT2

F034

E 1A

PWM Module Up/Down Counter 2

0000

PT3

F036

E 1B

PWM Module Up/Down Counter 3

0000

PW0

FE30

PWM Module Pulse Width Register 0

0000

PW1

FE32

PWM Module Pulse Width Register 1

0000

PW2

FE34

PWM Module Pulse Width Register 2

0000

PW3

FE36

PWM Module Pulse Width Register 3

0000

PWMCON0 b FF30

PWM Module Control Register 0

0000

PWMCON1 b FF32

PWM Module Control Register 1

0000

PWMIC

b F17E

E BF

PWM Module Interrupt Control Register

0000

RP0H

b F108

E 84

System Startup Configuration Register (Rd. only)

S0BG

FEB4

Serial Channel 0 Baud Rate Generator Reload
Register

0000

S0CON

b FFB0

Serial Channel 0 Control Register

0000

S0EIC

b FF70

Serial Channel 0 Error Interrupt Control Register

0000

S0RBUF

FEB2

Serial Channel 0 Receive Buffer Register
(read only)

S0RIC

b FF6E

Serial Channel 0 Receive Interrupt Control
Register

0000

S0TBIC

b F19C

E CE

Serial Channel 0 Transmit Buffer Interrupt Control
Register

0000

S0TBUF

FEB0

Serial Channel 0 Transmit Buffer Register
(write only)

S0TIC

b FF6C

Serial Channel 0 Transmit Interrupt Control
Register

0000

FE12

CPU System Stack Pointer Register

FC00

SSCBR

F0B4

E 5A

SSC Baudrate Register

0000

SSCCON

b FFB2

SSC Control Register

0000

Special Function Registers Overview (cont'd)

Name

Physical
Address

8-Bit
Address

Description

Reset
Value

20Dec96@09:25h Intermediate Version

Semiconductor Group

C167CR-16RM

SSCEIC

b FF76

SSC Error Interrupt Control Register

0000

SSCRB

F0B2

E 59

SSC Receive Buffer (read only)

XXXX

SSCRIC

b FF74

SSC Receive Interrupt Control Register

0000

SSCTB

F0B0

E 58

SSC Transmit Buffer (write only)

0000

SSCTIC

b FF72

SSC Transmit Interrupt Control Register

0000

STKOV

FE14

CPU Stack Overflow Pointer Register

FA00

STKUN

FE16

CPU Stack Underflow Pointer Register

FC00

SYSCON

b FF12

CPU System Configuration Register

0xx0

FE50

CAPCOM Timer 0 Register

0000

T01CON

b FF50

CAPCOM Timer 0 and Timer 1 Control Register

0000

T0IC

b FF9C

CAPCOM Timer 0 Interrupt Control Register

0000

T0REL

FE54

CAPCOM Timer 0 Reload Register

0000

FE52

CAPCOM Timer 1 Register

0000

T1IC

b FF9E

CAPCOM Timer 1 Interrupt Control Register

0000

T1REL

FE56

CAPCOM Timer 1 Reload Register

0000

FE40

GPT1 Timer 2 Register

0000

T2CON

b FF40

GPT1 Timer 2 Control Register

0000

T2IC

b FF60

GPT1 Timer 2 Interrupt Control Register

0000

FE42

GPT1 Timer 3 Register

0000

T3CON

b FF42

GPT1 Timer 3 Control Register

0000

T3IC

b FF62

GPT1 Timer 3 Interrupt Control Register

0000

FE44

GPT1 Timer 4 Register

0000

T4CON

b FF44

GPT1 Timer 4 Control Register

0000

T4IC

b FF64

GPT1 Timer 4 Interrupt Control Register

0000

FE46

GPT2 Timer 5 Register

0000

T5CON

b FF46

GPT2 Timer 5 Control Register

0000

T5IC

b FF66

GPT2 Timer 5 Interrupt Control Register

0000

FE48

GPT2 Timer 6 Register

0000

T6CON

b FF48

GPT2 Timer 6 Control Register

0000

Special Function Registers Overview (cont'd)

Name

Physical
Address

8-Bit
Address

Description

Reset
Value

20Dec96@09:25h Intermediate Version

Semiconductor Group

C167CR-16RM

The system configuration is selected during reset.

Bit WDTR indicates a watchdog timer triggered reset.

Note: The Interrupt Control Registers XPnIC are prepared to control interrupt requests from

integrated X-Bus peripherals. Nodes, where no X-Peripherals are connected, may be used
to generate software controlled interrupt requests by setting the respective XPnIR bit.

T6IC

b FF68

GPT2 Timer 6 Interrupt Control Register

0000

F050

E 28

CAPCOM Timer 7 Register

0000

T78CON

b FF20

CAPCOM Timer 7 and 8 Control Register

0000

T7IC

b F17A

E BE

CAPCOM Timer 7 Interrupt Control Register

0000

T7REL

F054

E 2A

CAPCOM Timer 7 Reload Register

0000

F052

E 29

CAPCOM Timer 8 Register

0000

T8IC

b F17C

E BF

CAPCOM Timer 8 Interrupt Control Register

0000

T8REL

F056

E 2B

CAPCOM Timer 8 Reload Register

0000

TFR

b FFAC

Trap Flag Register

0000

WDT

FEAE

Watchdog Timer Register (read only)

0000

WDTCON

FFAE

Watchdog Timer Control Register

000X

XP0IC

b F186

E C3

CAN Module Interrupt Control Register

0000

XP1IC

b F18E

E C7

X-Peripheral 1 Interrupt Control Register

0000

XP2IC

b F196

E CB

X-Peripheral 2 Interrupt Control Register

0000

XP3IC

b F19E

E CF

PLL Interrupt Control Register

0000

ZEROS

b FF1C

Constant Value 0's Register (read only)

0000

Special Function Registers Overview (cont'd)

Name

Physical
Address

8-Bit
Address

Description

Reset
Value

20Dec96@09:25h Intermediate Version

Semiconductor Group

C167CR-16RM

Absolute Maximum Ratings

Ambient temperature under bias (

SAB-C167CR-16RM ........................................................................................................0 to +70 °C
SAF-C167CR-16RM .................................................................................................... 40 to +85 °C
SAK-C167CR-16RM .................................................................................................. 40 to +125 °C
Storage temperature (

)......................................................................................... 65 to +150 °C

Voltage on

pins with respect to ground (

) ....................................................... 0.5 to +6.5 V

Voltage on any pin with respect to ground (

) ...................................................0.5 to

+0.5 V

Input current on any pin during overload condition .................................................... 10 to +10 mA
Absolute sum of all input currents during overload condition ..............................................|100 mA|
Power dissipation..................................................................................................................... 1.5 W

Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent

damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability. During overload conditions (

) the

voltage on pins with respect to ground (

) must not exceed the values defined by the

Absolute Maximum Ratings.

Parameter Interpretation

The parameters listed in the following partly represent the characteristics of the C167CR-16RM and
partly its demands on the system. To aid in interpreting the parameters right, when evaluating them
for a design, they are marked in column "Symbol":

CC (Controller Characteristics):
The logic of the C167CR-16RM will provide signals with the respective timing characteristics.

SR (System Requirement):
The external system must provide signals with the respective timing characteristics to the C167CR-
16RM.

20Dec96@09:25h Intermediate Version

Semiconductor Group

C167CR-16RM

DC Characteristics

= 5 V

10 %;

= 0 V;

CPU

= 20 MHz

= 0 to +70 °C

for SAB-C167CR-16RM

= -40 to +85 °C

for SAF-C167CR-16RM

= -40 to +125 °C

for SAK-C167CR-16RM

Parameter

Symbol

Limit Values

Unit

Test Condition

min.

max.

Input low voltage
(TTL)

SR 0.5

0.2

0.1

Input low voltage
(Special Threshold)

ILS

SR 0.5

2.0

Input high voltage, all except
RSTIN and XTAL1 (TTL)

SR 0.2

+ 0.9

+ 0.5

Input high voltage RSTIN

IH1

SR 0.6

+ 0.5

Input high voltage XTAL1

IH2

SR 0.7

+ 0.5

Input high voltage
(Special Threshold)

IHS

SR 0.8

- 0.2

+ 0.5

Input Hysteresis
(Special Threshold)

HYS

400

Output low voltage
(PORT0, PORT1, Port 4, ALE, RD,
WR, BHE, CLKOUT, RSTOUT)

0.45

= 2.4 mA

Output low voltage
(all other outputs)

OL1

0.45

OL1

= 1.6 mA

Output high voltage
(PORT0, PORT1, Port 4, ALE, RD,
WR, BHE, CLKOUT, RSTOUT)

CC 0.9

2.4

= 500

= 2.4 mA

Output high voltage

(all other outputs)

OH1

CC 0.9

2.4

V
V

= 250

= 1.6 mA

Input leakage current (Port 5)

OZ1

200

0.45V <

Input leakage current (all other)

OZ2

500

0.45V <

Overload current

5) 8)

RSTIN pullup resistor

RST

CC 50

250

Read/Write inactive current

RWH

-40

OUT

= 2.4 V

Read/Write active current

RWL

-500

OUT

OLmax

ALE inactive current

ALEL

OUT

OLmax

ALE active current

ALEH

500

OUT

= 2.4 V

Port 6 inactive current

P6H

-40

OUT

= 2.4 V

20Dec96@09:25h Intermediate Version

Semiconductor Group

C167CR-16RM

Notes

This specification is not valid for outputs which are switched to open drain mode. In this case the respective
output will float and the voltage results from the external circuitry.

The maximum current may be drawn while the respective signal line remains inactive.

The minimum current must be drawn in order to drive the respective signal line active.

This specification is only valid during Reset, or during Hold- or Adapt-mode. Port 6 pins are only affected, if
they are used for CS output and the open drain function is not enabled.

Not 100% tested, guaranteed by design characterization.

The supply current is a function of the operating frequency. This dependency is illustrated in the figure below.
These parameters are tested at

CCmax

and 20 MHz CPU clock with all outputs disconnected and all inputs

This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to
0.1 V or at

0.1 V to

REF

= 0 V, all outputs (including pins configured as outputs) disconnected.

Overload conditions occur if the standard operatings conditions are exceeded, ie. the voltage on any pin
exceeds the specified range (ie.

> V

+0.5V or

< V

-0.5V). The absolute sum of input overload

currents on all port pins may not exceed 50 mA. The supply voltage must remain within the specified limits.

Port 6 active current

P6L

-500

OUT

OL1max

PORT0 configuration current

P0H

-10

IHmin

P0L

-100

ILmax

XTAL1 input current

0 V <

Pin capacitance

(digital inputs/outputs)

= 1 MHz

= 25 °C

Power supply current

20 +
5 * f

CPU

RSTIN =

IL2

CPU

in [MHz]

Idle mode supply current

20 +
2 * f

CPU

RSTIN =

IH1

CPU

in [MHz]

Power-down mode supply current

100

= 5.5 V

Parameter

Symbol

Limit Values

Unit

Test Condition

min.

max.

20Dec96@09:25h Intermediate Version

Semiconductor Group

C167CR-16RM

Figure 8
Supply/Idle Current as a Function of Operating Frequency

AAAA

I [m

]

CPU

[MHz]

150

100

CCtyp

IDmax

CCmax

IDtyp

AAAA

20Dec96@09:25h Intermediate Version

Semiconductor Group

C167CR-16RM

A/D Converter Characteristics

= 5 V

10 %;

= 0 V

= 0 to +70 °C

for SAB-C167CR-16RM

= -40 to +85 °C

for SAF-C167CR-16RM

= -40 to +125 °C

for SAK-C167CR-16RM

4.0 V

AREF

+0.1 V ;

-0.1 V

AGND

+0.2 V

Sample time and conversion time of the C167CR-16RM's ADC are programmable. The table below
should be used to calculate the above timings.

Parameter

Symbol

Limit Values

Unit

Test Condition

min.

max.

Analog input voltage range

AIN

AGND

AREF

Sample time

2) 4)

Conversion time

+ 4TCL

3) 4)

Total unadjusted error

TUE CC

LSB

Internal resistance of reference
voltage source

AREF

/ 165

- 0.25

in [ns]

Internal resistance of analog
source

ASRC

/ 330

- 0.25

in [ns]

ADC input capacitance

AIN

ADCON.15|14
(ADCTC)

Conversion clock

ADCON.13|12
(ADSTC)

Sample clock

TCL * 24

Reserved, do not use

* 2

TCL * 96

* 4

TCL * 48

* 8

20Dec96@09:25h Intermediate Version

Semiconductor Group

C167CR-16RM

Notes

AIN

may exceed

AGND

AREF

up to the absolute maximum ratings. However, the conversion result in these

cases will be X000

or X3FF

, respectively.

During the sample time the input capacitance

can be charged/discharged by the external source. The

internal resistance of the analog source must allow the capacitance to reach its final voltage level within

After the end of the sample time

, changes of the analog input voltage have no effect on the conversion result.

Values for the sample clock

depend on programming and can be taken from the table above.

This parameter includes the sample time

, the time for determining the digital result and the time to load the

result register with the conversion result.
Values for the conversion clock

depend on programming and can be taken from the table above.

This parameter depends on the ADC control logic. It is not a real maximum value, but rather a fixum.

TUE is tested at

AREF

=5.0V,

AGND

=0V,

=4.9V. It is guaranteed by design characterization for all other

voltages within the defined voltage range.
The specified TUE is guaranteed only if an overload condition (see

specification) occurs on maximum 2

not selected analog input pins and the absolute sum of input overload currents on all analog input pins does
not exceed 10 mA.
During the reset calibration sequence the maximum TUE may be

4 LSB.

During the conversion the ADC's capacitance must be repeatedly charged or discharged. The internal
resistance of the reference voltage source must allow the capacitance to reach its respective voltage level
within

. The maximum internal resistance results from the programmed conversion timing.

Not 100% tested, guaranteed by design characterization.

20Dec96@09:25h Intermediate Version

Semiconductor Group

C167CR-16RM

Testing Waveforms

Figure 9
Input Output Waveforms

Figure 10
Float Waveforms

AC inputs during testing are driven at 2.4 V for a logic `1' and 0.45 V for a logic `0'.
Timing measurements are made at

min for a logic `1' and

max for a logic `0'.

For timing purposes a port pin is no longer floating when a 100 mV change from load
voltage occurs, but begins to float when a 100 mV change from the loaded

level occurs

(

= 20 mA).

20Dec96@09:25h Intermediate Version

Semiconductor Group

C167CR-16RM

AC Characteristics
Definition of Internal Timing

The internal operation of the C167CR-16RM is controlled by the internal CPU clock f

CPU

. Both

edges of the CPU clock can trigger internal (eg. pipeline) or external (eg. bus cycles) operations.

The specification of the external timing (AC Characteristics) therefore depends on the time between
two consecutive edges of the CPU clock, called "TCL" (see figure below).

Figure 11
Generation Mechanisms for the CPU Clock

The CPU clock signal can be generated via different mechanisms. The duration of TCLs and their
variation (and also the derived external timing) depends on the used mechanism to generate f

CPU

This influence must be regarded when calculating the timings for the C167CR-16RM.

Direct Drive

When pin P0.15 (P0H.7) is low (`0') during reset the on-chip phase locked loop is disabled and the
CPU clock is directly driven from the internal oscillator with the input clock signal.
The frequency of f

CPU

directly follows the frequency of f

XTAL

so the high and low time of f

CPU

(ie. the

duration of an individual TCL) is defined by the duty cycle of the input clock f

XTAL

The timings listed below that refer to TCLs therefore must be calculated using the minimum TCL
that is possible under the respective circumstances. This minimum value can be calculated via the
following formula:

TCL

min

= 1/f

XTAL

* DC

min

(DC = duty cycle)

For two consecutive TCLs the deviation caused by the duty cycle of f

XTAL

is compensated so the

duration of 2TCL is always 1/f

XTAL

. The minimum value TCL

min

therefore has to be used only once

for timings that require an odd number of TCLs (1,3,...). Timings that require an even number of
TCLs (2,4,...) may use the formula 2TCL = 1/f

XTAL

Note: The address float timings in Multiplexed bus mode (t

and t

) use the maximum duration of

TCL (TCL

max

= 1/f

XTAL

* DC

max

) instead of TCL

min

TCL TCL

CPU

XTAL

CPU

XTAL

Phase Locked Loop Operation

Direct Clock Drive

20Dec96@09:25h Intermediate Version

Semiconductor Group

C167CR-16RM

Phase Locked Loop

When pin P0.15 (P0H.7) is high (`1') during reset the on-chip phase locked loop is enabled and
provides the CPU clock. The PLL multiplies the input frequency by 4 (ie. f

CPU

= f

XTAL

* 4). With every

fourth transition of f

XTAL

the PLL circuit synchronizes the CPU clock to the input clock. This

synchronization is done smoothely, ie. the CPU clock frequency does not change abruptly.

Due to this adaptation to the input clock the frequency of f

CPU

is constantly adjusted so it is locked

to f

XTAL

. The slight variation causes a jitter of f

CPU

which also effects the duration of individual TCLs.

The timings listed in the AC Characteristics that refer to TCLs therefore must be calculated using the
minimum TCL that is possible under the respective circumstances.

The actual minimum value for TCL depends on the jitter of the PLL. As the PLL is constantly
adjusting its output frequency so it corresponds to the applied input frequency (crystal or oscillator)
the relative deviation for periods of more than one TCL is lower than for one single TCL (see formula
and figure below).
For a period of

N * TCL the minimum value is computed using the corresponding deviation D

TCL

min

= TCL

NOM

* (1 - D

/ 100)

(4 -

N /15) [%],

where

N = number of consecutive TCLs

and 1

40.

So for a period of 3 TCLs (ie.

N = 3): D

= 4 -

3/15 = 3.8%,

and TCL

min

= TCL

NOM

* (1 - 3.8 / 100) = TCL

NOM

* 0.962 (24.1 nsec @ f

CPU

= 20 MHz).

This is especially important for bus cycles using waitstates and eg. for the operation of timers, serial
interfaces, etc. For all slower operations and longer periods (eg. pulse train generation or
measurement, lower baudrates, etc.) the deviation caused by the PLL jitter is neglectible.

Figure 12
Approximated Maximum PLL Jitter

Max.jitter [%]

This approximated formula is valid for
1

40 and 10MHz

CPU

20MHz.

20Dec96@09:25h Intermediate Version

Semiconductor Group

C167CR-16RM

AC Characteristics
External Clock Drive XTAL1

= 5 V

10 %;

= 0 V

= 0 to +70 °C

for SAB-C167CR-16RM

= -40 to +85 °C

for SAF-C167CR-16RM-

= -40 to +125 °C

for SAK-C167CR-16RM

For temperatures above

= +85 °C the minimum value for

and

is 25 ns.

The clock input signal must reach the defined levels

and

IH2

Figure 13
External Clock Drive XTAL1

Parameter

Symbol

Direct Drive 1:1

PLL 1:4

Unit

min.

max.

min.

max.

Oscillator period

OSC

1000

200

333

High time

Low time

Rise time

Fall time

20Dec96@09:25h Intermediate Version

Semiconductor Group

C167CR-16RM

Memory Cycle Variables

The timing tables below use three variables which are derived from the BUSCONx registers and
represent the special characteristics of the programmed memory cycle. The following table
describes, how these variables are to be computed.

AC Characteristics
Multiplexed Bus

= 5 V

10 %;

= 0 V

= 0 to +70 °C

for SAB-C167CR-16RM

= -40 to +85 °C

for SAF-C167CR-16RM

= -40 to +125 °C

for SAK-C167CR-16RM

(for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF

(for Port 6, CS) = 100 pF

ALE cycle time = 6 TCL + 2

(150 ns at 20-MHz CPU clock without waitstates)

Description

Symbol Values

ALE Extension

TCL * <ALECTL>

Memory Cycle Time Waitstates

2TCL * (15 - <MCTC>)

Memory Tristate Time

2TCL * (1 - <MTTC>)

Parameter

Symbol

Max. CPU Clock

= 20 MHz

Variable CPU Clock

1/2TCL = 1 to 20 MHz

Unit

min.

max.

min.

max.

ALE high time

15 +

TCL - 10 +

Address setup to ALE

10 +

TCL - 15 +

Address hold after ALE

15 +

TCL - 10 +

ALE falling edge to RD,
WR (with RW-delay)

15 +

TCL - 10 +

ALE falling edge to RD,
WR (no RW-delay)

-10 +

Address float after RD,
WR (with RW-delay)

Address float after RD,
WR (no RW-delay)

TCL + 5

RD, WR low time
(with RW-delay)

40 +

2TCL - 10
+

RD, WR low time
(no RW-delay)

65 +

3TCL - 10
+

20Dec96@09:25h Intermediate Version

Semiconductor Group

C167CR-16RM

RD to valid data in
(with RW-delay)

30 +

2TCL - 20
+

RD to valid data in
(no RW-delay)

55 +

3TCL - 20
+

ALE low to valid data in

55
+

3TCL - 20
+

Address to valid data in

70
+

4TCL - 30
+

Data hold after RD
rising edge

Data float after RD

35 +

2TCL - 15
+

Data valid to WR

25 +

2TCL - 25
+

Data hold after WR

35 +

2TCL - 15
+

ALE rising edge after RD,
WR

35 +

2TCL - 15
+

Address hold after RD,
WR

35 +

2TCL - 15
+

ALE falling edge to CS

-5 -

10 -

-5 -

10 -

CS low to Valid Data In

55
+

3TCL - 20
+

CS hold after RD, WR

60 +

3TCL - 15
+

ALE fall. edge to RdCS,
WrCS (with RW delay)

20 +

TCL - 5
+

ALE fall. edge to RdCS,
WrCS (no RW delay)

-5 +

-5
+

Address float after RdCS,
WrCS (with RW delay)

Address float after RdCS,
WrCS (no RW delay)

TCL

RdCS to Valid Data In
(with RW delay)

25 +

2TCL - 25
+

Parameter

Symbol

Max. CPU Clock

= 20 MHz

Variable CPU Clock

1/2TCL = 1 to 20 MHz

Unit

min.

max.

min.

max.

20Dec96@09:25h Intermediate Version

Semiconductor Group

C167CR-16RM

RdCS to Valid Data In
(no RW delay)

50 +

3TCL - 25
+

RdCS, WrCS Low Time
(with RW delay)

40 +

2TCL - 10
+

RdCS, WrCS Low Time
(no RW delay)

65 +

3TCL - 10
+

Data valid to WrCS

35 +

2TCL - 15
+

Data hold after RdCS

Data float after RdCS

30 +

2TCL - 20
+

Address hold after
RdCS, WrCS

30 +

2TCL - 20
+

Data hold after WrCS

30 +

2TCL - 20
+

Parameter

Symbol

Max. CPU Clock

= 20 MHz

Variable CPU Clock

1/2TCL = 1 to 20 MHz

Unit

min.

max.

min.

max.

20Dec96@09:25h Intermediate Version

Semiconductor Group

C167CR-16RM

Figure 14-1
External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Normal ALE

Data In

Data Out

Address

ALE

CSx

A23-A16

(A15-A8)

BHE

BUS

Read Cycle

RdCSx

BUS

Write Cycle

WR,

WRL, WRH

WrCSx

20Dec96@09:25h Intermediate Version

Semiconductor Group

C167CR-16RM

Figure 14-2
External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Extended ALE

Data Out

Address

Data In

Address

ALE

CSx

A23-A16

(A15-A8)

BHE

BUS

Read Cycle

RdCSx

BUS

Write Cycle

WR,

WRL, WRH

WrCSx

20Dec96@09:25h Intermediate Version

Semiconductor Group

C167CR-16RM

Figure 14-3
External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Normal ALE

Data Out

Address

Data In

Address

ALE

CSx

A23-A16

(A15-A8)

BHE

BUS

Read Cycle

RdCSx

BUS

Write Cycle

WR,

WRL, WRH

WrCSx

20Dec96@09:25h Intermediate Version

Semiconductor Group

C167CR-16RM

Figure 14-4
External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Extended ALE

Data Out

Address

Data In

Address

ALE

CSx

A23-A16

(A15-A8)

BHE

BUS

Read Cycle

RdCSx

BUS

Write Cycle

WR,

WRL, WRH

WrCSx

20Dec96@09:25h Intermediate Version

Semiconductor Group

C167CR-16RM

AC Characteristics
Demultiplexed Bus

= 5 V

10 %;

= 0 V

= 0 to +70 °C

for SAB-C167CR-16RM

= -40 to +85 °C

for SAF-C167CR-16RM

= -40 to +125 °C

for SAK-C167CR-16RM

(for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF

(for Port 6, CS) = 100 pF

ALE cycle time = 4 TCL + 2

(100 ns at 20-MHz CPU clock without waitstates)

Parameter

Symbol

Max. CPU Clock

= 20 MHz

Variable CPU Clock

1/2TCL = 1 to 20 MHz

Unit

min.

max.

min.

max.

ALE high time

15 +

TCL - 10 +

Address setup to ALE

10 +

TCL - 15 +

ALE falling edge to RD,
WR (with RW-delay)

15 +

TCL - 10
+

ALE falling edge to RD,
WR (no RW-delay)

-10 +

-10
+

RD, WR low time
(with RW-delay)

40 +

2TCL - 10
+

RD, WR low time
(no RW-delay)

65 +

3TCL - 10
+

RD to valid data in
(with RW-delay)

30 +

2TCL - 20
+

RD to valid data in
(no RW-delay)

55 +

3TCL - 20
+

ALE low to valid data in

55
+

3TCL - 20
+

Address to valid data in

70
+

4TCL - 30
+

Data hold after RD
rising edge

Data float after RD rising
edge (with RW-delay

)

35 +

2TCL - 15
+

Data float after RD rising
edge (no RW-delay

)

15 +

TCL - 10
+

Data valid to WR

25 +

2TCL - 25
+

Data hold after WR

15 +

TCL - 10 +

20Dec96@09:25h Intermediate Version

Semiconductor Group

C167CR-16RM

RW-delay and

refer to the next following bus cycle.

ALE rising edge after RD,
WR

-10 +

-10
+

Address hold after RD,
WR

0 +

0
+

ALE falling edge to CS

-5 -

10 -

-5 -

10 -

CS low to Valid Data In

55
+

3TCL - 20
+

CS hold after RD, WR

10 +

TCL - 15
+

ALE falling edge to RdCS,
WrCS (with RW-delay)

20 +

TCL - 5
+

ALE falling edge to RdCS,
WrCS (no RW-delay)

-5 +

-5
+

RdCS to Valid Data In
(with RW-delay)

25 +

2TCL - 25
+

RdCS to Valid Data In
(no RW-delay)

50 +

3TCL - 25
+

RdCS, WrCS Low Time
(with RW-delay)

40 +

2TCL - 10
+

RdCS, WrCS Low Time
(no RW-delay)

65 +

3TCL - 10
+

Data valid to WrCS

35 +

2TCL - 15
+

Data hold after RdCS

Data float after RdCS
(with RW-delay)

30 +

2TCL - 20
+

Data float after RdCS
(no RW-delay)

5 +

TCL - 20
+

Address hold after
RdCS, WrCS

-10 +

-10
+

Data hold after WrCS

10 +

TCL - 15
+

Parameter

Symbol

Max. CPU Clock

= 20 MHz

Variable CPU Clock

1/2TCL = 1 to 20 MHz

Unit

min.

max.

min.

max.

20Dec96@09:25h Intermediate Version

Semiconductor Group

C167CR-16RM

Figure 15-1
External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Normal ALE

Data Out

Data In

Address

ALE

CSx

A23-A16

A15-A0

BHE

BUS

(D15-D8)

D7-D0

Read Cycle

RdCSx

Write Cycle

WrCSx

BUS

(D15-D8)

D7-D0

WR,

WRL, WRH

20Dec96@09:25h Intermediate Version

Semiconductor Group

C167CR-16RM

Figure 15-2
External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Extended ALE

Data Out

Data In

Address

ALE

CSx

A23-A16

A15-A0

BHE

Read Cycle

RdCSx

Write Cycle

WrCSx

BUS

(D15-D8)

D7-D0

BUS

(D15-D8)

D7-D0

WR,

WRL, WRH

20Dec96@09:25h Intermediate Version

Semiconductor Group

C167CR-16RM

Figure 15-3
External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Normal ALE

Data Out

Data In

Address

ALE

CSx

A23-A16

A15-A0

BHE

Read Cycle

RdCSx

Write Cycle

WrCSx

BUS

(D15-D8)

D7-D0

BUS

(D15-D8)

D7-D0

WR,

WRL, WRH

20Dec96@09:25h Intermediate Version

Semiconductor Group

C167CR-16RM

Figure 15-4
External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Extended ALE

Data Out

Data In

Address

ALE

CSx

A23-A16

A15-A0

BHE

Read Cycle

RdCSx

Write Cycle

WR,

WRL, WRH

WrCSx

BUS

(D15-D8)

D7-D0

BUS

(D15-D8)

D7-D0

20Dec96@09:25h Intermediate Version

Semiconductor Group

C167CR-16RM

AC Characteristics
CLKOUT and READY

= 5 V

10 %;

= 0 V

= 0 to +70 °C

for SAB-C167CR-16RM

= -40 to +85 °C

for SAF-C167CR-16RM

= -40 to +125 °C

for SAK-C167CR-16RM

(for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF

(for Port 6, CS) = 100 pF

Notes

These timings are given for test purposes only, in order to assure recognition at a specific clock edge.

Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This
adds even more time for deactivating READY.
The 2t

and t

refer to the next following bus cycle, t

refers to the current bus cycle.

Parameter

Symbol

Max. CPU Clock

= 20 MHz

Variable CPU Clock

1/2TCL = 1 to 20 MHz

Unit

min.

max.

min.

max.

CLKOUT cycle time

2TCL

CLKOUT high time

TCL 5

CLKOUT low time

TCL 10

CLKOUT rise time

CLKOUT fall time

CLKOUT rising edge to
ALE falling edge

0 +

10 +

0 +

10 +

Synchronous READY
setup time to CLKOUT

Synchronous READY
hold time after CLKOUT

Asynchronous READY
low time

2TCL + 15

Asynchronous READY
setup time

Asynchronous READY
hold time

Async. READY hold time
after RD, WR high
(Demultiplexed Bus)

0
+ 2

TCL - 25
+

20Dec96@09:25h Intermediate Version

Semiconductor Group

C167CR-16RM

Figure 16
CLKOUT and READY

Notes

Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS).

The leading edge of the respective command depends on RW-delay.

READY sampled HIGH at this sampling point generates a READY controlled waitstate,
READY sampled LOW at this sampling point terminates the currently running bus cycle.

READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or
WR).

If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT
(eg. because CLKOUT is not enabled), it must fulfill

in order to be safely synchronized. This is guaranteed,

if READY is removed in reponse to the command (see Note

Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may
be inserted here.
For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without
MTTC waitstate this delay is zero.

The next external bus cycle may start here.

AAAA

CLKOUT

ALE

Sync

READY

Async

READY

waitstate

READY

MUX/Tristate

Running cycle

Command

RD, WR

see 6)

20Dec96@09:25h Intermediate Version

Semiconductor Group

C167CR-16RM

AC Characteristics
External Bus Arbitration

= 5 V

10 %;

= 0 V

= 0 to +70 °C

for SAB-C167CR-16RM

= -40 to +85 °C

for SAF-C167CR-16RM

= -40 to +125 °C

for SAK-C167CR-16RM

(for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF

(for Port 6, CS) = 100 pF

Parameter

Symbol

Max. CPU Clock

= 20 MHz

Variable CPU Clock

1/2TCL = 1 to 20 MHz

Unit

min.

max.

min.

max.

HOLD input setup time
to CLKOUT

CLKOUT to HLDA high
or BREQ low delay

CLKOUT to HLDA low
or BREQ high delay

CSx release

CSx drive

-5

Other signals release

Other signals drive

-5

20Dec96@09:25h Intermediate Version

Semiconductor Group

C167CR-16RM

Figure 17
External Bus Arbitration, Releasing the Bus

Notes

The C167CR-16RM will complete the currently running bus cycle before granting bus access.

This is the first possibility for BREQ to get active.

The CS outputs will be resistive high (pullup) after

AAAA

CLKOUT

HOLD

HLDA

Other

Signals

AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA

CSx

(On P6.x)

BREQ

AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA

20Dec96@09:25h Intermediate Version

Semiconductor Group

C167CR-16RM

Figure 18
External Bus Arbitration, (Regaining the Bus)

Notes

This is the last chance for BREQ to trigger the indicated regain-sequence.
Even if BREQ is activated earlier, the regain-sequence is initiated by HOLD going high.
Please note that HOLD may also be deactivated without the C167CR-16RM requesting the bus.

The next C167CR-16RM driven bus cycle may start here.

CLKOUT

HOLD

HLDA

Other

Signals

AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA

CSx

(On P6.x)

AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA

BREQ

20Dec96@09:25h Intermediate Version

Semiconductor Group

C167CR-16RM

Package Outline

Figure 19

Sorts of Packing

Package outlines for tubes, trays, etc. are contained in our
Data Book "Package Information"

SMD = Surface Mounted Device

Dimensions in mm

Plastic Package, P-MQFP-144-1 (SMD)
(Plastic Metric Quad Flat Package)

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SAB-C167CR-16RM

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SAB-C167CR-16RM