C515A Data Sheet

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Edition 10.97
Published by

Siemens AG,

Bereich Halbleiter, Marketing-
Kommunikation, Balanstraße 73,
81541 München

Siemens AG 1997.

Attention please!

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and circuits implemented within components or assemblies.
The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved.
For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies
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your nearest Siemens Office, Semiconductor Group.
Siemens AG is an approved CECC manufacturer.

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Components used in life-support devices or systems must be expressly authorized for such purpose!

Critical components

of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems

with the express

written approval of the Semiconductor Group of Siemens AG.
1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the

failure of that life-support device or system, or to affect its safety or effectiveness of that device or system.

2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain hu-

man life. If they fail, it is reasonable to assume that the health of the user may be endangered.

Semiconductor Group

1997-10-01

8-Bit CMOS Microcontroller

Advance Information

C515A

Full upward compatibility with SAB 80C515A/83C515A-5

Up to 24 MHz external operating frequency
500 ns instruction cycle at 24 MHz operation

32K byte on-chip ROM (with optional ROM protection)
alternatively up to 64K byte external program memory

Up to 64K byte external data memory

256 byte on-chip RAM

1K byte on-chip RAM (XRAM)

Six 8-bit parallel I/O ports

One input port for analog/digital input

Full duplex serial interface (USART)
4 operating modes, fixed or variable baud rates

Three 16-bit timer/counters
Timer 0 / 1 (C501 compatible)
Timer 2 for 16-bit reload, compare, or capture functions

(further features are on next page)

Figure 1
C515A Functional Units

I / O

MCA03239

ROM

RAM

XRAM

CPU

USART

I / O

Timer

Watchdog

I / O

Analog /

Digital

Input

Watchdog

Oscillator

A / D Converter

10-Bit

Support Module

On-Chip Emulation

Power

Saving
Modes

Port 3

Port 2

Port 1

Port 0

Port 4

Port 5

Port 6

T 1

T 0

T 2

1 K x 8

256 x 8

32 k x 8

C515A

Semiconductor Group

1997-10-01

Features

(cont'd):

10-bit A/D converter
8 multiplexed analog inputs
Built-in self calibration

16-bit watchdog timer

Power saving modes
Slow down mode
Idle mode (can be combined with slow down mode)
Software power down mode with wake-up capability through INT0 pin
Hardware power down mode

12 interrupt sources (7 external, 5 internal) selectable at 4 priority levels

ALE switch-off capability

On-chip emulation support logic (Enhanced Hooks Technology

)

P-MQFP-80-1 package

Temperature Ranges:

SAB-C515A

= 0 to 70

SAF-C515A

= 40 to 85

SAH-C515A

= 40 to 85

SAK-C515

= 40 to 110

C (max. operating frequency: 18 MHz)

The C515A is an upward compatible version of the SAB 80C515A/83C515A-5 8-bit microcontroller
which additionally provides an improved 10-bit A/D converter, ALE switch-off capability, on-chip
emulation support, ROM protection, and enhanced power saving mode capabilities. With a

maximum external clock rate of 24 MHz it achieves a 500 ns instruction cycle time (1

s at 12 MHz).

The C515A is mounted in a P-MQFP-80 package.

Note:

Versions for extended temperature ranges 40

C to 110

C and 40

C to 125

(SAH-C515A and SAK-C515A) are available on request. The ordering number of ROM
types (DXXXX extensions) is defined after program release (verification) of the customer.

Ordering Information

Type

Ordering Code

Package

Description
(8-Bit CMOS microcontroller)

SAB-C515A-4RM

Q67121-DXXXX P-MQFP-80-1 with mask programmable ROM (18 MHz)

SAF-C515A-4RM

Q67121-DXXXX P-MQFP-80-1 with mask programmable ROM (18 MHz)

ext. temp. 40

C to 85

SAB-C515A-4R24M Q67121-DXXXX P-MQFP-80-1 with mask programmable ROM (24 MHz)

SAF-C515A-4R24M Q67121-DXXXX P-MQFP-80-1 with mask programmable ROM (24 MHz)

ext. temp. 40

C to 85

SAB-C515A-LM

Q67121-C1068

P-MQFP-80-1 for external memory (18 MHz)

SAF-C515A-LM

Q67121-C1069

P-MQFP-80-1 for external memory (18 MHz)

ext. temp. 40

C to 85

SAB-C515A-L24M

Q67121-C1070

P-MQFP-80-1 for external memory (24 MHz)

SAF-C515A-L24M

Q67127-C2020

P-MQFP-80-1 for external memory (24 MHz)

ext. temp. 40

C to 85

C515A

Semiconductor Group

1997-10-01

Figure 3
Pin Configuration P-MQFP-80 Package

(top view)

P5.7

P0.7 / AD7

P0.5 / AD5

P0.6 / AD6

P0.0 / AD0

P0.1 / AD1

P2.7 / A15

P2.6 / A14

PSEN

N.C.

ALE

P5.0

P5.5

P5.6

P5.4
P5.3

P5.1

P5.2

P4.4

P4.3

N.C.

HWPD

P3.2 / INT0

N.C.

P6.6 / AIN6

P6.4 / AIN4

P6.5 / AIN5

P6.7 / AIN7

RESET

P1.7 / T2

P1.6 / CLKOUT

P1.5 / T2EX

P1.4 / INT2

P1.0 / INT3 / CC0

XTAL2

XTAL1

P2.1 / A9

P2.2 / A10

MCP03241

P0.4 / AD4

P0.3 / AD3

P0.2 / AD2

P6.3 / AIN3

P6.2 / AIN2

P6.1 / AIN1

P3.0 / RxD

P3.1 / TxD

P2.0 / A8

C515A

P3.5 / T1

P3.4 / T0

P3.3 / INT1

N.C.

P4.7

P4.6

P4.5

P2.3 / A11

P2.4 / A12

P2.5 / A13

P3.6 / WR

N.C.
P3.7 / RD

P1.1 / INT4 / CC1
P1.2 / INT5 / CC2

AREF

AGND

P6.0 / AIN0

N.C.

P1.3 / INT6 / CC3

N.C.

P4.0 / ADST

P4.1
P4.2

PE / SWD

2 3 4 5 6 7 8 9

11 12

14 15 16 17 18 19

39
38
37
36
35
34
33

59 58

62
63
64
65
66
67
68
69

Semiconductor Group

1997-10-01

C515A

Table 1
Pin Definitions and Functions

Symbol

Pin Number

(P-MQFP-80)

I/O*)

Function

P4.0-P4.7

72-74,
76-80

I/O

Port 4

is an 8-bit quasi-bidirectional I/O port with internal pull-
up resistors. Port 4 pins that have 1's written to them are
pulled high by the internal pull-up resistors, and in that
state can be used as inputs. As inputs, port 4 pins being

externally pulled low will source current (

, in the DC

characteristics) because of the internal pull-up resistors.
P4 also contains the external A/D converter control pin.
The output latch corresponding to a secondary function
must be programmed to a one (1) for that function to
operate. The secondary function is assigned to port 6 as
follows:
P4.0 / ADST

external A/D converter start pin

PE/SWD

Power Saving Mode

Enable / Start Watchdog Timer

A low level on this pin allows the software to enter the
power down, idle, and slow down mode. In case the low
level is also seen during reset, the watchdog timer
function is off on default.
Use of the software controlled power saving modes is
blocked when this pin is held on high level. A high level
during reset performs an automatic start of the
watchdog timer immediately after reset.
When left unconnected this pin is pulled high by a weak
internal pull-up resistor.

Note: If PE/SWD is low and V

AREF

is low the oscillator

watchdog is disabled (testmode)!

RESET

RESET

A low level on this pin for the duration of two machine
cycles while the oscillator is running resets the C515A.
A small internal pullup resistor permits power-on reset

using only a capacitor connected to V

VAREF

Reference Voltage

for the A/D converter

VAGND

Reference Ground

for the A/D converter

P6.0-P6.7

12-5

Port 6

is an 8-bit unidirectional input port to the A/D converter.
Port pins can be used for digital input, if voltage levels
simultaneously meet the specifications for high/low input
voltages and for the eight multiplexed analog inputs.

*) I = Input

O = Output

C515A

Semiconductor Group

1997-10-01

P3.0-P3.7

15-22

19
20
21

I/O

Port 3
is an 8-bit quasi-bidirectional I/O port with internal pullup
resistors. Port 3 pins that have 1's written to them are
pulled high by the internal pullup resistors, and in that
state can be used as inputs. As inputs, port 3 pins being
externally pulled low will source current (

, in the DC

characteristics) because of the internal pullup resistors.
Port 3 also contains the interrupt, timer, serial port and
external memory strobe pins that are used by various
options. The output latch corresponding to a secondary
function must be programmed to a one (1) for that
function to operate. The secondary functions are
assigned to the pins of port 3, as follows:
P3.0 / RxD

Receiver data input (asynch.)
or data input/output (synch.)
of serial interface

P3.1 / TxD

Transmitter data output
(asynch.) or clock output
(synch.) of serial interface

P3.2 / INT0

External interrupt 0 input /
timer 0 gate control input

P3.3 / INT1

External interrupt 1 input /
timer 1 gate control input

P3.4 / T0

Timer 0 counter input

P3.5 / T1

Timer 1 counter input

P3.6 / WR

WR control output; latches
the data byte from port 0 into
the external data memory

P3.7 / RD

RD control output; enables
the external data memory

*) I = Input

O = Output

Table 1
Pin Definitions and Functions (cont'd)

Symbol

Pin Number

(P-MQFP-80)

I/O*)

Function

Semiconductor Group

1997-10-01

C515A

P1.0 - P1.7

31-24

27
26

25
24

I/O

Port 1
is an 8-bit quasi-bidirectional I/O port with internal pullup
resistors. Port 1 pins that have 1's written to them are
pulled high by the internal pullup resistors, and in that
state can be used as inputs. As inputs, port 1 pins being
externally pulled low will source current (

, in the DC

characteristics) because of the internal pullup resistors.
The port is used for the low-order address byte during
program verification. Port 1 also contains the interrupt,
timer, clock, capture and compare pins that are used by
various options. The output latch corresponding to a
secondary function must be programmed to a one (1) for
that function to operate (except when used for the
compare functions). The secondary functions are
assigned to the port 1 pins as follows:
P1.0 / INT3 / CC0

Interrupt 3 input /
compare 0 output /
capture 0 input

P1.1 / INT4 / CC1

Interrupt 4 input /
compare 1 output /
capture 1 input

P1.2 / INT5 / CC2

Interrupt 5 input /
compare 2 output /
capture 2 input

P1.3 / INT6 / CC3

Interrupt 6 input /
compare 3 output /
capture 3 input

P1.4 / INT2

Interrupt 2 input

P1.5 / T2EX

Timer 2 external reload /
trigger input

P1.6 / CLKOUT

System clock output

P1.7 / T2

Counter 2 input

32, 33

Supply Voltage
during normal, idle, and power down mode.

34, 35

Ground (0V)
during normal, idle, and power down operation.

*) I = Input

O = Output

Table 1
Pin Definitions and Functions (cont'd)

Symbol

Pin Number

(P-MQFP-80)

I/O*)

Function

C515A

Semiconductor Group

1997-10-01

XTAL2

XTAL2
Input to the inverting oscillator amplifier and input to the
internal clock generator circuits. To drive the device
from an external clock source, XTAL2 should be driven,
while XTAL1 is left unconnected.

Minimum and

maximum high and low times as well as rise/fall times
specified in the AC characteristics must be observed.

XTAL1

XTAL1
Output of the inverting oscillator amplifier.

P2.0-P2.7

38-45

I/O

Port 2
is an 8-bit quasi-bidirectional I/O port with internal pullup
resistors. Port 2 pins that have 1's written to them are
pulled high by the internal pullup resistors, and in that
state can be used as inputs. As inputs, port 2 pins being
externally pulled low will source current (

, in the DC

characteristics) because of the internal pullup resistors.
Port 2 emits the high-order address byte during fetches
from external program memory and during accesses to
external data memory that use 16-bit addresses
(MOVX @DPTR). In this application it uses strong
internal pullup resistors when issuing 1's. During
accesses to external data memory that use 8-bit
addresses (MOVX @Ri), port 2 issues the contents of
the P2 special function register.

PSEN

The Program Store Enable
output is a control signal that enables the external
program memory to the bus during external fetch
operations. It is activated every six oscillator periods,
except during external data memory accesses. The
signal remains high during internal program execution.

ALE

The Address Latch Enable
output is used for latching the address into external
memory during normal operation. It is activated every
six oscillator periods, except during an external data
memory access. ALE can be switched off when the
program is executed internally.

*) I = Input

O = Output

Table 1
Pin Definitions and Functions (cont'd)

Symbol

Pin Number

(P-MQFP-80)

I/O*)

Function

Semiconductor Group

1997-10-01

C515A

External Access Enable
When held high, the C515A executes instructions from
the internal ROM (C515A-4R) as long as the PC is less
than 8000H. When held low, the C515A fetches all
instructions from external program memory. For the
C515A-L this pin must be tied low.

P0.0-P0.7

52-59

I/O

Port 0
is an 8-bit open-drain bidirectional I/O port. Port 0 pins
that have 1's written to them float, and in that state can
be used as high-impedance inputs.
Port 0 is also the multiplexed low-order address and
data bus during accesses to external program and data
memory. In this application it uses strong internal pullup
resistors when issuing 1's. Port 0 also outputs the code
bytes during program verification in the C515A-4R.
External pullup resistors are required during program
verification.

P5.0-P5.7

67-60

I/O

Port 5
is an 8-bit quasi-bidirectional I/O port with internal pullup
resistors. Port 5 pins that have 1's written to them are
pulled high by the internal pullup resistors, and in that
state can be used as inputs. As inputs, port 5 pins being
externally pulled low will source current (

, in the DC

characteristics) because of the internal pullup resistors.

HWPD

Hardware Power Down
A low level on this pin for the duration of one machine
cycle while the oscillator is running resets the C515A. A
low level for a longer period will force the C515A into
Hardware Power Down Mode with the pins floating.

N.C.

2, 13, 14, 23,
46, 50, 51, 68,
70, 71

Not connected
These pins of the P-MQFP-80 package need not be
connected.

*) I = Input

O = Output

Table 1
Pin Definitions and Functions (cont'd)

Symbol

Pin Number

(P-MQFP-80)

I/O*)

Function

Semiconductor Group

1997-10-01

C515A

CPU

The C515A is efficient both as a controller and as an arithmetic processor. It has extensive facilities
for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program
memory results from an instruction set consisting of 44 % one-byte, 41 % two-byte, and 15%
three-byte instructions. With a 18 MHz crystal, 58% of the instructions are executed in 666 ns

(

24 MHz : 500 ns).

Special Function Register PSW (Address D0H)

Reset Value : 00H

Bit

Function

Carry Flag
Used by arithmetic instruction.

Auxiliary Carry Flag
Used by instructions which execute BCD operations.

General Purpose Flag

RS1
RS0

Overflow Flag
Used by arithmetic instruction.

General Purpose Flag

Parity Flag
Set/cleared by hardware after each instruction to indicate an odd/even
number of "one" bits in the accumulator, i.e. even parity.

RS1

RS0

D0H

PSW

D7H

D6H

D5H

D4H

D3H

D2H

D1H

D0H

Bit No.

MSB

LSB

RS1

RS0

Function

Bank 0 selected, data address 00H-07H

Bank 1 selected, data address 08H-0FH

Bank 2 selected, data address 10H-17H

Bank 3 selected, data address 18H-1FH

C515A

Semiconductor Group

1997-10-01

Memory Organization

The C515A CPU manipulates operands in the following five address spaces:

up to 64 Kbyte of program memory (32K on-chip program memory for C515A-4R)
up to 64 Kbyte of external data memory
256 bytes of internal data memory
1K bytes of internal XRAM data memory
a 128 byte special function register area

Figure 5 illustrates the memory address spaces of the C515A.

Figure 5
C515A Memory Map

Ext.

Int.

EA = 1)

Ext.

Data

Memory

Internal

XRAM

(1 KByte)

Ext.

FFFF

8000

7FFF

0000

Data

Memory

Ext.

FC00

Regs.

Function

Special

RAM

Internal

RAM

Internal

Addr.

Indirect

Addr.

Direct

Alternatively

"Code Space"

"Data Space"

"Internal Data Space"

MCB03243

EA = 1)

FFFF

0000

FBFF

Semiconductor Group

1997-10-01

C515A

Enhanced Hooks Emulation Concept

The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative
way to control the execution of C500 MCUs and to gain extensive information on the internal
operation of the controllers. Emulation of on-chip ROM based programs is possible, too.

Each production chip has built-in logic for the support of the Enhanced Hooks Emulation Concept.
Therefore, no costly bond-out chips are necessary for emulation. This also ensure that emulation
and production chips are identical.

The Enhanced Hooks Technology

, which requires embedded logic in the C500 allows the C500

together with an EH-IC to function similar to a bond-out chip. This simplifies the design and reduces
costs of an ICE-system. ICE-systems using an EH-IC and a compatible C500 are able to emulate
all operating modes of the different versions of the C500 microcontrollers. This includes emulation
of ROM, ROM with code rollover and ROMless modes of operation. It is also able to operate in
single step mode and to read the SFRs after a break.

Figure 8
Basic C500 MCU Enhanced Hooks Concept Configuration

Port 0, port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks
Emulation Concept to control the operation of the device during emulation and to transfer
informations about the program execution and data transfer between the external emulation
hardware (ICE-system) and the C500 MCU.

1 "Enhanced Hooks Technology" is a trademark and patent of Metalink Corporation licensed to Siemens.

SYSCON

PCON

TCON

RESET

ALE

PSEN

Port 0

Port 2

Port 1

Port 3

opt.

I/O Ports

C500

MCU

RPCON

RTCON

Enhanced Hooks

Interface Circuit

RSYSCON

RPORT RPORT

TEA TALE TPSEN

EH-IC

ICE-System interface

to emulation hardware

Target System Interface

MCS03254

C515A

Semiconductor Group

1997-10-01

Special Function Registers

The registers, except the program counter and the four general purpose register banks, reside in
the special function register area. The special function register area consists of two portions: the
standard special function register area and the mapped special function register area. One special
function register of the C515A (PCON1) is located in the mapped special function register area. For
accessing this mapped special function register, bit RMAP in special function register SYSCON
must be set. All other special function registers are located in the standard special function register
area which is accessed when RMAP is cleared ("0").

Special Function Register SYSCON (Address B1H)

Reset Value : XX10XX01B

As long as bit RMAP is set, the mapped special function register area (SFR PCON1) can be
accessed. This bit is not cleared by hardware automatically. Thus, when non-mapped/mapped
registers are to be accessed, the bit RMAP must be cleared/set respectively by software.

The 49 special function registers (SFRs) in the standard and mapped SFR area include pointers
and registers that provide an interface between the CPU and the other on-chip peripherals. All
SFRs with addresses where address bits 0-2 are 0 (e.g. 80H, 88H, 90H, 98H, ..., F8H, FFH) are
bitaddressable. The SFRs of the C515A are listed in table 2 and table 3. In table 2 they are
organized in groups which refer to the functional blocks of the C515A. Table 3 illustrates the
contents of the SFRs in numeric order of their addresses.

Bit

Function

RMAP

Special function register map bit
RMAP = 0: The access to the non-mapped (standard) special function

RMAP = 1: The access to the mapped special function register area (SFR

PCON1) is enabled.

Reserved bits for future use. Read by CPU returns undefined values.

EALE

RMAP

B1H

SYSCON

Bit No.

MSB

LSB

XMAP1

XMAP0

The functions of the shaded bits are not described in this section.

Semiconductor Group

1997-10-01

C515A

Table 2
Special Function Registers - Functional Blocks

Block

Symbol

Name

Address

Contents after
Reset

CPU

ACC
B
DPH
DPL
PSW
SP

SYSCON

Accumulator
B-Register
Data Pointer, High Byte
Data Pointer, Low Byte
Program Status Word Register
Stack Pointer
System/XRAM Control Register

E0H

F0H

83H
82H
D0H

81H
B1H

00H
00H
00H
00H
00H
07H
XX10 XX01B

A/D-
Converter

ADCON0

ADCON1
ADDATH
ADDATL

A/D Converter Control Register 0
A/D Converter Control Register 1
A/D Converter Data Register, High Byte
A/D Converter Data Register, low Byte

D8H

DCH
D9H
DAH

00H
0XXX X000B

00H
00XX XXXXB

Interrupt
System

IEN0

IEN1

IP0

IP1

IRCON
TCON

T2CON

SCON

Interrupt Enable Register 0
Interrupt Enable Register 1
Interrupt Priority Register 0
Interrupt Priority Register 1
Interrupt Request Control Register
Timer Control Register
Timer 2 Control Register
Serial Channel Control Register

A8H

B8H

A9H
B9H
C0H

88H

C8H

98H

00H
00H
00H
XX00 0000B

00H
00H
00H
00H

Timer 0/
Timer 1

TCON

TH0
TH1
TL0
TL1
TMOD

Timer 0/1 Control Register
Timer 0, High Byte
Timer 1, High Byte
Timer 0, Low Byte
Timer 1, Low Byte
Timer Mode Register

88H

8CH
8DH
8AH
8BH
89H

00H
00H
00H
00H
00H
00H

Compare/
Capture
Unit /
Timer 2

CCEN
CCH1
CCH2
CCH3
CCL1
CCL2
CCL3
CRCH
CRCL
TH2
TL2
T2CON

Comp./Capture Enable Reg.
Comp./Capture Reg. 1, High Byte
Comp./Capture Reg. 2, High Byte
Comp./Capture Reg. 3, High Byte
Comp./Capture Reg. 1, Low Byte
Comp./Capture Reg. 2, Low Byte
Comp./Capture Reg. 3, Low Byte
Com./Rel./Capt. Reg. High Byte
Com./Rel./Capt. Reg. Low Byte
Timer 2, High Byte
Timer 2, Low Byte
Timer 2 Control Register

C1H
C3H
C5H
C7H
C2H
C4H
C6H
CBH
CAH
CDH
CCH
C8H

00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H

C515A

Semiconductor Group

1997-10-01

Ports

P0
P1
P2
P3
P4
P5
P6

Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6, Analog/Digital Input

80H

90H

A0H

B0H

E8H

F8H

DBH

FFH
FFH
FFH
FFH
FFH
FFH

XRAM

XPAGE

SYSCON

Page Address Register for Extended
On-Chip RAM
System/XRAM Control Register

91H

B1H

00H

XX10 XX01B

Serial
Channel

ADCON0

PCON

SBUF
SCON

SRELL
SRELH

A/D Converter Control Register
Power Control Register
Serial Channel Buffer Register
Serial Channel Control Register
Serial Channel Reload Register, Low Byte
Serial Channel Reload Register, High Byte

D8H

87H
99H
98H

AAH
BAH

00H
00H
XXH

00H
D9H
XXXX XX11B

Watchdog IEN0

IEN1

IP0

2))

IP1

WDTREL

Interrupt Enable Register 0
Interrupt Enable Register 1
Interrupt Priority Register 0
Interrupt Priority Register 1
Watchdog Timer Reload Register

A8H

B8H

A9H
B9H
86H

00H
00H
00H
XX00 0000B

00H

Power
Saving
Modes

PCON

PCON1

Power Control Register
Power Control Register 1

87H
88H

00H
0XXX XXXXB

1) Bit-addressable special function registers
2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.
3) "X" means that the value is undefined and the location is reserved.
4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.

Table 2
Special Function Registers - Functional Blocks (cont'd)

Block

Symbol

Name

Address

Contents after
Reset

Semiconductor Group

1997-10-01

C515A

Table 3
Contents of the SFRs, SFRs in numeric order of their addresses

Addr Register Content

after
Reset

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

80H

FFH

81H SP

07H

82H DPL

00H

83H DPH

00H

86H WDTREL 00H

WDT
PSEL

87H PCON

00H

SMOD PDS

IDLS

GF1

GF0

PDE

IDLE

88H

TCON

00H

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

88H

PCON1

0XXX-
XXXXB

EWPD

89H TMOD

00H

GATE

C/T

GATE

C/T

8AH TL0

00H

8BH TL1

00H

8CH TH0

00H

8DH TH1

00H

90H

FFH

CLK-
OUT

T2EX

INT2

INT6

INT5

INT4

INT3

91H XPAGE

00H

98H

SCON

00H

SM0

SM1

SM2

REN

TB8

RB8

99H SBUF

XXH

A0H

FFH

A8H

IEN0

00H

EAL

WDT

ET2

ET1

EX1

ET0

EX0

A9H IP0

00H

OWDS WDTS

AAH SRELL

D9H

B0H

FFH

INT1

INT0

TxD

RxD

B1H SYSCON XX10-

XX01B

EALE

RMAP

XMAP1 XMAP0

B8H

IEN1

00H

EXEN2 SWDT

EX6

EX5

EX4

EX3

EX2

EADC

B9H IP1

XX00-
0000B

1) X means that the value is undefined and the location is reserved
2) Bit-addressable special function registers
3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.

C515A

Semiconductor Group

1997-10-01

BAH SRELH

XXXX-
XX11B

C0H

IRCON

00H

EXF2

TF2

IEX6

IEX5

IEX4

IEX3

IEX2

IADC

C1H CCEN

00H

COCA
H3

COCAL
3

COCA
H2

COCAL
2

COCA
H1

COCAL
1

COCA
H0

COCAL
0

C2H CCL1

00H

C3H CCH1

00H

C4H CCL2

00H

C5H CCH2

00H

C6H CCL3

00H

C7H CCH3

00H

C8H

T2CON

00H

T2PS

I3FR

I2FR

T2R1

T2R0

T2CM

T2I1

T2I0

CAH CRCL

00H

CBH CRCH

00H

CCH TL2

00H

CDH TH2

00H

D0H

PSW

00H

RS1

RS0

D8H

ADCON0 00H

CLK

ADEX

BSY

ADM

MX2

MX1

MX0

D9H ADDATH 00H

DAH ADDATL 00XX-

XXXXB

DBH P6

DCH ADCON1 0XXX-

X000B

ADCL

MX2

MX1

MX0

E0H

ACC

00H

E8H

00H

F0H

00H

F8H

FFH

1) X means that the value is undefined and the location is reserved
2) Bit-addressable special function registers

Table 3
Contents of the SFRs, SFRs in numeric order of their addresses (cont'd)

Addr Register Content

after
Reset

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Semiconductor Group

1997-10-01

C515A

Digital I/O Ports

The C515A allows for digital I/O on 48 lines grouped into 6 bidirectional 8-bit ports. Each port bit
consists of a latch, an output driver and an input buffer. Read and write accesses to the I/O ports P0
through P5 are performed via their corresponding special function registers P0 to P5.

The output drivers of port 0 and 2 and the input buffers of port 0 are also used for accessing external
memory. In this application, port 0 outputs the low byte of the external memory address, time-
multiplexed with the byte being written or read. Port 2 outputs the high byte of the external memory
address when the address is 16 bits wide. Otherwise, the port 2 pins continue emitting the P2 SFR
contents.

Analog Input Ports

Ports 6 is available as input port only and provides two functions. When used as digital inputs, the
corresponding SFR P6 contains the digital value applied to the port 6 lines. When used for analog
inputs the desired analog channel is selected by a three-bit field in SFR ADCON0. Of course, it
makes no sense to output a value to these input-only ports by writing to the SFR P6. This will have
no effect.

If a digital value is to be read, the voltage levels are to be held within the input voltage specifications
(

). Since P6 is not bit-addressable, all input lines of P6 are read at the same time by byte

instructions.

Nevertheless, it is possible to use port 6 simultaneously for analog and digital input. However, care
must be taken that all bits of P6 that have an undetermined value caused by their analog function
are masked.

C515A

Semiconductor Group

1997-10-01

Timer / Counter 0 and 1

Timer/Counter 0 and 1 can be used in four operating modes as listed in table 4:

In the "timer" function (C/T = `0') the register is incremented every machine cycle. Therefore the
count rate is

OSC

/12.

In the "counter" function the register is incremented in response to a 1-to-0 transition at its
corresponding external input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a
falling edge the max. count rate is

OSC

/24. External inputs INT0 and INT1 (P3.2, P3.3) can be

programmed to function as a gate to facilitate pulse width measurements. Figure 9 illustrates the
input clock logic.

Figure 9
Timer/Counter 0 and 1 Input Clock Logic

Table 4
Timer/Counter 0 and 1 Operating Modes

Mode

Description

TMOD

Input Clock

internal

external (max)

8-bit timer/counter with a
divide-by-32 prescaler

OSC

12x32

OSC

24x32

16-bit timer/counter

OSC

8-bit timer/counter with
8-bit autoreload

Timer/counter 0 used as one
8-bit timer/counter and one
8-bit timer
Timer 1 stops

OSC

/12

MCS01768

OSC

C/T

TMOD

Control

Timer 0/1
Input Clock

TCON

TR 0/1

Gate

TMOD

P3.4/T0
P3.5/T1
max

P3.2/INT0
P3.3/INT1

OSC

/24

Semiconductor Group

1997-10-01

C515A

Timer/Counter 2 with Compare/Capture/Reload

The timer 2 of the C515A provides additional compare/capture/reload features. which allow the
selection of the following operating modes:

Compare

: up to 4 PWM signals with 16-bit/500 ns resolution

Capture

: up to 4 high speed capture inputs with 500 ns resolution

Reload

: modulation of timer 2 cycle time

The block diagram in figure 10 shows the general configuration of timer 2 with the additional
compare/capture/reload registers. The I/O pins which can used for timer 2 control are located as
multifunctional port functions at port 1.

Figure 10
Timer 2 Block Diagram

MCB03205

Comparator

CCL3/CCH3

Capture

Input/

Output

Control

P1.0/
INT3/
CC0

CC1

INT4/

P1.1/

CC2

INT5/

P1.2/

CC3

INT6/

P1.2/

CCL2/CCH2

Comparator

CCL1/CCH1

Comparator

CRCL/CRCH

Comparator

Bit

16 Bit

OSC

÷ 12

÷ 24

OSC

T2PS

Sync.

P1.7/
T2

T2EX

P1.5/

Sync.

T2I1

T2I0

Timer 2

TH2

TL2

TF2

Reload

EXEN2

Reload

EXF2

Interrupt
Request

Compare

C515A

Semiconductor Group

1997-10-01

Timer 2 Operating Modes

The timer 2, which is a 16-bit-wide register, can operate as timer, event counter, or gated timer. A
roll-over of the count value in TL2/TH2 from all 1's to all 0's sets the timer overflow flag TF2 in SFR
IRCON, which can generate an interrupt. The bits in register T2CON are used to control the timer 2
operation.

Timer Mode: In timer function, the count rate is derived from the oscillator frequency. A prescaler
offers the possibility of selecting a count rate of 1/12 or 1/24 of the oscillator frequency.

Gated Timer Mode: In gated timer function, the external input pin T2 (P1.7) functions as a gate to
the input of timer 2. If T2 is high, the internal clock input is gated to the timer. T2 = 0 stops the
counting procedure. This facilitates pulse width measurements. The external gate signal is sampled
once every machine cycle.

Event Counter Mode: In the event counter function. the timer 2 is incremented in response to a
1-to-0 transition at its corresponding external input pin T2 (P1.7). In this function, the external input
is sampled every machine cycle. Since it takes two machine cycles (24 oscillator periods) to
recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. There are
no restrictions on the duty cycle of the external input signal, but to ensure that a given level is
sampled at least once before it changes, it must be held for at least one full machine cycle.

Reload of Timer 2: Two reload modes are selectable:
In mode 0, when timer 2 rolls over from all 1's to all 0's, it not only sets TF2 but also causes the
timer 2 registers to be loaded with the 16-bit value in the CRC register, which is preset by software.
In mode 1, a 16-bit reload from the CRC register is caused by a negative transition at the
corresponding input pin P1.5/T2EX. This transition will also set flag EXF2 if bit EXEN2 in SFR IEN1
has been set.

Semiconductor Group

1997-10-01

C515A

Timer 2 Compare Modes

The compare function of a timer/register combination operates as follows: the 16-bit value stored in
a compare or compare/capture register is compared with the contents of the timer register; if the
count value in the timer register matches the stored value, an appropriate output signal is generated
at a corresponding port pin and an interrupt can be generated.

Compare Mode 0

In compare mode 0, upon matching the timer and compare register contents, the output signal
changes from low to high. It goes back to a low level on timer overflow. As long as compare mode 0
is enabled, the appropriate output pin is controlled by the timer circuit only and writing to the port
will have no effect. Figure 11 shows a functional diagram of a port circuit when used in compare
mode 0. The port latch is directly controlled by the timer overflow and compare match signals. The
input line from the internal bus and the write-to-latch line of the port latch are disconnected when
compare mode 0 is enabled.

Figure 11
Port Latch in Compare Mode 0

MCS02661

Latch

Port

CLK

Port

Read Pin

Read Latch

Port Circuit

Internal
Bus

Latch

Write to

Compare Reg.

Compare Register

Circuit

Comparator

Timer Register

Timer Circuit

Compare
Match

Overflow

Timer

16 Bit

Bit

C515A

Semiconductor Group

1997-10-01

Compare Mode 1

If compare mode 1 is enabled and the software writes to the appropriate output latch at the port, the
new value will not appear at the output pin until the next compare match occurs. Thus, it can be
choosen whether the output signal has to make a new transition (1-to-0 or 0-to-1, depending on the
actual pin-level) or should keep its old value at the time when the timer value matches the stored
compare value.

In compare mode 1 (see figure 12) the port circuit consists of two separate latches. One latch
(which acts as a "shadow latch") can be written under software control, but its value will only be
transferred to the port latch (and thus to the port pin) when a compare match occurs.

Figure 12
Compare Function in Compare Mode 1

MCS02662

Latch

Port

CLK

Read Pin

CLK

Shadow

Latch

Read Latch

Port Circuit

Internal
Bus

Latch

Write to

Compare Reg.

Compare Register

Circuit

Comparator

Timer Register

Timer Circuit

Compare
Match

Port

16 Bit

Semiconductor Group

1997-10-01

C515A

Serial Interface (USART)

The serial port is full duplex and can operate in four modes (one synchronous mode, three
asynchronous modes) as illustrated in table 5. The possible baudrates can be calculated using the
formulas given in table 5.

For clarification some terms regarding the difference between "baud rate clock" and "baud rate"
should be mentioned. In the asynchronous modes the serial interfaces require a clock rate which is
16 times the baud rate for internal synchronization. Therefore, the baud rate generators/timers have
to provide a "baud rate clock" (output signal in figure 13 to the serial interface which - there divided
by 16 - results in the actual "baud rate". Further, the abbreviation f

OSC

refers to the oscillator

frequency (crystal or external clock operation).

The variable baud rates for modes 1 and 3 of the serial interface can be derived from either timer 1
or a dedicated baud rate generator (see figure 13).

Table 5
USART Operating Modes

Mode

SCON

Description

SM0

SM1

Shift register mode
Serial data enters and exits through R

D/ T

D outputs the shift

clock; 8-bit are transmitted/received (LSB first); fixed baud rate

8-bit UART, variable baud rate
10 bits are transmitted (through T

D) or received (at R

9-bit UART, fixed baud rate
11 bits are transmitted (through T

D) or received (at R

9-bit UART, variable baud rate
Like mode 2

Semiconductor Group

1997-10-01

C515A

10-Bit A/D Converter

The C515A provides an A/D converter with the following features:

8 multiplexed input channels (port 6), which can also be used as digital inputs
10-bit resolution
Single or continuous conversion mode
Internal or external start-of-conversion trigger capability
Interrupt request generation after each conversion
Using successive approximation conversion technique via a capacitor array
Built-in hidden calibration of offset and linearity errors

The A/D converter operates with a successive approximation technique and uses self calibration
mechanisms for reduction and compensation of offset and linearity errors. The externally applied
reference voltage range has to be held on a fixed value within the specifications. The main
functional blocks of the A/D converter are shown in figure 14.

Semiconductor Group

1997-10-01

C515A

Interrupt System

The C515A provides 12 interrupt sources with four priority levels. Five interrupts can be generated
by the on-chip peripherals (timer 0, timer 1, timer 2, A/D converter, and serial interface) and seven
interrupts may be triggered externally (P3.2/INT0, P3.3/INT1, P1.4/INT2, P1.0/INT3, P1.1/INT4,
P1.2/INT5, P1.3/INT6). The wake-up from power-down mode interrupt has a special functionality
which allows to exit from the software power-down mode by a short low pulse at pin P3.2/INT0.

This chapter shows the interrupt structure, the interrupt vectors and the interrupt related special
function registers. Figure 15 and 16 give a general overview of the interrupt sources and illustrate
the request and the control flags which are described in the next sections.

Semiconductor Group

1997-10-01

C515A

Fail Save Mechanisms

The C515A offers enhanced fail safe mechanisms, which allow an automatic recovery from
software upset or hardware failure:

a programmable watchdog timer (WDT), with variable time-out period from 512

s up to

approx. 1.1 s at 12 MHz (256

s up to approx. 0.65 s at 24 MHz)

an oscillator watchdog (OWD) which monitors the on-chip oscillator and forces the

microcontroller into reset state in case the on-chip oscillator fails; it also provides the clock for
a fast internal reset after power-on.

The watchdog timer in the C515A is a 15-bit timer, which is incremented by a count rate of

OSC

/24

up to

OSC

/384. The system clock of the C515A is divided by two prescalers, a divide-by-two and a

divide-by-16 prescaler. For programming of the watchdog timer overflow rate, the upper 7 bit of the
watchdog timer can be written. Figure 15 shows the block diagram of the watchdog timer unit.

Figure 17
Block Diagram of the Watchdog Timer

The watchdog timer can be started by software (bit SWDT) or by hardware through pin PE/SWD,
but it cannot be stopped during active mode of the C515A. If the software fails to refresh the running
watchdog timer an internal reset will be initiated on watchdog timer overflow. For refreshing of the
watchdog timer the content of the SFR WDTREL is transferred to the upper 7-bit of the watchdog
timer. The refresh sequence consists of two consecutive instructions which set the bits WDT and
SWDT each. The reset cause (external reset or reset caused by the watchdog) can be examined
by software (flag WDTS). It must be noted, however, that the watchdog timer is halted during the
idle mode and power down mode of the processor.

MCB03250

IP0 (A9 )

OSC

WDTS

WDTL

WDTH

/12

External HW Reset

External HW Power-Down

PE/SWD

Control Logic

IEN0 (A8 )H
IEN1 (B8 )H

WDT Reset-Request

WDTPSEL

WDTREL (86 )

WDT

SWDT

C515A

Semiconductor Group

1997-10-01

Oscillator Watchdog

The oscillator watchdog unit serves for four functions:

Monitoring of the on-chip oscillator's function

The watchdog supervises the on-chip oscillator's frequency; if it is lower than the frequency
of the auxiliary RC oscillator in the watchdog unit, the internal clock is supplied by the RC
oscillator and the device is brought into reset; if the failure condition disappears (i.e. the
on-chip oscillator has a higher frequency than the RC oscillator), the part executes a final
reset phase of typ. 1 ms in order to allow the oscillator to stabilize; then the oscillator watchdog
reset is released and the part starts program execution again.

Fast internal reset after power-on

The oscillator watchdog unit provides a clock supply for the reset before the on-chip oscillator
has started. The oscillator watchdog unit also works identically to the monitoring function.

Restart from the hardware power down mode.

If the hardware power down mode is terminated the oscillator watchdog has to control the
correct start-up of the on-chip oscillator and to restart the program. The oscillator watchdog
function is only part of the complete hardware power down sequence; however, the watchdog
works identically to the monitoring function.

Control of external wake-up from software power-down mode

When the software power-down mode is left by a low level at the P3.2/INT0 pin, the oscillator
watchdog unit assures that the microcontroller resumes operation (execution of the
power-down wake-up interrupt) with the nominal clock rate. In the power-down mode the RC
oscillator and the on-chip oscillator are stopped. Both oscillators are started again when
power-down mode is released. When the on-chip oscillator has a higher frequency than the
RC oscillator, the microcontroller starts operation after a final delay of typ. 1 ms in order to
allow the on-chip oscillator to stabilize.

C515A

Semiconductor Group

1997-10-01

Power Saving Modes

The C515A provides two basic power saving modes, the idle mode and the power down mode.
Additionally, a slow down mode is available. This power saving mode reduces the internal clock rate
in normal operating mode and it can be also used for further power reduction in idle mode.

Idle mode

The CPU is gated off from the oscillator. All peripherals are still provided with the clock and
are able to work. Idle mode is entered by software and can be left by an interrupt or reset.

Slow down mode

The controller keeps up the full operating functionality, but its normal clock frequency is
internally divided by 8. This slows down all parts of the controller, the CPU and all peripherals,
to 1/8th of their normal operating frequency and also reduces power consumption.

Software power down mode

The operation of the C515 is completely stopped and the oscillator is turned off. This mode is
used to save the contents of the internal RAM with a very low standby current. This power
down mode is entered by software and can be left by reset or by a short low pulse at pin P3.2/
INT0.

Hardware Power down mode

If pin HWPD gets active (low level) the part enters the hardware power down mode and starts
a complete internal reset sequence. Thereafter, both oscillators of the chip are stopped and
the port pins and several control lines enter a floating state.

In the power down mode of operation,

can be reduced to minimize power consumption. It must

be ensured, however, that

is not reduced before the power down mode is invoked, and that

is restored to its normal operating level, before the power down mode is terminated. Table 8 gives
a general overview of the entry and exit procedures of the power saving modes.

Semiconductor Group

1997-10-01

C515A

Table 8
Power Saving Modes Overview

Mode

Entering
2-Instruction
Example

Leaving by

Remarks

Idle mode

ORL PCON, #01H
ORL PCON, #20H

Occurrence of an
interrupt from a
peripheral unit

CPU clock is stopped;
CPU maintains their data;
peripheral units are active (if
enabled) and provided with
clock

Hardware Reset

Slow Down Mode

In normal mode:
ORL PCON,#10H

ANL PCON,#0EFH
or
Hardware Reset

Internal clock rate is reduced
to 1/8 of its nominal frequency

With idle mode:
ORL PCON,#01H
ORL PCON, #30H

Occurrence of an
interrupt from a
peripheral unit

CPU clock is stopped;
CPU maintains their data;
peripheral units are active (if
enabled) and provided with 1/8
of its nominal frequency

Hardware reset

Software
Power Down Mode

ORL PCON, #02H
ORL PCON, #40H

Hardware Reset

Oscillator is stopped;
contents of on-chip RAM and
SFR's are maintained;

Short low pulse at
pin P3.2/INT0

Hardware
Power Down Mode

HWPD = 0

HWPD = 1

Oscillator is stopped; internal
reset is executed;

C515A

Semiconductor Group

1997-10-01

Absolute Maximum Ratings

Ambient temperature under bias (

) ......................................................... 40 to + 125

Storage temperature (

stg

) .......................................................................... 65

C to 150

Voltage on

pins with respect to ground (

) ....................................... 0.5 V to 6.5 V

Voltage on any pin with respect to ground (

) ......................................... 0.5 V to

+0.5 V

Input current on any pin during overload condition..................................... 10 mA to 10 mA
Absolute sum of all input currents during overload condition ..................... I 100 mA I
Power dissipation of package ..................................................................... TBD

Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent

damage of the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for longer
periods may affect device reliability. During overload conditions (

) the

Voltage on

pins with respect to ground (

) must not exceed the values defined by the

absolute maximum ratings.

Semiconductor Group

1997-10-01

C515A

DC Characteristics

= 5 V + 10%, 15%;

= 0 V

= 0 to 70

for the SAB-C515A

= 40 to 85

for the SAF-C515A

= 40 to 110

for the SAH-C515A

= 40 to 125

for the SAK-C515A

Notes see next page

Parameter

Symbol

Limit Values

Unit

Test Condition

min.

max.

Input low voltage
Pins except EA,RESET,HWPD
EA pin
HWPD and RESET pins

IL1

IL2

0.5
0.5
0.5

0.2

0.1

0.2

0.3

0.2

+ 0.1

V
V
V

Input high voltage
pins except RESET, XTAL2 and
HWPD
XTAL2 pin
RESET and HWPD pin

IH1

IH2

0.2

+ 0.9

0.7

0.6

+ 0.5

V
V
V

Output low voltage
Ports 1, 2, 3, 4, 5
Port 0, ALE, PSEN

OL1

0.45
0.45

V
V

= 1.6 mA

= 3.2 mA

Output high voltage
Ports 1, 2, 3, 4, 5

Port 0 in external bus mode,
ALE, PSEN

OH1

2.4
0.9

V
V
V
V

= 10

800

= 80

Logic 0 input current
Ports 1, 2, 3, 4, 5

I N

0.45 V

Logical 0-to-1 transition current,
Ports 1, 2, 3, 4, 5

650

I N

2 V

Input leakage current
Port 0 and 6, EA, HWPD

0.45 <

I N

Input low current
to RESET for reset
XTAL2
PE/SWD

IL2

IL3

IL4

100
15
20

I N

0.45 V

I N

0.45 V

I N

0.45 V

Pin capacitance

= 1 MHz,

= 25

Overload current

8) 9)

C515A

Semiconductor Group

1997-10-01

Power Supply Current

Notes:

1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the

of ALE

and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these
pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise
pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a schmitt-trigger,
or use an address latch with a schmitt-trigger strobe input.

2) Capacitive loading on ports 0 and 2 may cause the

on ALE and PSEN to momentarily fall below the

0.9

specification when the address lines are stabilizing.

(software power-down mode) is measured under following conditions:

EA = RESET = Port 0 = Port 6 =

; XTAL1 = N.C.; XTAL2 =

; PE/SWD =

;

HWPD =

;

AGND

;

AREF

; all other pins are disconnected.

(hardware power-down mode): independent from any particular pin connection.

(active mode) is measured with:

XTAL2 driven with

CLCH

CHCL

= 5 ns ,

+ 0.5 V,

0.5 V; XTAL1 = N.C.;

EA = PE/SWD = Port 0 = Port 6 =

; HWPD =

;

RESET =

;

all other pins are disconnected.

would be slightly higher if a crystal oscillator is used (appr. 1 mA).

(idle mode) is measured with all output pins disconnected and with all peripherals disabled;

XTAL2 driven with

CLCH

CHCL

= 5 ns,

+ 0.5 V,

0.5 V; XTAL1 = N.C.;

RESET =

; HWPD = Port 0 = Port 6 =

; EA = PE/SWD =

; all other pins are disconnected;

(active mode with slow-down mode) is measured with all output pins disconnected and with all peripherals

disabled; XTAL2 driven with

CLCH

CHCL

= 5 ns,

+ 0.5 V,

0.5 V; XTAL1 = N.C.;

RESET =

; HWPD = Port 6 =

; EA = PE/SWD =

; all other pins are disconnected; the

microcontroller is put into slow-down mode by software;

(idle mode with slow-down mode) is measured with all output pins disconnected and with all peripherals

disabled; XTAL2 driven with

CLCH

CHCL

= 5 ns,

+ 0.5 V,

0.5 V; XTAL1 = N.C.;

RESET =

; HWPD = Port 6 =

; EA = PE/SWD =

; all other pins are disconnected;

the microcontroller is put into idle mode with slow-down mode enabled by software;

8) Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin

exceeds the specified range (i.e.

+ 0.5 V or

- 0.5 V). The supply voltage

and

must

remain within the specified limits. The absolute sum of input currents on all port pins may not exceed 50 mA.

9) Not 100% tested, guaranteed by design characterization

10)The typical

values are periodically measured at

= +25 °C and

= 5 V but not 100% tested.

11)The maximum

values are measured under worst case conditions (

= 0 °C or -40 °C and

= 5.5 V)

Parameter

Symbol

Limit Values

Unit Test Condition

typ.

10)

max.

11)

Active mode

18 MHz
24 MHz

16.9
21.7

23.1
29.4

mA
mA

Idle mode

18 MHz
24 MHz

8.5
11.0

12.1
15.0

mA
mA

Active mode with
slow-down enabled

18 MHz
24 MHz

5.6
6.6

8.0
9.6

mA
mA

Active mode with
slow-down enabled

18 MHz
24 MHz

3.0
3.3

4.1
4.7

mA
mA

Power-down mode

= 2

...

5.5 V

Semiconductor Group

1997-10-01

C515A

Figure 19
ICC Diagram

Note:

osc

is the oscillator frequency in MHz.

values are given in mA.

Table 9
Power Supply Current Calculation Formulas

Parameter

Symbol

Formula

Active mode

CC typ

CC max

0.79

OSC

+ 2.7

1.04

OSC

+ 4.4

Idle mode

CC typ

CC max

0.43

OSC

+ 0.7

0.48

OSC

+ 3.5

Active mode with
slow-down enabled

CC typ

CC max

0.17

OSC

+ 2.5

0.28

OSC

+ 2.9

Idle mode with
slow-down enabled

CC typ

CC max

0.06

OSC

+ 1.9

0.09

OSC

+ 2.5

OSC

MCD03252

MHz

Active Mode

Idle Mode

CC max

CC typ

Active + Slow Down Mode

Idle + Slow Down Mode

C515A

Semiconductor Group

1997-10-01

A/D Converter Characteristics

= 5 V + 10%, 15%;

= 0 V

= 0 to 70

for the SAB-C515A

= 40 to 85

for the SAF-C515A

= 40 to 110

for the SAH-C515A

= 40 to 125

for the SAK-C515A

4 V

AREF

+ 0.1 V;

0.1 V

AGND

+ 0.2 V

Notes see next page.

Clock calculation table:

Further timing conditions:

ADC

min = 500 ns

= 2 /

OSC

= 2

CLCL

Parameter

Symbol

Limit Values

Unit

Test Condition

min.

max.

Analog input voltage

AIN

AGND

AREF

Sample time

Prescaler

Conversion cycle time

ADCC

Prescaler

Total unadjusted error

LSB

+ 0.5 V

0.5 V

Internal resistance of
reference voltage source

AREF

ADC

/ 250

ADC

in [ns]

5) 6)

Internal resistance of
analog source

ASRC

/ 500

0.8

in [ns]

2) 6)

ADC input capacitance

AIN

Clock Prescaler
Ratio

ADCL

ADC

ADCC

Semiconductor Group

1997-10-01

C515A

Notes:

1) V

AIN

may exceed V

AGND

or V

AREF

up to the absolute maximum ratings. However, the conversion result in

these cases will be X000

or X3FF

, respectively.

2) During the sample time the input capacitance

AIN

can be charged/discharged by the external source. The

internal resistance of the analog source must allow the capacitance to reach their final voltage level within

After the end of the sample time

, changes of the analog input voltage have no effect on the conversion

result.

3) This parameter includes the sample time

, the time for determining the digital result and the time for the

calibration. Values for the conversion clock

ADC

depend on programming and can be taken from the table on

the previous page.

4) T

is tested at V

AREF

= 5.0 V, V

AGND

= 0 V, V

= 4.9 V. It is guaranteed by design characterization for all

other voltages within the defined voltage range.
If an overload condition occurs on maximum 2 not selected analog input pins and the absolute sum of input
overload currents on all analog input pins does not exceed 10 mA, an additional conversion error of 1/2 LSB
is permissible.

5) During the conversion the ADC's capacitance must be repeatedly charged or discharged. The internal

resistance of the reference source must allow the capacitance to reach their final voltage level within the
indicated time. The maximum internal resistance results from the programmed conversion timing.

6) Not 100% tested, but guaranteed by design characterization.

C515A

Semiconductor Group

1997-10-01

AC Characteristics (18 MHz)

= 5 V + 10%, 15%;

= 0 V

= 0 to 70

for the SAB-C515A

= 40 to 85

for the SAF-C515A

= 40 to 110

for the SAH-C515A

= 40 to 125

for the SAK-C515A

(

for port 0, ALE and PSEN outputs = 100 pF;

for all other outputs = 80 pF)

Program Memory Characteristics

Interfacing the C515A to devices with float times up to 48 ns is permissible. This limited bus contention will not
cause any damage to port 0 drivers.

Parameter

Symbol

Limit Values

Unit

18 MHz

Clock

Variable Clock

CLCL

= 3.5 MHz to 18 MHz

min.

max.

min.

max.

ALE pulse width

LHLL

CLCL

Address setup to ALE

AVLL

CLCL

Address hold after ALE

LLAX

CLCL

ALE low to valid instruction in

LLIV

122

CLCL

100

ALE to PSEN

LLPL

CLCL

PSEN pulse width

PLPH

132

CLCL

PSEN to valid instruction in

PLIV

CLCL

Input instruction hold after PSEN

PXIX

Input instruction float after PSEN

PXIZ

CLCL

Address valid after PSEN

PXAV

CLCL

Address to valid instr in

AVIV

180

CLCL

Address float to PSEN

AZPL

Semiconductor Group

1997-10-01

C515A

AC Characteristics (18 MHz, cont'd)

External Data Memory Characteristics

External Clock Drive Characteristics

Parameter

Symbol

Limit Values

Unit

18 MHz

Clock

Variable Clock

CLCL

= 3.5 MHz to 18 MHz

min.

max.

min.

max.

RD pulse width

RLRH

233

CLCL

100

WR pulse width

WLWH

233

CLCL

100

Address hold after ALE

LLAX2

CLCL

RD to valid data in

RLDV

128

CLCL

150

Data hold after RD

RHDX

Data float after RD

RHDZ

CLCL

ALE to valid data in

LLDV

294

CLCL

150

Address to valid data in

AVDV

335

CLCL

165

ALE to WR or RD

LLWL

117

217

CLCL

+ 50

Address valid to WR or RD

AVWL

CLCL

130

WR or RD high to ALE high

WHLH

CLCL

+ 40

Data valid to WR transition

QVWX

CLCL

Data setup before WR

QVWH

239

CLCL

150

Data hold after WR

WHQX

CLCL

Address float after RD

RLAZ

Parameter

Symbol

Limit Values

Unit

Variable Clock

Freq. = 3.5 MHz to 18 MHz

min.

max.

Oscillator period

CLCL

55.6

285.7

High time

CHCX

CLCL

CLCX

Low time

CLCX

CLCL

CHCX

Rise time

CLCH

Fall time

CHCL

C515A

Semiconductor Group

1997-10-01

AC Characteristics (24 MHz)

= 5 V + 10%, 15%;

= 0 V

= 0 to 70

for the SAB-C515A

= 40 to 85

for the SAF-C515A

= 40 to 110

for the SAH-C515A

(

for port 0, ALE and PSEN outputs = 100 pF;

for all other outputs = 80 pF)

Program Memory Characteristics

Interfacing the C515A to devices with float times up to 37 ns is permissible. This limited bus contention will not
cause any damage to port 0 drivers.

Parameter

Symbol

Limit Values

Unit

24 MHz

Clock

Variable Clock

CLCL

= 3.5 MHz to 24 MHz

min.

max.

min.

max.

ALE pulse width

LHLL

CLCL

Address setup to ALE

AVLL

CLCL

Address hold after ALE

LLAX

CLCL

ALE low to valid instruction in

LLIV

CLCL

ALE to PSEN

LLPL

CLCL

PSEN pulse width

PLPH

CLCL

PSEN to valid instruction in

PLIV

CLCL

Input instruction hold after PSEN

PXIX

Input instruction float after PSEN

PXIZ

CLCL

Address valid after PSEN

PXAV

CLCL

Address to valid instr in

AVIV

148

CLCL

Address float to PSEN

AZPL

Semiconductor Group

1997-10-01

C515A

AC Characteristics (24 MHz, cont'd)

External Data Memory Characteristics

External Clock Drive Characteristics

Parameter

Symbol

Limit Values

Unit

24 MHz

Clock

Variable Clock

CLCL

= 3.5 MHz to 24 MHz

min.

max.

min.

max.

RD pulse width

RLRH

180

CLCL

WR pulse width

WLWH

180

CLCL

Address hold after ALE

LLAX2

2 t

CLCL

RD to valid data in

RLDV

118

CLCL

Data hold after RD

RHDX

Data float after RD

RHDZ

CLCL

ALE to valid data in

LLDV

200

CLCL

133

Address to valid data in

AVDV

220

CLCL

155

ALE to WR or RD

LLWL

175

CLCL

+ 50

Address valid to WR or RD

AVWL

CLCL

WR or RD high to ALE high

WHLH

CLCL

+ 25

Data valid to WR transition

QVWX

CLCL

Data setup before WR

QVWH

170

CLCL

122

Data hold after WR

WHQX

CLCL

Address float after RD

RLAZ

Parameter

Symbol

Limit Values

Unit

Variable Clock

Freq. = 3.5 MHz to 24 MHz

min.

max.

Oscillator period

CLCL

41.7

285.7

High time

CHCX

CLCL

CLCX

Low time

CLCX

CLCL

CHCX

Rise time

CLCH

Fall time

CHCL

Semiconductor Group

1997-10-01

C515A

Figure 26
AC Testing: Input, Output Waveforms

Figure 27
AC Testing : Float Waveforms

Figure 28
Recommended Oscillator Circuits for Crystal Oscillator

AC Inputs during testing are driven at

- 0.5 V for a logic '1' and 0.45 V for a logic '0'.

Timing measurements are made at

IHmin

for a logic '1' and

ILmax

for a logic '0'.

0.45 V

0.2

-0.1

+0.9

0.2

Test Points

MCT00039

-0.5 V

For timing purposes a port pin is no longer floating when a 100 mV change from load voltage
occurs and begins to float when a 100 mV change from the loaded

level occurs.

20 mA

MCT00038

Load

-0.1 V

+0.1 V

Load

Timing Reference

Points

-0.1 V

+0.1 V

MCS03245

3.5 - 24

MHz

XTAL1

XTAL2

XTAL1

N.C.

External Oscillator
Signal

Crystal Oscillator Mode

Driving from External Source

Crystal Mode:

C = 20 pF 10 pF
(Incl. Stray Capacitance)

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