Semiconductor Group

Type

Ordering Code

Package

SDA 3302-5

Q67000-H5112

P-DIP-18-5

SDA 3302-5X

Q67000-H5111

P-DSO-20-1 (SMD)

SDA 3302-5X6

Q67000-H5110

P-DSO-16-1 (SMD)

SDA 3302-5X

Q67006-H5111

P-DSO-20-1 Tape & Reel (SMD)

SDA 3302-5X6

Q67006-H5110

P-DSO-16-1 Tape & Reel (SMD)

02.97

GHz PLL with

C Bus

and Four Chip Addresses

SDA 3302 Family

Bipolar IC

Preliminary Data

Features

1-chip system for MPU
control

C bus)

4 programmable chip addresses

Short pull-in time for quick channel
switch-over and optimized loop
stability

Charge pump output with switch
off option

Up to 3*) high current band switch
outputs (20 mA)

Up to 4*) output ports (5 mA)

*) depending on version

P-DIP-18-5

P-DSO-20-1

P-DSO-16-1

Semiconductor Group

Functional Description

Combined with a VCO (tuner) the SDA 3302 device, with four hardware-switched chip
addresses, forms a digitally programmable phase-locked loop for use in television sets with
PLL frequency-synthesis tuning.

The PLL permits precise crystal-controlled setting of the frequency of the tuner oscillators
between 16 and 1300 MHz in increments of 62.5 kHz. The tuning process is controlled by a
microprocessor via an

C bus. The crystal oscillator generates a sinusoidal signal suppressing

the higher-order harmonics, which reduces the moiré noise considerably.

Circuit Description

Tuning Section (refer to block diagram)

UHF/VHF

The tuner signal is capacitively coupled at the UHF/VHF input and
subsequently amplified. The reference input REF should be decoupled to
ground using a capacitor of low series inductance. The signal passes
through an asynchronous divider with a fixed ratio of

= 8, an adjustable

divider with ratio

= 256 through 32767 and is then compared in a digital

phase/frequency detector to a reference frequency

REF

of 7.8125 kHz. The

latter is derived from a balanced, low-impedance 4 MHz crystal oscillator

Q1, Q2

(pin Q1, Q2), whose output signal is divided by

= 512.

The phase detector has two outputs UP and DOWN that drive the two current
sources

+ and

of a charge pump. If the negative edge of the divided VCO

signal appears prior to the negative edge of the reference signal, the

current source pulses for the duration of the phase difference. In the reverse
case the

current source pulses.

PD, UD

When the two signals are in phase, the charge-pump output (PD) goes high-
impedance (PLL is locked). An active low-pass filter integrates the current
pulses to generate the tuning voltage for the VCO (internal amplifier an
external transistor at the UD output and an external RC circuitry). The
charge-pump output can also be set to high-impedance state when control
bit T0 = 1. Here it should be noted, however, that the tuning voltage can alter
over a long period in the high-impedance state as a result of self-discharge
in the peripheral circuitry. UD can be disconnected internally by the control
bit OS to enable external adjustments.

By means of a control bit 5I the pump current can be switched between two
values by software. This switchover permits alteration of the control
response of the PLL in the locked-in state. In this way different VCO gains in
the different TV bands can be compensated for example.

REF

SDA 3302 Family

Semiconductor Group

Circuit Description (cont'd)

P0-P2

The software-switched outputs (P0, P1, P2) can be used for direct band
selection (20-mA current output).

P4-P7

P4, P5, P6 and P7 are open-collector outputs for a variety of different
purposes. The test bit T1 = 1 switches the test signals

REF

(4 MHz/512) and

Cy (divided input signal) to P6 and P7.

CAS

Four different chip addresses can be set by appropriate connection of pin
CAS.

C-Bus Interface

SCL, SDA

Data are exchanged between the processor and the PLL on the

C bus. The

clock is produced by the processor (input SCL), while pin SDA works as an
input or output depending on the direction of the data (open collector;
external pullup resistor). Both inputs have hysteresis and a lowpass
characteristic, which enhances the noise immunity of the

C bus.

The data from the processor are applied to an

C bus controller and filed in

registers according to their function. When the bus is free, both lines are in
the marking state (SDA, SCL are high). Each telegram begins with a start
condition and ends with the stop condition. Start condition: SDA goes low
while SCL remains high; stop condition: SDA goes high while SCL remains
high. All further data exchanges occur while SCL is low and are accepted by
the controller with the positive clock edge.

For what follows, refer to the table of logic allocations.

All telegrams are transmitted byte by byte, followed by a ninth clock pulse,
during which the controller puts the SDA line on low (acknowledge condition).
The first byte consists of seven address bits, with which the processor
selects the PLL from a number of peripheral devices (chip select). The eighth
bit is always low. In the data portion of the telegram the first bit of the first or
third data byte determines whether a divider ratio or control information
follows. In each case the byte following the first byte must be of the same
data type (or a stop condition).

, GND

When the supply voltage is applied, a power-on reset circuit prevents the PLL
from putting the SDA line on low, which would block the bus.

SDA 3302 Family

Semiconductor Group

Circuit Description (cont'd)

Logic Allocations

Divider Ratio

= 16384

n14 + 8192

n13 + 4096

n12 + 2048

n11 + 1024

n10 + 512

n9 + 256

n8 +

+ 128

n7 + 64

n6 + 32

n5 + 16

n4 + 8

n3 + 4

n2 + 2

+ n0

Band Selection
P2-P0 = 1

Open-collector output is active.

Port Outputs
P7-P4 = 1

Open-collector output is active.

Pump Current Switchover
5I = 1

High current.

UD Disable

OS = 1

is disabled.

Test Mode
T1, T0 = 0,0

Normal mode

T1 = 1

P6 =

REF

; P7 = Cy

T0 = 1

Tristate charge pump PD is in high-impedance.

MSB

A = Acknowledge

Address byte

MA1

MA0

Prog. divider byte 1

n14

n13

n12

n11

n10

Prog. divider byte 2

Control info. byte 1

Control info. byte 2

SDA 3302 Family

Semiconductor Group

Circuit Description (cont'd)

Chip-Address Switching

Pulse Diagram

Telegram Examples

Start-Addr-DR1-DR2-CW1-CW2-Stop

Start

= start condition

Start-Addr-CW1-CW2-DR1-DR2-Stop

Addr

= address

Start-Addr-DR1-DR2-CW1-Stop

DR1

= divider ratio 1st byte

Start-Addr-CW1-CW2-DR1-Stop

DR2

= divider ratio 2nd byte

Start-Addr-DR1-DR2-Stop

CW1

= control word 1st byte

Start-Addr-CW1-CW2-Stop

CW2

= control word 2nd byte

Start-Addr-DR1-Stop

Stop

= stop condition

MA1

MA0

Voltage on CAS

(0-0.1)

open

(0.4-0.6)

(0.9-1)

SDA 3302 Family

Semiconductor Group

Pin Definitions and Functions (SDA 3302-5)

Pin No.

Symbol

Function

Active-filter input/charge-pump output

Crystal

SDA

Data input/output for

C bus

SCL

Clock input for

C bus

Port output (open collector)

CAS

Chip-address switchover

Port output (open collector)

Supply voltage

UHF/VHF

Signal input

REF

Amplifier reference input

GND

Ground

Output active filter

SDA 3302 Family

Semiconductor Group

Pin Definitions and Functions (SDA 3302-5X)

Pin No.

Symbol

Function

Active-filter input/charge-pump output

Crystal

N.C.

Not connected

SDA

Data input/output for

C bus

SCL

Clock input for

C bus

Port output (open collector)

N.C.

Not connected

Port output (open collector)

CAS

Chip-address switchover

Port output (open collector)

Supply voltage

UHF/VHF

Signal input

REF

Amplifier reference input

GND

Ground

Active-filter output

SDA 3302 Family

Semiconductor Group

Pin Definitions and Functions (SDA 3302-5X6)

Pin No.

Symbol

Function

Active-filter input/output pump output

Crystal

SDA

Data input/output for

C bus

SCL

Clock input for

C bus

Port output (open collector)

CAS

Chip-address switchover

Port output (open collector)

Supply voltage

UHF/VHF

Signal input

REF

Amplifier reference input

GND

Ground

Output active filter

SDA 3302 Family

Semiconductor Group

Pin Definitions and Functions, Reference List

SDA 3302
P-DIP-18-5
Pin No.

SDA 3302X
P-DSO-20-1
Pin No.

SDA 3302X6
P-DSO-16-1
Pin No.

Symbol

Function

Input active-filter input charge
pump output

Crystal

N.C.

Not connected

SDA

Data input/output for

C bus

SCL

Clock input for

C bus

Port output (open collector)

N.C.

Not connected

Port output (open collector)

CAS

Chip-address switchover

Port output (open collector)

Supply voltage

UHF/VHF

Signal input

REF

Amplifier reference input

GND

Ground

Output active filter

SDA 3302 Family

Semiconductor Group

2) Pin nos. refer to P-DIP-18 package

Absolute Maximum Ratings

= 25

Parameter

Symbol

Limit Values

Unit

Remarks

min.

max.

Supply voltage

0.3

Output PD

0.3

Crystal Q1

0.3

Crystal Q2

0.3

Bus input/output SDA

0.3

Bus input SCL

0.3

Port output P7, P6, P5, P4

6, 7, 8, 9

0.3

Chip-address switchover

0.3

Port output P2, P1, P0

11, 12, 13

0.3

open collector

Signal input UHF/VHF

0.3

for

= 0 V

Reference input REF

0.3

for

= 0 V

Output active filter UD

0.3

Bus output SDA

open collector

Port output P7, P6, P5, P4

6L, 7L, 8L, 9L

open collector

Port output P2, P1, P0

11L, 12L, 13L

open collector

Chip temperature

125

Total port output current

Storage temperature

stg

125

Thermal resistance (system-air)

thSA

K/W

SDA 3302 Family

Semiconductor Group

Characteristics

= 5 V;

= 25

Parameter

Symbol

Limit Values

Unit

Test Condition

Test
Circuit

min.

typ.

max.

Current
consumption

= 5 V

Crystal-oscillator
frequency

2, 3

3.99975 4.000 4.00025 MHz

series capaci-
tance 18 pF;

xtal

= 4 MHz

Oscillator level

(Voltage across
crystal)

2, 3

2.6

Vpp

Margin from 1st

and 2nd harmonic

Input Sensitivity UHF/VHF

27/10
27/10
27/10

3/315
3/315
3/315

= 70-500 MHz

= 1000 MHz

= 1100 MHz

2
2
2

Band-Select Outputs P0-P2 (switch with open collector)

Reserve current

13H

= 13.5 V

Residual voltage

13L

0.5

13H

= 20 mA

Port Outputs P4-P7 (switch with open collector)

Reserve current

= 13.5 V

Residual voltage

0.5

= 1.7 mA

Note: The sum of the currents in ports P0-P7 must not exceed 25 mA

Phase-Detector Output PD

Pump current

230

300

= HIGH;

= 2 V

Pump current

= LOW;

= 2 V

Output voltage

1.0

2.5

locked

1) Design note: no 100 % final inspection.

2) Pin nos. refer to P-DIP-18 package

3) dBm/mV

rms

into 50

SDA 3302 Family

Semiconductor Group

Output Active Filter UD (T0 = 1)

Output current

500

= 0.8 V;

= 90

Output voltage

100

= 0 V

Output voltage

500

OS = 1

Chip-Address Switchover

Input current

10H

= 5 V

Input current

 I

10H

= 0 V

Bus Inputs SCL, SDA

Input voltage

5.5
5.5

V
V

6
6

Input current

= 0 V

Output SDA (open collector)

Reverse current

= 5.5 V

Output voltage

0.4

= 3 mA

Edges SCL, SDA

Rise time

Fall time

0.3

Shift Clock SCL

Frequency

100

kHz

H-pulse width

L-pulse width

4.7

2) Pin nos. refer to P-DIP-18 package

Characteristics (cont'd)

= 5 V;

= 25

Parameter

Symbol

Limit Values

Unit

Test Condition

Test
Circuit

min.

typ.

max.

SDA 3302 Family

Semiconductor Group

Start

Setup time

SUSta

4.7

Hold time

HDSta

Stop

Setup time

SUsto

4.7

Bus free

BUF

4.7

Data Exchange

Setup time

SUDat

0.25

Hold time

HDDat

Input hysteresis

SCL, SDA

300

Lowpass cutoff

frequency
SCL, SDA

500

kHz

1) Design note: no 100 % final inspection.

Pin nos. refer to P-DIP-18 package

Characteristics (cont'd)

= 5 V;

= 25

Parameter

Symbol

Limit Values

Unit

Test Condition

Test
Circuit

min.

typ.

max.

SDA 3302 Family

Semiconductor Group

Application Circuit

Calculation of Loop Filter

Loop bandwidth

(

VCO

) / (

)

Attenuation:

= 0.5

= prescaler

= programmable divider

= pump current

VCO

= tuner slope

= loop filter

Example for channel 47:

= 8,

= 11520,

= 100

VCO

= 18.7 MHz/V,

= 22 k

= 180 nF,

= 336 Hz,

= 54 Hz,

= 0.67

Standard dimensioning:

1/5

Note: The high-impedance port outputs and CAS can be blocked against external noise with

a capacitor of 1 nF.

SDA 3302 Family

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SDA3302-5X