Edition 1998-02-01

This edition was realized using
the software system FrameMaker

Published by Siemens AG, Bereich
Halbleiter, Marketing-Kommunikation,
Balanstraße 73,
81541 München

Siemens AG 1998.

Attention please!

As far as patents or other rights of third
parties are concerned, liability is only
assumed for components, not for
applications, processes and circuits
implemented within components or
assemblies.

The information describes the type of
component and shall not be considered
as assured characteristics.

Terms of delivery and rights to change
design reserved.
For questions on technology, delivery
and prices please contact
the Semiconductor Group Offices in
Germany or the Siemens Companies and
Representatives worldwide
(see address list).

Due to technical requirements compo-
nents may contain dangerous substanc-
es. For information on the types in ques-
tion please contact your nearest
Siemens Office, Semiconductor Group.
Siemens AG is an approved CECC man-
ufacturer.

Packing

Please use the recycling operators
known to you. We can also help you get
in touch with your nearest sales office. By
agreement we will take packing material
back, if it is sorted. You must bear the
costs of transport.

For packing material that is returned to us
unsorted or which we are not obliged to
accept, we shall have to invoice you for
any costs incurred.

Components used in life-support de-
vices or systems must be expressly
authorized for such purpose!

Critical components

of the Semiconduc-

tor Group of Siemens AG, may only be
used in life-support devices or systems

with the express written approval of the
Semiconductor Group of Siemens AG.

1 A critical component is a component

used in a life-support device or system
whose failure can reasonably be
expected to cause the failure of that
life-support device or system, or to
affect its safety or effectiveness of that
device or system.

2 Life support devices or systems are

intended (a) to be implanted in the
human body, or (b) to support and/or
maintain and sustain human life. If
they fail, it is reasonable to assume
that the health of the user may be
endangered.

Data Classification

Maximum Ratings

Maximum ratings are absolute ratings; exceeding only one of these values may cause
irreversible damage to the integrated circuit.

Recommended Operating Conditions

Under this conditions the functions given in the circuit description are fulfilled. Nominal
conditions specify mean values expected over the production spread and are the
proposed values for interface and application. If not stated otherwise, nominal values will
apply at

=25°C and the nominal supply voltage.

Characteristics

The listed characteristics are ensured over the operating range of the integrated circuit.

Edition 1998-02-01

Published by Siemens AG, Semiconductor Group
Copyright

Terms of delivery and right to change design reserved.

SDA 9361
Revision History:

Current Version: 1998-02-01

Previous Version:

1997-04-07

Page
(in previous
Version)

Page
(in current
Version)

Subjects (major changes since last revision)

Setup time of input HSYNC (CLEXT=1) changed from 6 ns to 4 ns

Nom. average and max. stand-by current specified

Specification of charge current pump of PLL pin LF is unnecessary

SDA 9361

Table of Contents

Page

Semiconductor Group

1998-02-01

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.2

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.3

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.4

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.5

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

System Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.1

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.2

Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.3

Reset Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.4

Frequency Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.5

I²C-Bus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.5.1

I²C-Bus Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.5.2

I²C-Bus Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.5.3

I²C-Bus Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.5.4

Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.5.5

Explanation of Some Control Items . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.1

Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.2

Characteristics (Assuming Recommended Operating Conditions) . . . . . . . 37

Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

5.1

VD- Output Voltage, 4/3-CRT and 16/9-Source . . . . . . . . . . . . . . . . . . . . . . 41

5.2

Timing Diagram of SCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

5.3

Power On/Off Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

5.4

Standby Mode, RESN Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

5.5

Function of H,V Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

P-MQFP-44-2

Semiconductor Group

1998-02-01

DDC-PLUS-Deflection Controller

SDA 9361

MOS

Type

Ordering Code

Package

SDA 9361

Q67107-H5167-A703

P-MQFP-44-2

Overview

1.1

Features

· Deflection - Protection - 16:9 / 4:3

· No external clock needed

PLL and

PLL on chip

C-Bus alignment of all deflection parameters

· All EW-, V- and H- functions

· PW EHT compensation

· PH EHT compensation

· Compensation of H-phase deviation (e.g. caused by white bar)

· Upper/lower EW-corner correction separately adjustable

· V-angle correction: Vertical frequent linear modulation of H-phase

· V-bow correction: Vertical frequent parabolic modulation of H-phase

· Three reduced V-scan modes (75 %, 66 %, 50 % V-size) adjustable by only 2 Bits

· H-frequent PWM output signal for general purpose

· H- and V-blanking time adjustable

· Partial overscan adjustable to hide the cut off control measuring lines in the

reducedscan modes

· Stop/start of vertical deflection adjustable to fill out the 16/9 screen with different

letterbox formats without annoying overscan

· Control signal SCAN as reference for vertical positioning of OSD, PIP etc.

· Vertical noise reduction with memory

· Standard and doubled line frequencies for NTSC and PAL, MUSE standard,

ATV standard, HDTV standard

· Self adaptation of V-frequency/number of lines per field between 192 and 680 for each

possible line frequency

· Protection against EHT run away (X-rays protection)

SDA 9361

Semiconductor Group

1998-02-01

· Protection against missing V-deflection (CRT-protection)

· Selectable softstart of the H-output stage

· Clock generation on chip

· P-MQFP-44-2 package

· 5 V supply voltage

1.2

General Description

The SDA 9361 is a highly integrated deflection controller for CTV receivers with standard
or doubled line and field frequencies. It controls among others an horizontal driver circuit
for a flyback line output stage, a DC coupled vertical saw-tooth output stage and an east/
west raster correction circuit. All adjustable output parameters are

C Bus controlled.

Inputs are HSYNC and VSYNC. The HSYNC signal is the reference for the internal clock
system which includes the

1 and

2 control loops.

1.3

Pin Configuration

Figure 1

UEP10278

HSYNC

1 2 3 4 5 6 7 8 9 10

32 31 30 29 28 27 26 25 24 23

SELFH1_2

CLKI

SDAT

DD(D)

SS(D)

SCLK

SCAN

RESN

SCP

E/W

DD(A2)

REFP

REFN

SSA(1)

ABL
D/A

DDA(1)

HPROT

CLEXT

FH1_2

TEST

PWM

REFH

REFL

SS(A2)

DD(A3)

REFC

SS(A3)

DD(D)

SS(D)

SSD

SS(A4)

DD(A4)

VOFFD

VPROT

VD+

VD-

VSYNC

SDA 9361

Semiconductor Group

1998-02-01

1.4

Pin Description

Pin No. Symbol

Type

Description

CLKI

I/TTL

Input for external clock

Reference oscillator input, crystal

Reference oscillator output, crystal

SDAT

C-Bus data

SCLK

C-Bus clock

RESN

I/TTL

Reset input, active low

SCAN

Q/TTL

Control signal for vertical positioning of OSD, PIP etc.

SCP

Blanking signal with H- and color burst component
(V-component selectable by

C Bus)

DD(D)

Digital supply

SS(D)

Digital ground

VPROT

Watching external V-output stage (input is the V-saw-
tooth from feedback resistor)

HPROT

Watching EHT (input is e.g. H-flyback)

DD(A1)

Analog supply

D/A

Output of an

C Bus controlled DC voltage

ABL

Input for a beam current dependent signal for
stabilization of width, height and H-phase

SS(A1)

Analog ground

REFN

Ground for

REFP

REFH

REFL

REFP

Reference voltage for IBEAM ADC, DAC, HPROT /
VPROT thresholds

DD(A2)

Analog supply

E/W

Control signal output for east/west raster correction

VD+

Control signal output for DC coupled V-output stage

VD-

Like VD+

SS(A2)

Analog ground

REFL

Reference voltages for E/W-DAC, V-DAC

REFH

REFL

Line flyback for H-delay compensation

PWM

Q/TTL

Control signal output

SDA 9361

Semiconductor Group

1998-02-01

1.4

Pin Description

(cont'd)

The external clock mode can not be used with 33.75 kHz and 35 kHz line frequency.

Pin No. Symbol

Type

Description

VSYNC

I/TTL

V-sync input

Control signal output for H driver stage

TEST

I/TTL

Switching normal operation (TEST = L) and test mode
(TEST = H: pins 7, 27, 31, 32, 33, 40, 44 are additional
test pins)

FH1_2

I/TTL

Switching between 1F

mode (L) and 2F

mode (H)

(Pin SELFH1_2 = 0)

CLEXT

I/TTL

Switching between internal (L) and external clock (H)

SELFH1_2 I/TTL

Selection of switching between 1F

mode and 2F

mode
SELFH1_2 = 0:1F

/2F

selected via pin FH1_2

SELFH1_2 = 1:1F

/2F

selected via

C-Bus register 00

, Bit D5

DD(A3)

Analog supply

HSYNC

HSYNC input (CLEXT = 1: TTL; CLEXT = 0: analog)

REFC

Reference voltage for sync ADC

SS(A3)

Analog ground

DD(D)

Digital supply

SS(D)

Digital ground

SSD

I/TTL

Disables softstart

SS(A4)

Analog ground

PLL loop filter

DD(A4)

Analog supply

VOFFD

I/TTL

Defines default value of VOFF-Bit
(

C-Bus register 00

, Bit D7)

SDA 9361

Semiconductor Group

1998-02-01

System Description

2.1

Functional Description

The main input signals are HSYNC with standard or doubled horizontal frequency and
VSYNC with vertical frequencies of 50/100 Hz or 60/120 Hz.

The VSYNC is processed in a noise reduction circuit to enable synchronization by worse
transmission too.

The output signals control the horizontal as well as the vertical deflection stages and the
east/west raster correction circuit.

The H-output signal HD compensates the delays of the line output stage and its phase
can be modulated vertical frequent to remove horizontal distortions of vertical raster lines
(V-Bow, V-Angle). Time reference is the middle of the front and back edge of the line
flyback pulse. A positive HD pulse switches off the line output transistor. Maximal H-shift
is about 4.5

s (for 1F

) or 2.25

s (for 2F

Picture tubes with 4:3 or 16:9 aspect ratio can be used by adapting the raster to the
aspect ratio of the source signal.

The V-output saw-tooth signals VD- and VD+ controls a DC coupled output stage and
can be disabled. Suitable blanking signals are delivered by the IC.

The east/west output signal E/W is a vertical frequent parabola of 4th order, enabling an
additional corner correction, separately for the upper and lower part.

The pulse width modulated horizontal frequent output signal PWM is for optional use. It
can be modulated between 1 and 215 steps. The step width is 4

/864.

The output D/A delivers a variable DC signal for general purpose.

The picture width and picture height compensation (PW/PH Comp) processes the beam
current dependent input signal ABL with effect to the outputs E/W and VD to keep width
and height constant and independent of brightness.

The alignment parameter Horizontal Shift Compensation enables to adjust the influence
of the input signal ABL on the horizontal phase.

The selectable start up circuit controls the energy supply of the H-output stage during the
receiver's run up time by smooth decreasing the line output transistors switching
frequency down to the normal operating value (softstart). HD starts with about double the
line frequency and converges within 85 ms to its final value. The high time is kept
constant.The normal operating pulse ratio H/L is 45/55.

The protection circuit watches an EHT reference and the saw-tooth of the vertical output
stage. H-output stage is switched off if the EHT succeeds a defined threshold or if the
V-deflection fails (refer to page 46).

HPROT:

Input

< V2

Continuous blanking

> V1

HD disabled

< V1

Operating range

SDA 9361

Semiconductor Group

1998-02-01

VPROT:

Vertical saw-tooth voltage

< V1 in first half of V-period or

> V2 in second half: HD disabled

The pin SCP delivers the composite blanking signal SCP. It contains burst (

), H-

blanking HBL (

HBL

) and selectable V-blanking (control bit SSC). The phase and width

of the H-blanking period can be varied by

C Bus. For the timing following settings are

possible:

BD = 1

= 0

BD = 0, BSE = 0 (default value)

HBL

(H-flyback time)

BD = 0, BSE = 1(alignment range)

HBL

= (4

H-blanking-time + 1) / CLL

DBL

= (H-shift + 4

H-blanking-phase

-2

H-blanking-time + 43) / CLL

SSC = 0

VBL

during V-blanking period

SSC = 1

is always

HBL

Figure 3

BG-pulse width

54 / CLL

Delay to HSYNC

if CLEXT = L-level: (76-4

Internal-H-sync-phase) / CLL

if CLEXT = H-level:

(38-4

Internal-H-sync-phase) / CLL

UED10260

Input Signal
HSYNC

DBL

OHBL

SDA 9361

Semiconductor Group

1998-02-01

2.2

Circuit Description

The HSYNC is reference for a numeric PLL. This PLL generates a clock which is phase
locked to the incoming horizontal sync pulse and exactly 864 times faster then the
horizontal frequency. In order to lock the internal frequency to the external sync signal
positive horizontal sync pulses are required (see figure 4).

Figure 4
Incoming Signal HSYNC (CLEXT = 0)

Pulse width

for

C-Bus Bit 'HSWID' = 0:

s ... 6.1

low FH-range

1.5

s ... 3.1

high FH-range

Pulse width

for

C-Bus Bit 'HSWID' = 1:

s ... 8.8

low FH-range

1.5

s ... 4.0

high FH-range

Rise time

:100 ns minimum (CLEXT = 0)

The described input signal is first applied to an A/D converter. Conversion takes place
with 6 Bits and a nominal frequency of 27 MHz. The digital PLL uses a low pass filter to
obtain defined slopes for further measurements (PAL/NTSC applications). In addition
the actual high and low level of the signal as well as a threshold value is evaluated and
used to calculate the phase error between internal clock and external horizontal sync

UED10279

HSmax

HSmin

HSpp

SDA 9361

Semiconductor Group

1998-02-01

pulse. By means of digital PI filtering an increment is gained from this. The PI filter can
be set by the

C-Bus VCR bit so that the lock-in behavior of the PLL is optimal in relation

to either the TV or VCR mode. Moreover it is possible to adapt the nominal frequency by
means of 5

C-Bus bits (INCR4..INCR0) to different horizontal frequencies. An

additional bus bit GENMOD offers the possibility to use the PLL as a frequency
generator which frequency is controlled by the INCR bits.

Once an increment has been obtained, either from the PI-filter or the

C Bus, it can be

used to operate the Digital Timing Oscillator. The DTO generates a saw-tooth with a
frequency that is proportional to the increment. The saw-tooth is converted into a
sinusoidal clock signal by means of sin ROM's and D/A converters and applied to an
analog PLL which multiplies the frequency by 2 or 4 (depends on mode 1F

or 2F

; for

detailed explanation see pinning and

C-Bus description) and minimizes residual jitter.

In this manner the required line locked clock is provided to operate the other functional
parts of the circuit. If no HSYNC is applied to pin 35 the system holds its momentary
frequency for 2040 lines and following resets the PLL to its nominal frequency. The
status bit CON indicates the lock state of the PLL.
The system also provides a stable HS-pulse for internal use. The phase between this
internal pulse and the external HSYNC is adjustable via

C-Bus bits HPHASE. It can be

shifted over the range of one TV line.
An external clock (CLKI) can be provided by pin selection (CLEXT = H). The clock
frequency has to be 864

HSYNC

The external clock mode can not be used with

33.75 kHz and 35 kHz line frequency.

For effective noise suppression the VSYNC has to pass a window at first and is then
processed in a flywheel logic. The window allows a VSYNC pulse only after a minimum
number of lines from its predecessor and sets an artificial one after a maximum number
of lines. The number of H-periods between two subsequent VSYNCs is stored and
determines (after several checks) the following V-periods (internal synchronization). If
incoincidence is detected between internal and external VSYNC, the system switches
after a hysteresis of a defined number of V-periods to external synchronization and the
checks are repeated.

Values which influence shape and amplitude of the output signals are transmitted as
reduced binary values to the SDA 9361 via

C Bus. A CPU which is designed for speed

reasons in a pipe line structure calculates in consideration of feedback signals (e.g.ABL)
values which exactly represent the output signals. These values control after D/A
conversion the external deflection and raster correction circuits.

The CPU firmware is stored in an internal ROM.

SDA 9361

Semiconductor Group

1998-02-01

2.3

Reset Modes

The circuit is completely reset at power-on/off (timing diagram see figure 11) or if the
pin RESN has L-level (timing diagram see figure 12). During standby operation some
parts of the circuit are not affected (timing diagram see figure 12):

Note: Power-On-Reset and RESN = Low state are deactivated after ca. 32 cycles of the

X1/X2 oscillator clock and ca. 42 cycles of the CLL clock.
Standby state is deactivated after ca. 42 cycles of the CLL clock.

Can only be read after Power-On-Reset is finished

Power-On-Reset

External Reset
(pin RESN = Low)

Standby Mode
(

C Bit STDBY = 1)

HD output

Low

Active

H-protection

Inactive

V-protection

Inactive

C interface (SDA,

SCL)

Tristate

Ready

C register

...1C

, 1F

Set to default values Set to default values Set to default values

C register 00

, 1E

, 44

...48

Set to default values Set to default values Not affected

Status Bit PONRES

Set to 1

Not affected

REFP

REFH

REFL

Not affected

Inactive

CPU

Inactive

SDA 9361

Semiconductor Group

1998-02-01

2.4

Frequency Ranges

The allowed deviation of all input line frequencies is max. ± 4.5 %.

number of lines per frame

interlaced

NI:

non interlaced

If NSA = 0 (subaddress 01

/D5

) number of lines per field is selfadaptable between 192

and 680 for each specified H-frequency.

Only with internal clock generation

15.625 kHz

50 Hz

625 I

15.75 kHz

60 Hz

525 I

31.25 kHz

50 Hz
100 Hz

625 NI / 1250I
625 I

31.5 kHz

60 Hz
70 Hz
120 Hz

525 NI / 1050 I
449 NI
525 I

32.4 kHz

60 Hz

1080 I

33.75 kHz

60 Hz

1125 I

35 kHz

66.7 Hz

525 NI

SDA 9361

Semiconductor Group

1998-02-01

2.5.3

C-Bus Commands

see 2.5.5: Explanation of some control items

Control item

Sub

add

r
. D7 D6 D5 D4 D3 D2 D1 D0 Allowed

Range

Effective

Range

Can be

Disabled

by Bit

Default

Value if

Disabled

Unit

Deflection control 0

see below

Deflection control 1

see below

Vertical shift

B7 B6 B5 B4 B3 B2 B1 B0 -128..127 -128..127

Vertical size

B7 B6 B5 B4 B3 B2 B1 B0 -128..127 -128..127

Vertical linearity

B7 B6 B5 B4 B3 B2 B1 B0 -128..127 -128..127

Vertical S-correction

B7 B6 B5 B4 B3 B2 B1 B0 -128..127 -128..127

Vertical EHT
compensation

B7 B6 B5 B4 B3 B2 B1 B0

0..255

Horizontal size

B7 B6 B5 B4 B3 B2 B1 B0 -128..127 -128..127

Pin phase

B7 B6 B5 B4 B3 B2 B1 B0 -128..127 -128..127

Pin amp

B7 B6 B5 B4 B3 B2 B1 B0 -128..127 -128..127

Upper corner pin
correction

B7 B6 B5 B4 B3 B2 B1 B0 -128..127 -128..127

Lower corner pin
correction

B7 B6 B5 B4 B3 B2 B1 B0 -128..127 -128..127

Horizontal EHT
compensation

B7 B6 B5 B4 B3 B2 B1 B0

0..255

Horizontal shift

B6 B5 B4 B3 B2 B1 B0 X

-64..63

1/CLL

Vertical angle

B7 B6 B5 B4 B3 B2 B1 B0 -128..127 -128..127

Vertical bow

B7 B6 B5 B4 B3 B2 B1 B0 -128..127 -128..127

PWM start

B7 B6 B5 B4 B3 B2 B1 B0

0..255

0..215

4/CLL

D/A

B5 B4 B3 B2 B1 B0 X

-32..31

Vertical blanking time

X B6 B5 B4 B3 B2 B1 B0

0..127

BSE = 0

lines

Horizontal blanking time 13

B5 B4 B3 B2 B1 B0

0..63

BSE = 0 H-flyback

4/CLL

Start vertical scan

B7 B6 B5 B4 B3 B2 B1 B0 -128..127

SSE = 0

line

Horizontal blanking
phase

B5 B4 B3 B2 B1 B0

-32..31

4/CLL

Vertical scan width 0

B9 B8

0..+3

STE = 0

256 lines

Vertical scan width 1

B7 B6 B5 B4 B3 B2 B1 B0

0..255

STE = 0

lines

Guard band

B5 B4 B3 B2 B1 B0

0..63

GBE = 0

half lines

Start reduced scan

B5 B4 B3 B2 B1 B0

0..63

0, 2..63

SRSE =

line

Vertical sync control

see below

Min. No. of lines / field

B7 B6 B5 B4 B3 B2 B1 B0

0..255

2 lines

Max. No. of lines / field

B7 B6 B5 B4 B3 B2 B1 B0

0..255

2 lines

AFC EHT
compensation

B5 B4 B3 B2 B1 B0 X

-32..31

Internal PLL control

see below

Internal H-sync phase

B7 B6 B5 B4 B3 B2 B1 B0 -128..127 -96..119

4/CLL

PWM width

B7 B6 B5 B4 B3 B2 B1 B0

0..255

0..215

PWM

width=0

4/CLL

Universal register 1

see below

Universal register 3

see below

Internal voltage Ref
control

see below

SDA 9361

Semiconductor Group

1998-02-01

a) The effective range for Vertical Blanking Time:

16 ... 127 (absolute value)

if STE = 0

0 ... 127 (offset value)

if STE = 1.

b) The "default value if disabled" for Vertical Blanking Time:

21 (absolute value)if STE = 0

8 (offset value)if STE = 1.

c) The effective range for Start Vertical Scan:

2 ... 127 (absolute value)

if STE = 0
if STE = 1 and NSA = 1

-128 ... 127 (offset value)

if STE = 1 and NSA = 0.

d) The effective range for Vertical Scan (total width: 10 Bit): 160 ... 684 lines.

e) The "default value if disabled" for Vertical Scan equals the number of lines of the
source signal reduced by the control value for Start Vertical Scan. (E.g.: input signal:
262 lines per field; Start vertical scan = 8 lines; then (if SSE = 1, STE = 0) vertical
scan = 262 - 8 = 254 lines.

At power on the RAM containing the control items is cleared. Therefore all data are zero
by default (if not otherwise defined) before transferring individual values via

C Bus.

Allowed values out of the effective range are limited, e. g. Vertical blanking time = 3 is
limited to 16 if STE = 0 (that means a minimum of 16 lines is blanked).
There are five bits (SRSE, BSE, SSE, STE, GBE) in the deflection control byte 1 for
disabling some control items. If one of these bits is "0", the value of the corresponding
control item will be ignored and replaced by the value "default value if disabled" in the
table above.

2.5.4

Detailed Description

The Deflection Control Byte 0 includes the following bits:

VOFF:

Vertical off
0:

normal vertical output due to control items

vertical saw-tooth is switched off,
vertical protection is disabled

Default value depends on pin 44 (VOFFD)
VOFFD = Low: 0
VOFFD = High: 1

VOFF

STDBY

2FH

RABL

VR1

VR0

HDE

SDA 9361

Semiconductor Group

1998-02-01

STDBY:

Stand-by mode
0:

normal operation

stand-by mode (all internal clocks are disabled)

2FH:

Setting of line frequency
0:

low range of line frequency (14900 Hz ... 17650 Hz)

high range of line frequency (29800 Hz ... 35300 Hz)

Note: this bit is don't care if pin SELFH1_2 has L-level

BD:

Blanking disable
0:

horizontal and vertical blanking enabled

horizontal and vertical blanking disabled

RABL:

ABL input range
0:

2 V ... 3 V

0 V ... 4 V

VR1 ... VR0:

Reduction of the vertical size
00: 100 % V-size

(16:9 source on 16:9 display)

01: 75 % V-size

(16:9 source on 4:3 display)

10: 66 % V-size

(two 4:3 sources on 16:9 display)

11: 50 % V-size

(two 16:9 sources on 16:9 display)

HDE:

HD enable
0:

line is switched off (HD disabled, that is L-level)

line is switched on (HD enabled)

Default value depends on pin 40 (SSD)
SSD = Low: 0
SSD = High: 1

The Deflection Control Byte 1 includes the following bits:

NSA:

No self adaptation
0:

self adaptation on

self adaptation off

NSA

STE

GBE

SRSE

SSE

BSE

SDA 9361

Semiconductor Group

1998-02-01

STE:

Scan time enable
0:

control items for vertical scan width 0 and width 1 are disabled

control items for vertical scan width 0 and width 1 are enabled

GBE:

Guard band enable
0:

control item for guard band is disabled

control item for guard band is enabled

SRSE:

Start reduced scan enable
0:

control item for start reduced scan is disabled

control item for start reduced scan is enabled

SSE:

Start scan enable
0:

control item for start vertical scan is disabled

control item for start vertical scan is enabled

BSE:

Blanking select enable
0:

control items for blanking times are disabled

control items for blanking times are enabled

The Vertical Sync Control Byte includes the following bits:

SSC:

Sandcastle without VBL
0:

output SCP with VBL component

output SCP without VBL component

NR:

Noise reduction
0:

no noise reduction of the vertical sync

noise reduction of the vertical sync

NI:

Non interlace
0:

interlace depends on source

no interlace

SSC

NL2

NL1

NL0

SDA 9361

Semiconductor Group

1998-02-01

NL2 ... NL0:

Number of lines per field when NR = 1 and no vertical sync
at the input is detected

The Internal PLL Control Byte includes the following bits:

HSWID:

Maximum width of HSYNC
0:

6.1

for low FH-range

3.1

for high FH-range

8.8

for low FH-range

4.0

for high FH-range

GENMOD:

Clock generator mode
0:

normal PLL mode

generator mode (fixed frequency output, controlled by INCR..)

VCR:

PLL filter optimized for
0:

TV mode

VCR mode

INCR4 ... 0:

Nominal PLL output frequency
for low FH-range:

INCR = INT((FH

110592) / FQ - 64.625)

for high FH-range:

INCR = INT((FH

55296) / FQ - 64.625)

(for typical values see table below)

NL2

NL1

NL0

Number of Lines per Field

262.5

312.5

525

562.5

625

HSWID

GENMOD

VCR

INCR4

INCR3

INCR2

INCR1

INCR0

SDA 9361

Semiconductor Group

1998-02-01

specified range for:
GENMOD = 0:

INCR

GENMOD = 1:

INCR

(FQ = 24.576 MHz)

Default value: INCR = 6

Warning:
1)A change of INCR or 2FH causes spontaneous changes of the generated clock

frequency greater than the specified 4.5 %.
Switching from PLL mode to Generator mode (GENMOD) with constant INCR
values does not result in exceeding the specified frequency deviation range.

2)If pin SSD has H-level the output signal HD starts immediately after power on. In

this case the starting horizontal frequency is either 15.75 kHz (if SELFH1_2 has
H-level or if SELFH1_2 and FH1_2 have L-level) or 31.5 kHz (if SELFH1_2 has
L-level and FH1_2 H-level). Starting with Muse or Macintosh standard requires
L-level at SSD so that INCR can be changed before enabling HD with HDE = 1.

3)Using external clock at pin 1, CLKI, (pin 32, CLEXT = 1): no internal protection

against missing clock pulses is provided.

4)In order to guarantee error free operation of the build in soft start circuit the input

frequency has to be inside the lock range of the PLL (+/-4.5 % of standard input
frequency)

Application

FH[Hz]

INCR

PAL

15625

NTSC

15750

PAL (100 Hz)

31250

NTSC (120 Hz)

31500

ATV

32400

MUSE

33750

Macintosh

35000

SDA 9361

Semiconductor Group

1998-02-01

The Universal Register 1 (Subaddress 45

) includes the following bit:

NOISYVCR:

Handling of noisy input signals in VCR mode
0:

normal handling

improved handling

Note: this bit is don't care if bit VCR = 0 (TV mode)

The Universal Register 3 (Subaddress 47

) includes the following bits:

KILL_ZIP:

Top flutter suppression
0:

no top flutter suppression

1: top

flutter

suppression

(phase jumps max.

s for low FH-range

rsp. max.

s for high FH-range)

TC_3RD:

Third time constant
0:

slow VCR time constant

fast VCR time constant

Note: this bit is don't care if bit VCR = 0 (TV mode)

The Internal Voltage Ref. Control Byte includes the following bits:

BANDG4 ...

Adjustment of internal bandgap reference

BANDG0:

10000: Reference Output voltage min
:
01111: Reference Output voltage max
Typical adjustment range is 0.5 V.

BANDGOFF: Bandgap Off

REFH

REFL

derived internally from

REFP

NOISY

VCR

KILL_ZIP TC_3RD

BANDG4 BANDG3 BANDG2 BANDG1 BANDG0

BANDG

OFF

BANDG4

OFF

SDA 9361

Semiconductor Group

1998-02-01

external references on

REFP

REFH

REFL

have to be applied

(in this case BANDG4OFF must be = 1)

BANDG4OFF: Bandgap 4 V Off

internal bandgap reference is used for

REFP

external reference on

REFP

(4 V) has to be applied

The Status Byte includes the following bits:

HPON:

protection on
0:

normal operation of the line output stage

high level on input HPROT has switched off the line

VPON:

V-protection on
0:

normal operation of the vertical output stage

incorrect signal on input VPROT has switched off the line

CON:

Coincidence not
0:

H-coincidence detected

no H-coincidence detected

PONRES:

Power-On-Reset
0:

after bus master has read the status byte

after each detected reset

Note: PONRES is reset after this byte has been read.

2.5.5

Explanation of Some Control Items

D/A

This item controls directly a 6 Bit D/A Converter at the output D/A that can be used for
general purpose.

Start Vertical Scan

If enabled (SSE = 1) this control item defines the start of calculation of the vertical saw-
tooth, the east/west parabola and the vertical function required for the vertical modulated
output HD.

HPON

VPON

CON

PONRES

SDA 9361

Semiconductor Group

1998-02-01

Vertical Scan (width0 and width1)

The total width of this control item is 10 Bit. Therefore two registers (width0 and width1)
are necessary. If enabled (STE = 1) it defines the duration of the vertical scan. When the
vertical period has more lines than the sum of Start Vertical Scan and Vertical Scan,
the calculation of the vertical saw-tooth, the east/west parabola and the vertical parabola
required for HD stops so that the corresponding output signals remain unchanged till the
next vertical synchron pulse.

Guard Band

This control item is useful for optimizing self adaptation. Video signals with different
number of lines in consecutive fields (e. g. VCR search mode) must not start the
procedure of self adaptation. But switching between different TV standards has to
change the slope of the vertical saw-tooth getting always the same amplitude (self
adaptation). To avoid problems with flicker free TV systems which have alternating
number of lines per field an average value of four consecutive fields is calculated. If the
deviation of these average values (e.g. PAL: 312.5 lines or 625 half lines) is less or
equals Guard Band, no adaptation takes place. When it exceeds Guard Band, the
vertical slope will be changed.

Start Reduced Scan

If enabled (SRSE = 1) this item defines the start of the D/A conversion of the calculated
vertical saw-tooth. From begin of the vertical flyback to the line defined by Start
Reduced Scan the output signals VD+, VD- remain unchanged (flyback level). Other
outputs are not affected.

a) control bits VR1, VR0 # 00 (reduction of vertical size)

In this case the byte is useful for e.g. displaying 16/9 source format on 4/3 picture
tubes without visible RGB lines generated of the automatic cut-off control (partial
overscan). It defines the start of the reduced amplitude (factors 0.5, 0.66, 0.75) of the
vertical saw-tooth (refer page 39). When Start Reduced Scan = 0 the reduction
takes place over all lines including vertical flyback.

b) control bits VR1, VR0 = 00 (no reduction of vertical size)

If Start Reduced Scan > Start Vertical Scan the D/A conversion of the saw-tooth
starts (Start Reduced Scan - Start Vertical Scan) lines after begin of the
calculation. This causes a jump of the output voltage VD+, VD- from flyback to scan
level. It may be useful to hide the automatic cut-off control lines if no overscan is
desired (e.g. for VGA display). If Start Reduced Scan <= Start Vertical Scan this
byte has no effect.

SDA 9361

Semiconductor Group

1998-02-01

Vertical EHT Compensation

This item controls the influence of the beam current dependent input signal ABL on the
outputs VD+ and VD- according to the following equation:

(if RABL = 0)

(if RABL = 1)

VDPP

: variation of VD+ and VD- peak-to-peak voltage

ABL

: variation of ABL input voltage

The factor 0.57 depends on

REFP

REFH

REFL

If Vertical EHT Compensation = 0 the outputs VD+ and VD- are independent of
the input signal ABL.

Horizontal EHT Compensation

This item controls the influence of the input signal ABL on the output E/W according to
the following equation:

(if RABL = 0)

(if RABL = 1)

: variation of E/W output voltage

ABL

: variation of ABL input voltage

The factor 2.12 depends on

REFP

REFH

REFL

If Horizontal EHT Compensation = 0 the output E/W is independent of the input
signal ABL.

AFC EHT Compensation

Deviation of the horizontal phase caused by high beam current (e.g. white bar) can be
eliminated by this control item. The beam current dependent input signal ABL is
multiplied by AFC EHT Compensation.

VDPP

ABL

Vertical EHT compensation

512

------------------------------------------------------------------------ * 0,57

)

VDPP

ABL

Vertical EHT compensation

2048

------------------------------------------------------------------------ * 0,57

)

ABL

Horizontal EHT compensation

128

---------------------------------------------------------------------------------- * 2,12

)

ABL

Horizontal EHT compensation

512

---------------------------------------------------------------------------------- * 2,12

)

SDA 9361

Semiconductor Group

1998-02-01

Additional to the control items Vertical angle, Vertical bow and Horizontal shift, this
product influences the horizontal phase at the output HD according to the following
equation:

(if RABL = 0)

(if RABL = 1)

:variation of horizontal phase at the output HD
(positive values: shift left, negatives values: shift right)

ABL

:variation of ABL input voltage (units: Volt)

CLL

:864

The factor 52 depends on

REFP

Vertical Blanking Time (VBT)

VBT defines the vertical blanking pulse VBL which is part of the output signal SCP. VBL
is synchronized with the leading edge of HSYNC. It always starts and stops at the
beginning of line and never in the center.

a) Case of STE = 0

In this case the control item Vertical blanking time defines the duration of the
V-blanking pulse (VBL) exactly in number of lines. Because of IC internal limitations
16 through 127 lines can be blanked. If BSE = 0 the control item Vertical blanking
time is disabled and always 21 lines (default value if disabled) are blanked.
After power on the control bit BSE is 0. Therefore 21 lines will be blanked before any
programming of the IC. If Vertical Blanking Time is less or equals 21 lines, VBL
starts (point A in fig. above) always 0 ... 0.5 line (new odd field) or 0.5 ... 1 line (new
even field) prior to the vertical flyback. Otherwise VBL is concentric to a fictitious
vertical flyback period of 21 lines, that means VBL starts (VBT - 21) / 2 lines at the
end of an odd field or (VBT - 20) / 2 at the end of an even field prior to point A.
Possible start points are only the beginning of line.

ABL

AFC EHT compensation

---------------------------------------------------------------- *

)

CLL

-----------

ABL

AFC EHT compensation

256

---------------------------------------------------------------- *

)

CLL

-----------

SDA 9361

Semiconductor Group

1998-02-01

Field = Constant

b) Case of STE = 1

In this case the control item Vertical blanking time is an extension for the V-blanking
pulse.

- If BSE = 1 and VBT = 0 the V-blanking pulse has its minimum: it starts always at

end of scan (line B in Fig. below) and ends at start of scan (line C) defined by the
control items Start Vertical Scan (if SSE = 1) and Vertical Scan.

- BSE = 1 and (128 > VBT > 0) extend the V-blanking pulse according to the following

relationship
(If VBT > 127 this value is ignored and replaced by VBT - 128):
VBL starts VBT / 2 lines (even field) respectively (VBT + 1) / 2 lines (odd field)
prior to line B.
VBL ends (VBT + 1) / 2 lines (even field) respectively VBT / 2 lines (odd field) after
end of line C.
Possible start points are only the beginning of line.

- If BSE = 0 (after power on) the control item Vertical Blanking Time is disabled and

VBL starts 4 lines prior to end of scan (line B) and ends 4 lines after start of scan
(line C).

Figure 6
Vertical Blanking Pulse VBL when STE = 1

UED10262

~ ~

HSYNC

~ ~

VSYNC

VD-

VBL
(BSE = 0)

(BSE = 1,

VBL

VBT = 0)

VBT = 7)

(BSE = 1,

VBL

1 Line

Start of even Field

Start of odd Field

3 Lines

~ ~

4 Lines

3 Lines

4 Lines

Even

SDA 9361

Semiconductor Group

1998-02-01

Minimum Number of Lines per Field

It defines the minimum number of lines per field for the vertical synchronisation. If the TV
standard at the inputs VSYNC and HSYNC has less lines per field than defined by
Minimum Number of Lines per Field no synchronisation is possible.The relationship
between Minimum Number of Lines per Field

and the minimum number of lines is

given in the following table:

Maximum Number of Lines per Field

It defines the maximum number of lines per field for the vertical synchronisation. If the
TV standard at the inputs VSYNC and HSYNC has more lines per field than defined by
Maximum Number of Lines per Field no synchronisation is possible. The relationship
between Maximum Number of Lines per Field and the maximum number of lines is
given in the following table:

Minimum Number of Lines per Field

192

194

...

127

446

128

448

...

254

700

255

702

Maximum Number of Lines per Field

702

192

194

...

127

444

128

446

...

255

700

SDA 9361

Semiconductor Group

1998-02-01

Most Important V-Deflection Modes for 4:3 CRT

Mode

Description

Characteristics

Notes

VR1
VR0

NSA SRSE GBE STE SSE

N0 Normal mode

(for 4:3 source,
Letterbox)
with default
settings

Self adaptation
scan start = line 9
start of V-ramp = line 9
scan time: depends on source signal
guard band = 1.5 lines

Mode after
power on

N1 Normal mode

(for 4:3 source,
Letterbox)
with user
defined values

Self adaptation
scan start = Start Vertical Scan
if (Start Reduced Scan>Start Vertical Scan)

start of V-ramp = Start Reduced Scan

else

start of V-ramp = Start Vertical Scan

scan time: depends on source signal
guard band = Guard Band/2 [lines]

Start of scan
adjustable
start of
V-ramp
adjustable
guard band
adjustable

S0 Shrink

mode 75%
(for 16:9 source)
with default
settings

Self adaptation
scan start = line 9
start of reduced V-ramp = line 9
scan time: depends on source signal
guard band = 1.5 lines

S1 Shrink

mode 75%
(for 16:9 source)
with user
defined values

Self adaptation
scan start = Start Vertical Scan
if (Start Reduced Scan>Start Vertical Scan)

start of reduced V-ramp =

Start Reduced Scan

else

start of reduced V-ramp =

Start Vertical Scan

scan time: depends on source signal
guard band = Guard Band/2 [lines]

Start of scan
adjustable
start of
reduced
V-ramp
adjustable
guard band
adjustable

SDA 9361

Semiconductor Group

1998-02-01

Most Important V-Deflection Modes for 16:9 CRT

Mode

Description

Characteristics

Notes

VR1
VR0

NSA SRSE GBE STE SSE

N0 Normal mode

(for 16:9 or
4:3 source)
with default
settings

Self adaptation
scan start = line 9
start of V-ramp = line 9
scan time: depends on source signal
guard band = 1.5 lines

Mode after
power on

N1 Normal mode

(for 16:9 or
4:3 source)
with user
defined values

Self adaptation
scan start = Start Vertical Scan
if (Start Reduced Scan>Start Vertical Scan)

start of V-ramp = Start Reduced Scan

else

start of V-ramp = Start Vertical Scan

scan time: depends on source signal
guard band = Guard Band/2 [lines]

Start of scan
adjustable
start of
V-ramp
adjustable
guard band
adjustable

Zoom mode
(for 4:3 source,
Letterbox)

scan start =

(number_of_lines - Vertical Scan)/2 + 8

scan time = Vertical Scan

Vertical
scan
controls
zoom factor

SC Scroll mode

(for 4:3 source,
Letterbox)

Scan start =

(number_of_lines - Vertical Scan)/2 + 8
+ Start Vertical Scan

scan time = Vertical Scan

Like above;
Start vertical
scan can be
additionally
used for
adjustment
of picture
phase

Manual mode
(for 4:3 source,
Letterbox)

Scan start = Start Vertical Scan
scan time = Vertical Scan

Scan start
and
scan time
are
separately
adjustable

S2 Shrink

mode 66%
(for two
4:3 sources)
with default
settings

Self adaptation
scan start = line 9
start of reduced V-ramp = line 9
scan time: depends on source signal
guard band =1.5 lines

S3 Shrink

mode 50%
(for two
16:9 sources)
with default
settings

Self adaptation
scan start = line 9
start of reduced V-ramp = line 9
scan time: depends on source signal
guard band = 1.5 lines

SDA 9361

Semiconductor Group

1998-02-01

Absolute Maximum Ratings

Note: Absolute Maximum Ratings are those values beyond which damage to the device

may occur. Functional operation under these conditions or at any other condition
beyond those indicated in the operational sections of this specification is
not implied.

Between any internally non-connected supply pin of the same kind.
All

DD(D)

- and

DD(A)

- Pins are connected internally by about 3

The

SS(D)

-Pins are connected internally by about 3

Parameter

Symbol

Limit Values

Unit

Remark

min.

max.

Operating temperature

-20

°C

Storage temperature

stg

-40

125

°C

Junction temperature

125

°C

Soldering temperature

260

°C

Input voltage

- 0.3 V

+ 0.3 V

Output voltage

- 0.3 V

+ 0.3 V

Supply voltages

-0.3

Supply total voltage
differentials

-0.25

0.25

Total power dissipation

tot

0.85

Latch-up protection

-100

100

All inputs/outputs

SDA 9361

Semiconductor Group

1998-02-01

3.1

Recommended Operating Conditions

Parameter

Symbol

Limit Values

Unit

Remark

min.

nom.

max.

Supply voltages

4.5

5.5

Ambient temperature

-20

°C

For analog
parameters: 0°C

TTL Inputs: CLKI, VSYNC, TEST, FH1_2, SELFH1_2, CLEXT, SSD, VOFFD, RESN

H-input voltage

2.0

L-input voltage

0.8

Input VPROT

Threshold V1

1.4

1.5

1.6

REFP

= 4 V

Threshold V2

0.9

1.0

1.1

REFP

= 4 V

Input HPROT

Threshold V1

3.9

4.1

REFP

= 4 V

Threshold V2

2.1

2.4

2.7

REFP

= 4 V

Input ABL

L-input voltage

REFP

= 4 V

RABL = 0

REFP

= 4 V RABL = 1

Full range input
voltage

REFP

= 4 V

RABL = 0

REFP

= 4 V RABL = 1

Reference Voltage Input Pins (Internal Voltage Ref. Control Byte Reg 48H = 00000110)

REFP

input voltage

VREFP

REFH

input voltage

VREFH

2.5

REFL

input voltage

VREFL

1.2

REFN

input voltage

VREFN

REFC

input voltage

VREFC

Independent of
register 48

max =

SDA 9361

Semiconductor Group

1998-02-01

3.1

Recommended Operating Conditions (cont'd)

Parameter

Symbol

Limit Values

Unit

Remark

min.

nom.

max.

Input

L-input voltage

0.7

REFP

= 4 V

H-input voltage

2.0

REFP

= 4 V

Input HSYNC (CLEXT = 0)

Input voltage range

HSpp

See page 12

Input voltage low level

HSmin

See page 12

Input voltage high level

HSmax

See page 12

Pulse width
(HSWID = 0)

3.0

6.1

Low FH-range

1.5

3.1

High FH-range

Pulse width
(HSWID = 1)

3.0

8.8

Low FH-range

1.5

4.0

µs

High FH-range

Rise time

100

Input HSYNC (CLEXT = 1)

L-input voltage

0.8

H-input voltage

2.0

Setup time

Referred to falling
edge of CLKI

Hold time

Referred to falling
edge of CLKI

Input VSYNC

Pulse width high

100

100/

FH1_2 = 1, NI = 0

Pulse width high

200

100/

FH1_2 = 0, NI = 0

Pulse width high

1.5/

100/

NI = 1

SDA 9361

Semiconductor Group

1998-02-01

3.1

Recommended Operating Conditions (cont'd)

Parameter

Symbol

Limit Values

Unit

Remark

min.

nom.

max.

Input CLKI (External Clock Generation, CLEXT = High)

Input frequency

12.5

13.5

MHz

Low FH-range

MHz

High FH-range

Quartz Oscillator Input / Output X1, X2

Crystal frequency

24.576

MHz

Fundamental
crystal type,
e.g. Saronix
9922 520 00282

Crystal resonant
impedance

External capacitance

See Application
information

C Bus (All Values are Referred to min.(

) and max.(

)

High-level input
voltage

Low-level input
voltage

1.5

SCLK clock frequency

SCLK

400

kHz

Rise times of SCLK,
SDAT

0.3

SCLK

= 400 kHz

Fall times of SCLK,
SDAT

0.3

Set-up time DATA

SU;DAT

100

Hold time DATA

HD;DAT

Load capacitance

400

SDA 9361

Semiconductor Group

1998-02-01

3.2

Characteristics (Assuming Recommended Operating Conditions)

Parameter

Symbol

Limit Values

Unit

Remark

min.

nom.

max.

Average supply
current

150

Stand-by supply
current

Output Pins: SCAN, PWM

Output low level

0.4

= 1 mA

Output high level

2.8

= -1 mA

Input / Output SDAT

Output low level

0.6

= 6 mA

Output SCP

Output low level

= 1 mA

Output HBL level

OHBL

/ 2

-0.4 V

/ 2

+0.4 V

| = 100

Output high level

4.0

= -1 mA

DAC Output D/A

DAC resolution

Bit

DAC output low

REFP

= 4 V

DAC output high

3.953

REFP

= 4 V

Load capacitance

Output load

Offset error

-3 %

3 %

REFP

= 4 V

Gain error

-3 %

3 %

REFP

= 4 V

INL

-1

LSB

DNL

-0.5

0.5

LSB

DAC Output E/W

DAC resolution

Bit

Linear range:
100 ... 900

DAC output low

1.45

Input data = 100

SDA 9361

Semiconductor Group

1998-02-01

3.2

Characteristics (Assuming Recommended Operating Conditions)

(cont'd)

Parameter

Symbol

Limit Values

Unit

Remark

min.

nom.

max.

DAC output high

3.48

Input data = 900

Load capacitance

Output load

Zero error

-2 %

2 %

DAC output
voltage = 2.5 V

Gain error

-5 %

5 %

INL

-0.2 %

0.2 %

DNL

-0.1 %

0.1 %

REFH

= 2.5 V,

REFL

= 1.2 V

REFH

= 2.5 V,

REFL

= 1.2 V, Input range = 100 ... 900

DAC Output VD+, VD-

DAC resolution

Bit

Linear range:
1500 ... 15000

DAC output low (VD-)

1.44

Input data = 1500

DAC output high (VD-)

3.58

Input data = 15000

DAC output low
(VD-) - (VD+)

-2.12

Input data = 1500

DAC output high
(VD-) - (VD+)

2.16

Input data = 15000

Load capacitance

Output load

Zero error

-1 %

1 %

(VD-) - (VD+) = 0 V

Gain error

-5 %

5 %

INL

-0.5 %

0.5 %

DNL

Monotonous

Guaranteed by design

REFH

= 2.5 V,

REFL

= 1.2 V

REFH

= 2.5 V,

REFL

= 1.2 V, Input range = 1500 ... 15000

SDA 9361

Semiconductor Group

1998-02-01

3.2

Characteristics (Assuming Recommended Operating Conditions)

(cont'd)

Parameter

Symbol

Limit Values

Unit

Remark

min.

nom.

max.

Reference Output

REFP

(Adjustable by Reg 48

, Bit D7 ... D3)

(

Reg 48

, Bit D2 = 0, Bit D1 = 0)

Output voltage min

4.0

Bit D7 ... D3 = 10000

Output voltage max

4.0

Bit D7 ... D3 = 01111

Output current

-50

Reference Output

REFH

(Reg 48

, Bit D2 = 0)

Output voltage

2.4

2.5

2.6

REFP

= 4 V

Reference Output

REFL

(Reg 48

, Bit D2 = 0)

Output voltage

1.1

1.2

1.3

REFP

= 4 V

Output HD

Output low level

= 8 mA

Output high level

-1 V

= -8 mA

SDA 9361

Semiconductor Group

1998-02-01

5.3

Power On/Off Diagram

Figure 11

UED10283

REFH

Programmable

~ 42 Cycles

For low FH-range this time has to be multiplied by 2

Power On

Default

C Reg.

Active
Inactive

CPU

CLL

...

Active
Inactive

...

C Reg.

1E ,

Protection

REFL

De-

fault

Glitch

Power Off

Programmable

~ 42 Cycles

Default

Programmable

De-

fault

Programmable

fault

De-

fault

De-

SSD = 1: ~ 380

SSD = 0: ~ 250

C Registers 01

Tristate

REFP

C Bus

X1, X2

On-
Reset

Power-

Cycles

Voltage

Supply

SSD = 1: ~ 380

SSD = 0: ~ 250

Programmable

Ready

...

Tri-

state

Cycles

Programmable

Ready

C Registers 01

...

Tristate

,1F

SDA 9361

Semiconductor Group

1998-02-01

5.4

Standby Mode, RESN Diagram

Figure 12

UED10284

Active

REFL

Ready

Default Values

Programmable

Standby Mode

For low FH-range this time has to be multiplied by 2

...

C Reg.

Inactive

Programmable

C Bus

C Reg.

...

Protection

Default Values

External Reset

Values

Default

Programmable

Tristate

Programmable

Ready

Free Run

2-Loop

Active

Inactive

Active

Inactive

CPU

REFP

REFH

RESN

Standby

32 x 1

Cycles

2-Loop

~ 42 CLL Cycles

Run

~ 42 CLL Cycles

SSD = 0: ~ 250
SSD = 1: ~ 380

Free

SDA 9361

Semiconductor Group

1998-02-01

5.5

Function of H,V Protection

= 2 /

... 3 /

= 64 /

... 128 /

= 1 /

... 2 /

Depends on

C-control items

HPON or VPON = 1:HD = 0 (OFF)

HPROT

VPROT

Mode

SCP

HPON

C Bus

VPON

C Bus

Start up

Continuous
blanking

H, V
operation

EHT over-
voltage

Continuous
blanking
after

after

H operation
V short
failure

Continuous
blanking
after

SSC = 0

V longer
failure
H off
after

Continuous
blanking
after

SSC = 0

after

EHT
short over-
voltage

Continuous
blanking
after

after

V1
V2

t <

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SDA9361

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SDA9361

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SDA9361